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#include "spr_defs.h"
#include "board.h"
#include "mc.h"
 
 
 
        .extern _reset_support
        .extern _eth_int
        .extern _src_beg
        .extern _dst_beg
        .extern _dst_end
        .extern _c_reset
        .extern _int_main
        .extern _crc32
 
        /* Used by global.src_addr for default value */
        .extern _src_addr
 
        .global _lolev_ie
        .global _lolev_idis
        .global _align
        .global _calc_mycrc32
        .global _mycrc32
        .global _mysize
 
        .section .stack, "aw", @nobits
.space  STACK_SIZE
_stack:
                                .section .crc
_mycrc32:
        .word   0xcccccccc
_mysize:
        .word 0xdddddddd
 
.if SELF_CHECK
_calc_mycrc32:
        l.addi  r3,r0,0
        l.movhi r4,hi(_calc_mycrc32)
        l.ori   r4,r4,lo(_calc_mycrc32)
        l.movhi r5,hi(_mysize)
        l.ori   r5,r5,lo(_mysize)
        l.lwz   r5,0(r5)
        l.addi  r1,r1,-4
        l.sw    0(r1),r9
 
        /* unsigned long crc32 (unsigned long crc, const unsigned char *buf, unsigned long len); */
        l.jal           _crc32
        l.nop
 
        l.movhi r3,hi(_mycrc32)
        l.ori   r3,r3,lo(_mycrc32)
        l.lwz   r3,0(r3)
 
        l.xor     r11,r3,r11
        l.lwz   r9,0(r1)
        l.jr    r9
        l.addi  r1,r1,4
.endif
 
        .org 0x100
.if IN_FLASH
        .section .reset, "ax"
.else
        .section .vectors, "ax"
.endif
 
_reset:
.if IN_FLASH
        l.movhi r3,hi(MC_BASE_ADDR)
        l.ori   r3,r3,MC_BA_MASK
        l.addi  r5,r0,0x00
        l.sw    0(r3),r5
.endif
        l.movhi r3,hi(_start1)
        l.ori   r3,r3,lo(_start1)
        l.jr    r3
        l.nop
 
.if IN_FLASH
        .section .vectors, "ax"
        .org 0x600
.else
        .org (0x600 - 0x100 + _reset)
.endif
 
        l.j     _align
        l.nop
 
.if IN_FLASH
        .org 0x800
.else
        .org (0x800 - 0x100 + _reset)
.endif
 
        l.j     _int_wrapper
        l.nop
 
        .section .text
        l.nop
_start1:
        l.jal   _putc
.if IN_FLASH
        l.jal   _init_mc
        l.nop
 
        /* Wait for SDRAM */
        l.addi  r3,r0,0x0000  /* igor zmanjsal iz 0x7fff na 0x0000 */
1:      l.sfeqi r3,0
        l.bnf   1b
        l.addi  r3,r3,-1
.endif
        /* Copy form flash to sram */
.if IN_FLASH
        l.movhi r3,hi(_src_beg)
        l.ori   r3,r3,lo(_src_beg)
        l.movhi r4,hi(_vec_start)
        l.ori   r4,r4,lo(_vec_start)
        l.movhi r5,hi(_vec_end)
        l.ori   r5,r5,lo(_vec_end)
        l.sub   r5,r5,r4
        l.sfeqi r5,0
        l.bf    2f
        l.nop
1:      l.lwz   r6,0(r3)
        l.sw    0(r4),r6
        l.addi  r3,r3,4
        l.addi  r4,r4,4
        l.addi  r5,r5,-4
        l.sfgtsi r5,0
        l.bf    1b
        l.nop
2:
        l.movhi r4,hi(_dst_beg)
        l.ori   r4,r4,lo(_dst_beg)
        l.movhi r5,hi(_dst_end)
        l.ori   r5,r5,lo(_dst_end)
1:      l.sfgeu r4,r5
        l.bf    1f
        l.nop
        l.lwz   r8,0(r3)
        l.sw    0(r4),r8
        l.addi  r3,r3,4
        l.bnf   1b
        l.addi  r4,r4,4
1:
        l.addi  r3,r0,0
        l.addi  r4,r0,0
3:
.endif
 
.if IC_ENABLE
  l.jal _ic_enable
  l.nop
.endif
 
.if DC_ENABLE
  l.jal _dc_enable
  l.nop
.endif
 
        l.movhi r1,hi(_stack-4)
        l.addi  r1,r1,lo(_stack-4)
  l.addi  r2,r0,-3
  l.and r1,r1,r2
 
        l.movhi r2,hi(_main)
        l.ori   r2,r2,lo(_main)
        l.jr    r2
        l.addi  r2,r0,0
 
_ic_enable:
 
        /* Flush IC */
        l.addi  r10,r0,0
        l.addi  r11,r0,IC_SIZE
1:
        l.mtspr r0,r10,SPR_ICBIR
        l.sfne  r10,r11
        l.bf    1b
        l.addi  r10,r10,16
 
        /* Enable IC */
        l.addi  r10,r0,(SPR_SR_ICE|SPR_SR_SM)
        l.mtspr r0,r10,SPR_SR
        l.nop
        l.nop
        l.nop
        l.nop
        l.nop
 
  l.jr  r9
  l.nop
 
_dc_enable:
 
        /* Flush DC */
        l.addi  r10,r0,0
        l.addi  r11,r0,DC_SIZE
1:
        l.mtspr r0,r10,SPR_DCBIR
        l.sfne  r10,r11
        l.bf    1b
        l.addi  r10,r10,16
 
        /* Enable DC */
        l.addi  r10,r0,(SPR_SR_DCE|SPR_SR_SM)
        l.mtspr r0,r10,SPR_SR
 
  l.jr  r9
  l.nop
 
.if IN_FLASH
_init_mc:
 
        l.movhi r3,hi(MC_BASE_ADDR)
        l.ori   r3,r3,lo(MC_BASE_ADDR)
 
        l.addi  r4,r3,MC_CSC(0)
        l.movhi r5,hi(FLASH_BASE_ADDR)
        l.srai  r5,r5,5
        l.ori   r5,r5,0x0025
        l.sw    0(r4),r5
 
        l.addi  r4,r3,MC_TMS(0)
        l.movhi r5,hi(FLASH_TMS_VAL)
        l.ori   r5,r5,lo(FLASH_TMS_VAL)
        l.sw    0(r4),r5
 
        l.addi  r4,r3,MC_BA_MASK
        l.addi  r5,r0,MC_MASK_VAL
        l.sw    0(r4),r5
 
        l.addi  r4,r3,MC_CSR
        l.movhi r5,hi(MC_CSR_VAL)
        l.ori   r5,r5,lo(MC_CSR_VAL)
        l.sw    0(r4),r5
 
        l.addi  r4,r3,MC_TMS(1)
        l.movhi r5,hi(SDRAM_TMS_VAL)
        l.ori   r5,r5,lo(SDRAM_TMS_VAL)
        l.sw    0(r4),r5
 
        l.addi  r4,r3,MC_CSC(1)
        l.movhi r5,hi(SDRAM_BASE_ADDR)
        l.srai  r5,r5,5
        l.ori   r5,r5,0x0411
        l.sw    0(r4),r5
 
        l.jr    r9
        l.nop
.endif
 
_int_wrapper:
        l.addi  r1,r1,-128
 
        l.sw    0x4(r1),r2
        l.sw    0x8(r1),r4
        l.sw    0xc(r1),r5
        l.sw    0x10(r1),r6
        l.sw    0x14(r1),r7
        l.sw    0x18(r1),r8
        l.sw    0x1c(r1),r9
        l.sw    0x20(r1),r10
        l.sw    0x24(r1),r11
        l.sw    0x28(r1),r12
        l.sw    0x2c(r1),r13
        l.sw    0x30(r1),r14
        l.sw    0x34(r1),r15
        l.sw    0x38(r1),r16
        l.sw    0x3c(r1),r17
        l.sw    0x40(r1),r18
        l.sw    0x44(r1),r19
        l.sw    0x48(r1),r20
        l.sw    0x4c(r1),r21
        l.sw    0x50(r1),r22
        l.sw    0x54(r1),r23
        l.sw    0x58(r1),r24
        l.sw    0x5c(r1),r25
        l.sw    0x60(r1),r26
        l.sw    0x64(r1),r27
        l.sw    0x68(r1),r28
        l.sw    0x6c(r1),r29
        l.sw    0x70(r1),r30
        l.sw    0x74(r1),r31
        l.sw    0x78(r1),r3
 
        l.movhi r3,hi(_eth_int)
        l.ori   r3,r3,lo(_eth_int)
        l.jalr  r3
        l.nop
 
        l.lwz   r2,0x4(r1)
        l.lwz   r4,0x8(r1)
        l.lwz   r5,0xc(r1)
        l.lwz   r6,0x10(r1)
        l.lwz   r7,0x14(r1)
        l.lwz   r8,0x18(r1)
        l.lwz   r9,0x1c(r1)
        l.lwz   r10,0x20(r1)
        l.lwz   r11,0x24(r1)
        l.lwz   r12,0x28(r1)
        l.lwz   r13,0x2c(r1)
        l.lwz   r14,0x30(r1)
        l.lwz   r15,0x34(r1)
        l.lwz   r16,0x38(r1)
        l.lwz   r17,0x3c(r1)
        l.lwz   r18,0x40(r1)
        l.lwz   r19,0x44(r1)
        l.lwz   r20,0x48(r1)
        l.lwz   r21,0x4c(r1)
        l.lwz   r22,0x50(r1)
        l.lwz   r23,0x54(r1)
        l.lwz   r24,0x58(r1)
        l.lwz   r25,0x5c(r1)
        l.lwz   r26,0x60(r1)
        l.lwz   r27,0x64(r1)
        l.lwz   r28,0x68(r1)
        l.lwz   r29,0x6c(r1)
        l.lwz   r30,0x70(r1)
        l.lwz   r31,0x74(r1)
#        l.lwz   r3,0x78(r1)
 
        l.mtspr r0,r0,SPR_PICSR
 
        l.mfspr r3,r0,SPR_ESR_BASE
        l.ori   r3,r3,SPR_SR_IEE
        l.mtspr r0,r3,SPR_ESR_BASE
 
        l.lwz   r3,0x78(r1)
 
        l.addi  r1,r1,128
        l.rfe
        l.nop
 
_align:
        l.addi  r1,r1,-128
        l.sw    0x08(r1),r2
        l.sw    0x0c(r1),r3
        l.sw    0x10(r1),r4
        l.sw    0x14(r1),r5
        l.sw    0x18(r1),r6
        l.sw    0x1c(r1),r7
        l.sw    0x20(r1),r8
        l.sw    0x24(r1),r9
        l.sw    0x28(r1),r10
        l.sw    0x2c(r1),r11
        l.sw    0x30(r1),r12
        l.sw    0x34(r1),r13
        l.sw    0x38(r1),r14
        l.sw    0x3c(r1),r15
        l.sw    0x40(r1),r16
        l.sw    0x44(r1),r17
        l.sw    0x48(r1),r18
        l.sw    0x4c(r1),r19
        l.sw    0x50(r1),r20
        l.sw    0x54(r1),r21
        l.sw    0x58(r1),r22
        l.sw    0x5c(r1),r23
        l.sw    0x60(r1),r24
        l.sw    0x64(r1),r25
        l.sw    0x68(r1),r26
        l.sw    0x6c(r1),r27
        l.sw    0x70(r1),r28
        l.sw    0x74(r1),r29
        l.sw    0x78(r1),r30
        l.sw    0x7c(r1),r31
 
        l.mfspr r2,r0,SPR_EEAR_BASE /* Load the efective addres */
        l.mfspr r5,r0,SPR_EPCR_BASE /* Load the insn address */
 
        l.lwz r3,0(r5)      /* Load insn */
        l.srli  r4,r3,26    /* Shift left to get the insn opcode */
 
        l.sfeqi r4,0x00     /* Check if the load/store insn is in delay slot */
        l.bf  jmp
        l.sfeqi r4,0x01
        l.bf  jmp
        l.sfeqi r4,0x03
        l.bf  jmp
        l.sfeqi r4,0x04
        l.bf  jmp
        l.sfeqi r4,0x11
        l.bf  jr
        l.sfeqi r4,0x12
        l.bf  jr
        l.nop
        l.j 1f
        l.addi  r5,r5,4     /* Increment PC to get return insn address */
 
jmp:
        l.slli  r4,r3,6     /* Get the signed extended jump length */
        l.srai  r4,r4,4
 
        l.lwz r3,4(r5)      /* Load the real load/store insn */
 
        l.add r5,r5,r4      /* Calculate jump target address */
 
        l.j 1f
        l.srli  r4,r3,26    /* Shift left to get the insn opcode */
 
jr:
        l.slli  r4,r3,9     /* Shift to get the reg nb */
        l.andi  r4,r4,0x7c
 
        l.lwz r3,4(r5)    /* Load the real load/store insn */
 
        l.add r4,r4,r1    /* Load the jump register value from the stack */
        l.lwz r5,0(r4)
 
        l.srli  r4,r3,26    /* Shift left to get the insn opcode */
 
 
1:      l.mtspr r0,r5,SPR_EPCR_BASE
 
        l.sfeqi r4,0x26
        l.bf  lhs
        l.sfeqi r4,0x25
        l.bf  lhz
        l.sfeqi r4,0x22
        l.bf  lws
        l.sfeqi r4,0x21
        l.bf  lwz
        l.sfeqi r4,0x37
        l.bf  sh
        l.sfeqi r4,0x35
        l.bf  sw
        l.nop
 
1:      l.j 1b      /* I don't know what to do */
        l.nop
 
lhs:    l.lbs r5,0(r2)
        l.slli  r5,r5,8
        l.lbz r6,1(r2)
        l.or  r5,r5,r6
        l.srli  r4,r3,19
        l.andi  r4,r4,0x7c
        l.add r4,r4,r1
        l.j align_end
        l.sw  0(r4),r5
 
lhz:    l.lbz r5,0(r2)
        l.slli  r5,r5,8
        l.lbz r6,1(r2)
        l.or  r5,r5,r6
        l.srli  r4,r3,19
        l.andi  r4,r4,0x7c
        l.add r4,r4,r1
        l.j align_end
        l.sw  0(r4),r5
 
lws:    l.lbs r5,0(r2)
        l.slli  r5,r5,24
        l.lbz r6,1(r2)
        l.slli  r6,r6,16
        l.or  r5,r5,r6
        l.lbz r6,2(r2)
        l.slli  r6,r6,8
        l.or  r5,r5,r6
        l.lbz r6,3(r2)
        l.or  r5,r5,r6
        l.srli  r4,r3,19
        l.andi  r4,r4,0x7c
        l.add r4,r4,r1
        l.j align_end
        l.sw  0(r4),r5
 
lwz:    l.lbz r5,0(r2)
        l.slli  r5,r5,24
        l.lbz r6,1(r2)
        l.slli  r6,r6,16
        l.or  r5,r5,r6
        l.lbz r6,2(r2)
        l.slli  r6,r6,8
        l.or  r5,r5,r6
        l.lbz r6,3(r2)
        l.or  r5,r5,r6
        l.srli  r4,r3,19
        l.andi  r4,r4,0x7c
        l.add r4,r4,r1
        l.j align_end
        l.sw  0(r4),r5
 
sh:
        l.srli  r4,r3,9
        l.andi  r4,r4,0x7c
        l.add r4,r4,r1
        l.lwz r5,0(r4)
        l.sb  1(r2),r5
        l.slli  r5,r5,8
        l.j align_end
        l.sb  0(r2),r5
 
sw:
        l.srli  r4,r3,9
        l.andi  r4,r4,0x7c
        l.add r4,r4,r1
        l.lwz r5,0(r4)
        l.sb  3(r2),r5
        l.slli  r5,r5,8
        l.sb  2(r2),r5
        l.slli  r5,r5,8
        l.sb  1(r2),r5
        l.slli  r5,r5,8
        l.j align_end
        l.sb  0(r2),r5
 
align_end:
        l.lwz   r2,0x08(r1)
        l.lwz   r3,0x0c(r1)
        l.lwz   r4,0x10(r1)
        l.lwz   r5,0x14(r1)
        l.lwz   r6,0x18(r1)
        l.lwz   r7,0x1c(r1)
        l.lwz   r8,0x20(r1)
        l.lwz   r9,0x24(r1)
        l.lwz   r10,0x28(r1)
        l.lwz   r11,0x2c(r1)
        l.lwz   r12,0x30(r1)
        l.lwz   r13,0x34(r1)
        l.lwz   r14,0x38(r1)
        l.lwz   r15,0x3c(r1)
        l.lwz   r16,0x40(r1)
        l.lwz   r17,0x44(r1)
        l.lwz   r18,0x48(r1)
        l.lwz   r19,0x4c(r1)
        l.lwz   r20,0x50(r1)
        l.lwz   r21,0x54(r1)
        l.lwz   r22,0x58(r1)
        l.lwz   r23,0x5c(r1)
        l.lwz   r24,0x60(r1)
        l.lwz   r25,0x64(r1)
        l.lwz   r26,0x68(r1)
        l.lwz   r27,0x6c(r1)
        l.lwz   r28,0x70(r1)
        l.lwz   r29,0x74(r1)
        l.lwz   r30,0x78(r1)
        l.lwz   r31,0x7c(r1)
        l.addi  r1,r1,128
        l.rfe
 
        .section .text
_lolev_ie:
        l.mfspr r3,r0,SPR_SR
        l.ori   r3,r3,SPR_SR_IEE
        l.mtspr r0,r3,SPR_SR
        l.movhi r3,hi(ETH0_INT)
  l.ori r3,r3,lo(ETH0_INT)
        l.mtspr r0,r3,SPR_PICMR
 
        l.jr    r9
        l.nop
 
_lolev_idis:
        l.mtspr r0,r0,SPR_PICMR
 
        l.jr    r9
        l.nop

Line No.	Rev	Author	Line
1	809	simons	`#include "spr_defs.h"`
2			`#include "board.h"`
3			`#include "mc.h"`
4
5
6
7			`.extern _reset_support`
8			`.extern _eth_int`
9			`.extern _src_beg`
10			`.extern _dst_beg`
11			`.extern _dst_end`
12			`.extern _c_reset`
13			`.extern _int_main`
14	820	markom	`.extern _crc32`
15	816	markom
16			`/* Used by global.src_addr for default value */`
17			`.extern _src_addr`
18	809	simons
19			`.global _lolev_ie`
20			`.global _lolev_idis`
21	817	simons	`.global _align`
22	820	markom	`.global _calc_mycrc32`
23	822	markom	`.global _mycrc32`
24			`.global _mysize`
25	809	simons
26	817	simons	`.section .stack, "aw", @nobits`
27			`.space STACK_SIZE`
28	809	simons	`_stack:`
29	820	markom	`.section .crc`
30			`_mycrc32:`
31			`.word 0xcccccccc`
32			`_mysize:`
33			`.word 0xdddddddd`
34	809	simons
35	829	markom	`.if SELF_CHECK`
36	820	markom	`_calc_mycrc32:`
37	828	markom	`l.addi r3,r0,0`
38	820	markom	`l.movhi r4,hi(_calc_mycrc32)`
39			`l.ori r4,r4,lo(_calc_mycrc32)`
40			`l.movhi r5,hi(_mysize)`
41			`l.ori r5,r5,lo(_mysize)`
42			`l.lwz r5,0(r5)`
43	822	markom	`l.addi r1,r1,-4`
44	828	markom	`l.sw 0(r1),r9`
45	820	markom
46			`/* unsigned long crc32 (unsigned long crc, const unsigned char buf, unsigned long len); /`
47	828	markom	`l.jal _crc32`
48			`l.nop`
49	820	markom
50	828	markom	`l.movhi r3,hi(_mycrc32)`
51	820	markom	`l.ori r3,r3,lo(_mycrc32)`
52			`l.lwz r3,0(r3)`
53
54	822	markom	`l.xor r11,r3,r11`
55			`l.lwz r9,0(r1)`
56			`l.jr r9`
57			`l.addi r1,r1,4`
58	829	markom	`.endif`
59
60	828	markom	`.org 0x100`
61	809	simons	`.if IN_FLASH`
62			`.section .reset, "ax"`
63			`.else`
64	817	simons	`.section .vectors, "ax"`
65	809	simons	`.endif`
66
67			`_reset:`
68			`.if IN_FLASH`
69	817	simons	`l.movhi r3,hi(MC_BASE_ADDR)`
70	809	simons	`l.ori r3,r3,MC_BA_MASK`
71			`l.addi r5,r0,0x00`
72			`l.sw 0(r3),r5`
73			`.endif`
74	824	markom	`l.movhi r3,hi(_start1)`
75			`l.ori r3,r3,lo(_start1)`
76	829	markom	`l.jr r3`
77			`l.nop`
78	809	simons
79			`.if IN_FLASH`
80			`.section .vectors, "ax"`
81	824	markom	`.org 0x600`
82			`.else`
83			`.org (0x600 - 0x100 + _reset)`
84	809	simons	`.endif`
85
86	817	simons	`l.j _align`
87			`l.nop`
88
89	824	markom	`.if IN_FLASH`
90	817	simons	`.org 0x800`
91	824	markom	`.else`
92			`.org (0x800 - 0x100 + _reset)`
93			`.endif`
94	817	simons
95	809	simons	`l.j _int_wrapper`
96			`l.nop`
97
98			`.section .text`
99	829	markom	`l.nop`
100	824	markom	`_start1:`
101	828	markom	`l.jal _putc`
102	809	simons	`.if IN_FLASH`
103			`l.jal _init_mc`
104			`l.nop`
105
106			`/* Wait for SDRAM */`
107			`l.addi r3,r0,0x0000 /* igor zmanjsal iz 0x7fff na 0x0000 */`
108			`1: l.sfeqi r3,0`
109			`l.bnf 1b`
110			`l.addi r3,r3,-1`
111			`.endif`
112	817	simons	`/* Copy form flash to sram */`
113	809	simons	`.if IN_FLASH`
114			`l.movhi r3,hi(_src_beg)`
115			`l.ori r3,r3,lo(_src_beg)`
116			`l.movhi r4,hi(_vec_start)`
117			`l.ori r4,r4,lo(_vec_start)`
118			`l.movhi r5,hi(_vec_end)`
119			`l.ori r5,r5,lo(_vec_end)`
120			`l.sub r5,r5,r4`
121			`l.sfeqi r5,0`
122			`l.bf 2f`
123			`l.nop`
124			`1: l.lwz r6,0(r3)`
125			`l.sw 0(r4),r6`
126			`l.addi r3,r3,4`
127			`l.addi r4,r4,4`
128			`l.addi r5,r5,-4`
129			`l.sfgtsi r5,0`
130	817	simons	`l.bf 1b`
131	809	simons	`l.nop`
132			`2:`
133			`l.movhi r4,hi(_dst_beg)`
134			`l.ori r4,r4,lo(_dst_beg)`
135			`l.movhi r5,hi(_dst_end)`
136			`l.ori r5,r5,lo(_dst_end)`
137			`1: l.sfgeu r4,r5`
138			`l.bf 1f`
139			`l.nop`
140			`l.lwz r8,0(r3)`
141			`l.sw 0(r4),r8`
142			`l.addi r3,r3,4`
143			`l.bnf 1b`
144			`l.addi r4,r4,4`
145			`1:`
146			`l.addi r3,r0,0`
147			`l.addi r4,r0,0`
148			`3:`
149			`.endif`
150
151			`.if IC_ENABLE`
152	817	simons	`l.jal _ic_enable`
153			`l.nop`
154	809	simons	`.endif`
155
156			`.if DC_ENABLE`
157	817	simons	`l.jal _dc_enable`
158			`l.nop`
159	809	simons	`.endif`
160
161			`l.movhi r1,hi(_stack-4)`
162			`l.addi r1,r1,lo(_stack-4)`
163	817	simons	`l.addi r2,r0,-3`
164			`l.and r1,r1,r2`
165	809	simons
166			`l.movhi r2,hi(_main)`
167			`l.ori r2,r2,lo(_main)`
168			`l.jr r2`
169			`l.addi r2,r0,0`
170
171			`_ic_enable:`
172
173			`/* Flush IC */`
174			`l.addi r10,r0,0`
175			`l.addi r11,r0,IC_SIZE`
176			`1:`
177			`l.mtspr r0,r10,SPR_ICBIR`
178			`l.sfne r10,r11`
179			`l.bf 1b`
180			`l.addi r10,r10,16`
181
182			`/* Enable IC */`
183			`l.addi r10,r0,(SPR_SR_ICE\|SPR_SR_SM)`
184			`l.mtspr r0,r10,SPR_SR`
185			`l.nop`
186			`l.nop`
187			`l.nop`
188			`l.nop`
189			`l.nop`
190
191	817	simons	`l.jr r9`
192			`l.nop`
193	809	simons
194			`_dc_enable:`
195
196			`/* Flush DC */`
197			`l.addi r10,r0,0`
198			`l.addi r11,r0,DC_SIZE`
199			`1:`
200			`l.mtspr r0,r10,SPR_DCBIR`
201			`l.sfne r10,r11`
202			`l.bf 1b`
203			`l.addi r10,r10,16`
204
205			`/* Enable DC */`
206			`l.addi r10,r0,(SPR_SR_DCE\|SPR_SR_SM)`
207			`l.mtspr r0,r10,SPR_SR`
208
209	817	simons	`l.jr r9`
210			`l.nop`
211	809	simons
212			`.if IN_FLASH`
213			`_init_mc:`
214
215	817	simons	`l.movhi r3,hi(MC_BASE_ADDR)`
216			`l.ori r3,r3,lo(MC_BASE_ADDR)`
217	809	simons
218			`l.addi r4,r3,MC_CSC(0)`
219	817	simons	`l.movhi r5,hi(FLASH_BASE_ADDR)`
220	809	simons	`l.srai r5,r5,5`
221			`l.ori r5,r5,0x0025`
222			`l.sw 0(r4),r5`
223
224			`l.addi r4,r3,MC_TMS(0)`
225			`l.movhi r5,hi(FLASH_TMS_VAL)`
226			`l.ori r5,r5,lo(FLASH_TMS_VAL)`
227			`l.sw 0(r4),r5`
228
229			`l.addi r4,r3,MC_BA_MASK`
230			`l.addi r5,r0,MC_MASK_VAL`
231			`l.sw 0(r4),r5`
232
233			`l.addi r4,r3,MC_CSR`
234			`l.movhi r5,hi(MC_CSR_VAL)`
235			`l.ori r5,r5,lo(MC_CSR_VAL)`
236			`l.sw 0(r4),r5`
237
238			`l.addi r4,r3,MC_TMS(1)`
239			`l.movhi r5,hi(SDRAM_TMS_VAL)`
240			`l.ori r5,r5,lo(SDRAM_TMS_VAL)`
241			`l.sw 0(r4),r5`
242
243			`l.addi r4,r3,MC_CSC(1)`
244	817	simons	`l.movhi r5,hi(SDRAM_BASE_ADDR)`
245	809	simons	`l.srai r5,r5,5`
246			`l.ori r5,r5,0x0411`
247			`l.sw 0(r4),r5`
248
249			`l.jr r9`
250			`l.nop`
251			`.endif`
252
253			`_int_wrapper:`
254			`l.addi r1,r1,-128`
255
256			`l.sw 0x4(r1),r2`
257			`l.sw 0x8(r1),r4`
258			`l.sw 0xc(r1),r5`
259			`l.sw 0x10(r1),r6`
260			`l.sw 0x14(r1),r7`
261			`l.sw 0x18(r1),r8`
262			`l.sw 0x1c(r1),r9`
263			`l.sw 0x20(r1),r10`
264			`l.sw 0x24(r1),r11`
265			`l.sw 0x28(r1),r12`
266			`l.sw 0x2c(r1),r13`
267			`l.sw 0x30(r1),r14`
268			`l.sw 0x34(r1),r15`
269			`l.sw 0x38(r1),r16`
270			`l.sw 0x3c(r1),r17`
271			`l.sw 0x40(r1),r18`
272			`l.sw 0x44(r1),r19`
273			`l.sw 0x48(r1),r20`
274			`l.sw 0x4c(r1),r21`
275			`l.sw 0x50(r1),r22`
276			`l.sw 0x54(r1),r23`
277			`l.sw 0x58(r1),r24`
278			`l.sw 0x5c(r1),r25`
279			`l.sw 0x60(r1),r26`
280			`l.sw 0x64(r1),r27`
281			`l.sw 0x68(r1),r28`
282			`l.sw 0x6c(r1),r29`
283			`l.sw 0x70(r1),r30`
284			`l.sw 0x74(r1),r31`
285			`l.sw 0x78(r1),r3`
286
287			`l.movhi r3,hi(_eth_int)`
288			`l.ori r3,r3,lo(_eth_int)`
289			`l.jalr r3`
290			`l.nop`
291
292			`l.lwz r2,0x4(r1)`
293			`l.lwz r4,0x8(r1)`
294			`l.lwz r5,0xc(r1)`
295			`l.lwz r6,0x10(r1)`
296			`l.lwz r7,0x14(r1)`
297			`l.lwz r8,0x18(r1)`
298			`l.lwz r9,0x1c(r1)`
299			`l.lwz r10,0x20(r1)`
300			`l.lwz r11,0x24(r1)`
301			`l.lwz r12,0x28(r1)`
302			`l.lwz r13,0x2c(r1)`
303			`l.lwz r14,0x30(r1)`
304			`l.lwz r15,0x34(r1)`
305			`l.lwz r16,0x38(r1)`
306			`l.lwz r17,0x3c(r1)`
307			`l.lwz r18,0x40(r1)`
308			`l.lwz r19,0x44(r1)`
309			`l.lwz r20,0x48(r1)`
310			`l.lwz r21,0x4c(r1)`
311			`l.lwz r22,0x50(r1)`
312			`l.lwz r23,0x54(r1)`
313			`l.lwz r24,0x58(r1)`
314			`l.lwz r25,0x5c(r1)`
315			`l.lwz r26,0x60(r1)`
316			`l.lwz r27,0x64(r1)`
317			`l.lwz r28,0x68(r1)`
318			`l.lwz r29,0x6c(r1)`
319			`l.lwz r30,0x70(r1)`
320			`l.lwz r31,0x74(r1)`
321			`# l.lwz r3,0x78(r1)`
322
323			`l.mtspr r0,r0,SPR_PICSR`
324
325			`l.mfspr r3,r0,SPR_ESR_BASE`
326			`l.ori r3,r3,SPR_SR_IEE`
327			`l.mtspr r0,r3,SPR_ESR_BASE`
328
329			`l.lwz r3,0x78(r1)`
330
331			`l.addi r1,r1,128`
332			`l.rfe`
333			`l.nop`
334
335	817	simons	`_align:`
336			`l.addi r1,r1,-128`
337			`l.sw 0x08(r1),r2`
338			`l.sw 0x0c(r1),r3`
339			`l.sw 0x10(r1),r4`
340			`l.sw 0x14(r1),r5`
341			`l.sw 0x18(r1),r6`
342			`l.sw 0x1c(r1),r7`
343			`l.sw 0x20(r1),r8`
344			`l.sw 0x24(r1),r9`
345			`l.sw 0x28(r1),r10`
346			`l.sw 0x2c(r1),r11`
347			`l.sw 0x30(r1),r12`
348			`l.sw 0x34(r1),r13`
349			`l.sw 0x38(r1),r14`
350			`l.sw 0x3c(r1),r15`
351			`l.sw 0x40(r1),r16`
352			`l.sw 0x44(r1),r17`
353			`l.sw 0x48(r1),r18`
354			`l.sw 0x4c(r1),r19`
355			`l.sw 0x50(r1),r20`
356			`l.sw 0x54(r1),r21`
357			`l.sw 0x58(r1),r22`
358			`l.sw 0x5c(r1),r23`
359			`l.sw 0x60(r1),r24`
360			`l.sw 0x64(r1),r25`
361			`l.sw 0x68(r1),r26`
362			`l.sw 0x6c(r1),r27`
363			`l.sw 0x70(r1),r28`
364			`l.sw 0x74(r1),r29`
365			`l.sw 0x78(r1),r30`
366			`l.sw 0x7c(r1),r31`
367
368			`l.mfspr r2,r0,SPR_EEAR_BASE /* Load the efective addres */`
369			`l.mfspr r5,r0,SPR_EPCR_BASE /* Load the insn address */`
370
371			`l.lwz r3,0(r5) /* Load insn */`
372			`l.srli r4,r3,26 /* Shift left to get the insn opcode */`
373
374			`l.sfeqi r4,0x00 /* Check if the load/store insn is in delay slot */`
375			`l.bf jmp`
376			`l.sfeqi r4,0x01`
377			`l.bf jmp`
378			`l.sfeqi r4,0x03`
379			`l.bf jmp`
380			`l.sfeqi r4,0x04`
381			`l.bf jmp`
382			`l.sfeqi r4,0x11`
383			`l.bf jr`
384			`l.sfeqi r4,0x12`
385			`l.bf jr`
386			`l.nop`
387			`l.j 1f`
388			`l.addi r5,r5,4 /* Increment PC to get return insn address */`
389
390			`jmp:`
391			`l.slli r4,r3,6 /* Get the signed extended jump length */`
392			`l.srai r4,r4,4`
393
394			`l.lwz r3,4(r5) /* Load the real load/store insn */`
395
396			`l.add r5,r5,r4 /* Calculate jump target address */`
397
398			`l.j 1f`
399			`l.srli r4,r3,26 /* Shift left to get the insn opcode */`
400
401			`jr:`
402			`l.slli r4,r3,9 /* Shift to get the reg nb */`
403			`l.andi r4,r4,0x7c`
404
405			`l.lwz r3,4(r5) /* Load the real load/store insn */`
406
407			`l.add r4,r4,r1 /* Load the jump register value from the stack */`
408			`l.lwz r5,0(r4)`
409
410			`l.srli r4,r3,26 /* Shift left to get the insn opcode */`
411
412
413			`1: l.mtspr r0,r5,SPR_EPCR_BASE`
414
415			`l.sfeqi r4,0x26`
416			`l.bf lhs`
417			`l.sfeqi r4,0x25`
418			`l.bf lhz`
419			`l.sfeqi r4,0x22`
420			`l.bf lws`
421			`l.sfeqi r4,0x21`
422			`l.bf lwz`
423			`l.sfeqi r4,0x37`
424			`l.bf sh`
425			`l.sfeqi r4,0x35`
426			`l.bf sw`
427			`l.nop`
428
429			`1: l.j 1b /* I don't know what to do */`
430			`l.nop`
431
432			`lhs: l.lbs r5,0(r2)`
433			`l.slli r5,r5,8`
434			`l.lbz r6,1(r2)`
435			`l.or r5,r5,r6`
436			`l.srli r4,r3,19`
437			`l.andi r4,r4,0x7c`
438			`l.add r4,r4,r1`
439			`l.j align_end`
440			`l.sw 0(r4),r5`
441
442			`lhz: l.lbz r5,0(r2)`
443			`l.slli r5,r5,8`
444			`l.lbz r6,1(r2)`
445			`l.or r5,r5,r6`
446			`l.srli r4,r3,19`
447			`l.andi r4,r4,0x7c`
448			`l.add r4,r4,r1`
449			`l.j align_end`
450			`l.sw 0(r4),r5`
451
452			`lws: l.lbs r5,0(r2)`
453			`l.slli r5,r5,24`
454			`l.lbz r6,1(r2)`
455			`l.slli r6,r6,16`
456			`l.or r5,r5,r6`
457			`l.lbz r6,2(r2)`
458			`l.slli r6,r6,8`
459			`l.or r5,r5,r6`
460			`l.lbz r6,3(r2)`
461			`l.or r5,r5,r6`
462			`l.srli r4,r3,19`
463			`l.andi r4,r4,0x7c`
464			`l.add r4,r4,r1`
465			`l.j align_end`
466			`l.sw 0(r4),r5`
467
468			`lwz: l.lbz r5,0(r2)`
469			`l.slli r5,r5,24`
470			`l.lbz r6,1(r2)`
471			`l.slli r6,r6,16`
472			`l.or r5,r5,r6`
473			`l.lbz r6,2(r2)`
474			`l.slli r6,r6,8`
475			`l.or r5,r5,r6`
476			`l.lbz r6,3(r2)`
477			`l.or r5,r5,r6`
478			`l.srli r4,r3,19`
479			`l.andi r4,r4,0x7c`
480			`l.add r4,r4,r1`
481			`l.j align_end`
482			`l.sw 0(r4),r5`
483
484			`sh:`
485			`l.srli r4,r3,9`
486			`l.andi r4,r4,0x7c`
487			`l.add r4,r4,r1`
488			`l.lwz r5,0(r4)`
489			`l.sb 1(r2),r5`
490			`l.slli r5,r5,8`
491			`l.j align_end`
492			`l.sb 0(r2),r5`
493
494			`sw:`
495			`l.srli r4,r3,9`
496			`l.andi r4,r4,0x7c`
497			`l.add r4,r4,r1`
498			`l.lwz r5,0(r4)`
499			`l.sb 3(r2),r5`
500			`l.slli r5,r5,8`

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