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jcastillo |
//////////////////////////////////////////////////////////////////////
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//// ////
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//// dbg_tb.v ////
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//// ////
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//// ////
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//// This file is part of the SoC Debug Interface. ////
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//// http://www.opencores.org/projects/DebugInterface/ ////
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//// ////
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//// Author(s): ////
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//// Igor Mohor (igorm@opencores.org) ////
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//// ////
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//// ////
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//// All additional information is avaliable in the README.txt ////
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//// file. ////
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//// ////
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//////////////////////////////////////////////////////////////////////
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//// ////
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//// Copyright (C) 2000 - 2004 Authors ////
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//// ////
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//// This source file may be used and distributed without ////
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//// restriction provided that this copyright statement is not ////
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//// removed from the file and that any derivative work contains ////
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//// the original copyright notice and the associated disclaimer. ////
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//// ////
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//// This source file is free software; you can redistribute it ////
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//// and/or modify it under the terms of the GNU Lesser General ////
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//// Public License as published by the Free Software Foundation; ////
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//// either version 2.1 of the License, or (at your option) any ////
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//// later version. ////
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//// ////
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//// This source is distributed in the hope that it will be ////
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//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
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//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
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//// PURPOSE. See the GNU Lesser General Public License for more ////
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//// details. ////
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//// ////
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//// You should have received a copy of the GNU Lesser General ////
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//// Public License along with this source; if not, download it ////
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//// from http://www.opencores.org/lgpl.shtml ////
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//// ////
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//////////////////////////////////////////////////////////////////////
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//
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// CVS Revision History
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//
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// $Log: not supported by cvs2svn $
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// Revision 1.45 2004/04/01 12:50:19 igorm
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// Support for 2 CPUs added.
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//
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// Revision 1.44 2004/04/01 09:33:26 igorm
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// Typo fixed.
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//
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// Revision 1.43 2004/03/31 14:34:13 igorm
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// data_cnt_lim length changed to reduce number of warnings.
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//
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// Revision 1.42 2004/03/30 23:10:39 igorm
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// CRC checking of incoming CRC added to all tasks.
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//
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// Revision 1.41 2004/03/28 20:27:40 igorm
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// New release of the debug interface (3rd. release).
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//
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// Revision 1.40 2004/03/22 16:36:06 igorm
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// Temp version before changing dbg interface.
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//
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// Revision 1.39 2004/03/15 16:17:07 igorm
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// 'hz changed to 1'hz because Icarus complains.
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//
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// Revision 1.38 2004/01/30 10:24:02 mohor
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// Defines WISHBONE_SUPPORTED and CPU_SUPPORTED added. By default both are
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// turned on.
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//
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// Revision 1.37 2004/01/25 14:10:25 mohor
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// Display for VATS added.
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//
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// Revision 1.36 2004/01/22 13:58:51 mohor
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// Port signals are all set to zero after reset.
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//
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// Revision 1.35 2004/01/22 11:07:28 mohor
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// test stall_test added.
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//
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// Revision 1.34 2004/01/20 14:24:08 mohor
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// Define name changed.
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//
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// Revision 1.33 2004/01/20 14:05:26 mohor
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// Data latching changed when testing WB.
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//
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// Revision 1.32 2004/01/20 10:23:21 mohor
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// More debug data added.
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//
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// Revision 1.31 2004/01/20 09:07:44 mohor
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// CRC generation iand verification in bench changed.
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//
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// Revision 1.30 2004/01/20 08:03:35 mohor
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// IDCODE test improved.
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//
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// Revision 1.29 2004/01/19 13:13:18 mohor
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// Define tap_defines.v added to test bench.
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//
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// Revision 1.28 2004/01/19 12:38:10 mohor
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// Waiting for "ready" improved.
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//
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// Revision 1.27 2004/01/17 18:01:31 mohor
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// New version.
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//
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// Revision 1.26 2004/01/17 17:01:25 mohor
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// Almost finished.
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//
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// Revision 1.25 2004/01/16 14:51:24 mohor
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// cpu registers added.
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//
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// Revision 1.24 2004/01/15 10:47:13 mohor
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// Working.
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//
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// Revision 1.23 2004/01/14 22:59:01 mohor
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// Temp version.
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//
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// Revision 1.22 2004/01/13 11:28:30 mohor
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// tmp version.
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//
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// Revision 1.21 2004/01/10 07:50:41 mohor
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// temp version.
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//
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// Revision 1.20 2004/01/09 12:49:23 mohor
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// tmp version.
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//
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// Revision 1.19 2004/01/08 17:53:12 mohor
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// tmp version.
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//
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// Revision 1.18 2004/01/07 11:59:48 mohor
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// temp4 version.
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//
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// Revision 1.17 2004/01/06 17:14:59 mohor
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// temp3 version.
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//
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// Revision 1.16 2004/01/05 12:16:50 mohor
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// tmp2 version.
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//
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// Revision 1.15 2003/12/23 14:26:01 mohor
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// New version of the debug interface. Not finished, yet.
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//
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// Revision 1.14 2003/10/23 16:16:30 mohor
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// CRC logic changed.
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//
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// Revision 1.13 2003/08/28 13:54:33 simons
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// Three more chains added for cpu debug access.
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//
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// Revision 1.12 2002/05/07 14:44:52 mohor
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// mon_cntl_o signals that controls monitor mux added.
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//
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// Revision 1.11 2002/03/12 14:32:26 mohor
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// Few outputs for boundary scan chain added.
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//
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// Revision 1.10 2002/03/08 15:27:08 mohor
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// Structure changed. Hooks for jtag chain added.
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//
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// Revision 1.9 2001/10/19 11:39:20 mohor
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// dbg_timescale.v changed to timescale.v This is done for the simulation of
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// few different cores in a single project.
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//
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// Revision 1.8 2001/10/17 10:39:17 mohor
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// bs_chain_o added.
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//
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// Revision 1.7 2001/10/16 10:10:18 mohor
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// Signal names changed to lowercase.
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//
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// Revision 1.6 2001/10/15 09:52:50 mohor
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// Wishbone interface added, few fixes for better performance,
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// hooks for boundary scan testing added.
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//
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// Revision 1.5 2001/09/24 14:06:12 mohor
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// Changes connected to the OpenRISC access (SPR read, SPR write).
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//
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// Revision 1.4 2001/09/20 10:10:29 mohor
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// Working version. Few bugs fixed, comments added.
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//
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// Revision 1.3 2001/09/19 11:54:03 mohor
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// Minor changes for simulation.
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//
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// Revision 1.2 2001/09/18 14:12:43 mohor
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// Trace fixed. Some registers changed, trace simplified.
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//
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// Revision 1.1.1.1 2001/09/13 13:49:19 mohor
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// Initial official release.
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//
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// Revision 1.3 2001/06/01 22:23:40 mohor
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// This is a backup. It is not a fully working version. Not for use, yet.
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//
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// Revision 1.2 2001/05/18 13:10:05 mohor
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// Headers changed. All additional information is now avaliable in the README.txt file.
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//
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// Revision 1.1.1.1 2001/05/18 06:35:15 mohor
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// Initial release
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//
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//
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`include "timescale.v"
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`include "tap_defines.v"
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`include "dbg_defines.v"
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`include "dbg_wb_defines.v"
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`include "dbg_cpu_defines.v"
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`define DBG_TEXT(TEXT) $display("%0s", TEXT);
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// `DBG_TEXT("Bla bla bla")
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// $sformat(dbg_text, "\n\nbla 0x%0x 0x%0x\n\n", 32'h12345678, 16'h543);
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// `DBG_TEXT(dbg_text)
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// For common cpu routines
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`ifdef DBG_CPU0_SUPPORTED
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`define DBG_CPU_SUPPORTED
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`else
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`ifdef DBG_CPU1_SUPPORTED
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`define DBG_CPU_SUPPORTED
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`endif
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`endif
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// Test bench
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module dbg_tb;
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parameter TCLK = 50; // Clock half period (Clok period = 100 ns => 10 MHz)
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reg [999:0] dbg_text;
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reg tms_pad_i;
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reg tck_pad_i;
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reg trst_pad_i;
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reg tdi_pad_i;
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wire tdo_pad_o;
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wire tdo_padoe_o;
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wire shift_dr_o;
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wire pause_dr_o;
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wire update_dr_o;
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wire capture_dr_o;
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wire extest_select_o;
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wire sample_preload_select_o;
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wire mbist_select_o;
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wire debug_select_o;
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reg rst_i;
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`ifdef DBG_WISHBONE_SUPPORTED
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// WISHBONE common signals
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reg wb_clk_i;
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// WISHBONE master interface
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wire [31:0] wb_adr_o;
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wire [31:0] wb_dat_o;
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wire [31:0] wb_dat_i;
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wire wb_cyc_o;
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wire wb_stb_o;
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wire [3:0] wb_sel_o;
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wire wb_we_o;
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wire wb_ack_i;
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wire wb_cab_o;
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wire wb_err_i;
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wire [2:0] wb_cti_o;
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wire [1:0] wb_bte_o;
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`endif
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`ifdef DBG_CPU0_SUPPORTED
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// CPU signals
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wire cpu0_clk_i;
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wire [31:0] cpu0_addr_o;
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wire [31:0] cpu0_data_i;
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wire [31:0] cpu0_data_o;
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wire cpu0_bp_i;
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wire cpu0_stall_o;
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wire cpu0_stb_o;
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wire cpu0_we_o;
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wire cpu0_ack_i;
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wire cpu0_rst_o;
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`endif
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`ifdef DBG_CPU1_SUPPORTED
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// CPU signals
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wire cpu1_clk_i;
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wire [31:0] cpu1_addr_o;
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wire [31:0] cpu1_data_i;
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wire [31:0] cpu1_data_o;
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wire cpu1_bp_i;
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wire cpu1_stall_o;
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wire cpu1_stb_o;
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wire cpu1_we_o;
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wire cpu1_ack_i;
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wire cpu1_rst_o;
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`endif
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// Text used for easier debugging
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reg [199:0] test_text;
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reg [`DBG_WB_CMD_LEN -1:0] last_wb_cmd;
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reg [`DBG_CPU_CMD_LEN -1:0] last_cpu_cmd;
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reg [199:0] last_wb_cmd_text;
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reg [199:0] last_cpu_cmd_text;
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reg [31:0] wb_data [0:4095]; // Data that is written to (read from) wishbone is stored here.
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wire tdo_o;
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wire debug_tdi_i;
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wire bs_chain_tdi_i;
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wire mbist_tdi_i;
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reg test_enabled;
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reg [31:0] result;
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reg [31:0] in_data_le, in_data_be;
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reg [31:0] id;
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wire crc_match_in;
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reg [31:0] crc_in;
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reg [31:0] crc_out;
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reg [`DBG_TOP_STATUS_LEN -1:0] status;
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reg [`DBG_WB_STATUS_LEN -1:0] status_wb;
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reg [`DBG_CPU_STATUS_LEN -1:0] status_cpu;
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reg [`DBG_WB_ACC_TYPE_LEN -1:0] read_acc_type;
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reg [`DBG_WB_ADR_LEN -1:0] read_addr;
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reg [`DBG_WB_LEN_LEN -1:0] read_length;
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reg [`DBG_CPU_CTRL_LEN -1:0] read_ctrl_reg;
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integer length_global;
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wire tdo;
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assign tdo = tdo_padoe_o? tdo_pad_o : 1'hz;
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| 328 |
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| 329 |
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// Connecting TAP module
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| 331 |
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tap_top i_tap_top (
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|
|
.tms_pad_i (tms_pad_i),
|
| 333 |
|
|
.tck_pad_i (tck_pad_i),
|
| 334 |
|
|
.trst_pad_i (!trst_pad_i),
|
| 335 |
|
|
.tdi_pad_i (tdi_pad_i),
|
| 336 |
|
|
.tdo_pad_o (tdo_pad_o),
|
| 337 |
|
|
.tdo_padoe_o (tdo_padoe_o),
|
| 338 |
|
|
|
| 339 |
|
|
// TAP states
|
| 340 |
|
|
.shift_dr_o (shift_dr_o),
|
| 341 |
|
|
.pause_dr_o (pause_dr_o),
|
| 342 |
|
|
.update_dr_o (update_dr_o),
|
| 343 |
|
|
.capture_dr_o (capture_dr_o),
|
| 344 |
|
|
|
| 345 |
|
|
// Select signals for boundary scan or mbist
|
| 346 |
|
|
.extest_select_o (extest_select_o),
|
| 347 |
|
|
.sample_preload_select_o(sample_preload_select_o),
|
| 348 |
|
|
.mbist_select_o (mbist_select_o),
|
| 349 |
|
|
.debug_select_o (debug_select_o),
|
| 350 |
|
|
|
| 351 |
|
|
// TDO signal that is connected to TDI of sub-modules.
|
| 352 |
|
|
.tdo_o (tdo_o),
|
| 353 |
|
|
|
| 354 |
|
|
// TDI signals from sub-modules
|
| 355 |
|
|
.debug_tdi_i (debug_tdi_i), // from debug module
|
| 356 |
|
|
.bs_chain_tdi_i (bs_chain_tdi_i), // from Boundary Scan Chain
|
| 357 |
|
|
.mbist_tdi_i (mbist_tdi_i) // from Mbist Chain
|
| 358 |
|
|
|
| 359 |
|
|
);
|
| 360 |
|
|
|
| 361 |
|
|
|
| 362 |
|
|
// Connecting debug top module
|
| 363 |
|
|
dbg_top i_dbg_top (
|
| 364 |
|
|
.tck_i (tck_pad_i),
|
| 365 |
|
|
.tdi_i (tdo_o),
|
| 366 |
|
|
.tdo_o (debug_tdi_i),
|
| 367 |
|
|
.rst_i (rst_i),
|
| 368 |
|
|
|
| 369 |
|
|
// TAP states
|
| 370 |
|
|
.shift_dr_i (shift_dr_o),
|
| 371 |
|
|
.pause_dr_i (pause_dr_o),
|
| 372 |
|
|
.update_dr_i (update_dr_o),
|
| 373 |
|
|
|
| 374 |
|
|
// Instructions
|
| 375 |
|
|
.debug_select_i (debug_select_o)
|
| 376 |
|
|
|
| 377 |
|
|
`ifdef DBG_WISHBONE_SUPPORTED
|
| 378 |
|
|
// WISHBONE common signals
|
| 379 |
|
|
,
|
| 380 |
|
|
.wb_clk_i (wb_clk_i),
|
| 381 |
|
|
|
| 382 |
|
|
// WISHBONE master interface
|
| 383 |
|
|
.wb_adr_o (wb_adr_o),
|
| 384 |
|
|
.wb_dat_o (wb_dat_o),
|
| 385 |
|
|
.wb_dat_i (wb_dat_i),
|
| 386 |
|
|
.wb_cyc_o (wb_cyc_o),
|
| 387 |
|
|
.wb_stb_o (wb_stb_o),
|
| 388 |
|
|
.wb_sel_o (wb_sel_o),
|
| 389 |
|
|
.wb_we_o (wb_we_o),
|
| 390 |
|
|
.wb_ack_i (wb_ack_i),
|
| 391 |
|
|
.wb_cab_o (wb_cab_o),
|
| 392 |
|
|
.wb_err_i (wb_err_i),
|
| 393 |
|
|
.wb_cti_o (wb_cti_o),
|
| 394 |
|
|
.wb_bte_o (wb_bte_o)
|
| 395 |
|
|
`endif
|
| 396 |
|
|
|
| 397 |
|
|
`ifdef DBG_CPU0_SUPPORTED
|
| 398 |
|
|
// CPU signals
|
| 399 |
|
|
,
|
| 400 |
|
|
.cpu0_clk_i (cpu0_clk_i),
|
| 401 |
|
|
.cpu0_addr_o (cpu0_addr_o),
|
| 402 |
|
|
.cpu0_data_i (cpu0_data_i),
|
| 403 |
|
|
.cpu0_data_o (cpu0_data_o),
|
| 404 |
|
|
.cpu0_bp_i (cpu0_bp_i),
|
| 405 |
|
|
.cpu0_stall_o (cpu0_stall_o),
|
| 406 |
|
|
.cpu0_stb_o (cpu0_stb_o),
|
| 407 |
|
|
.cpu0_we_o (cpu0_we_o),
|
| 408 |
|
|
.cpu0_ack_i (cpu0_ack_i),
|
| 409 |
|
|
.cpu0_rst_o (cpu0_rst_o)
|
| 410 |
|
|
`endif
|
| 411 |
|
|
|
| 412 |
|
|
`ifdef DBG_CPU1_SUPPORTED
|
| 413 |
|
|
// CPU signals
|
| 414 |
|
|
,
|
| 415 |
|
|
.cpu1_clk_i (cpu1_clk_i),
|
| 416 |
|
|
.cpu1_addr_o (cpu1_addr_o),
|
| 417 |
|
|
.cpu1_data_i (cpu1_data_i),
|
| 418 |
|
|
.cpu1_data_o (cpu1_data_o),
|
| 419 |
|
|
.cpu1_bp_i (cpu1_bp_i),
|
| 420 |
|
|
.cpu1_stall_o (cpu1_stall_o),
|
| 421 |
|
|
.cpu1_stb_o (cpu1_stb_o),
|
| 422 |
|
|
.cpu1_we_o (cpu1_we_o),
|
| 423 |
|
|
.cpu1_ack_i (cpu1_ack_i),
|
| 424 |
|
|
.cpu1_rst_o (cpu1_rst_o)
|
| 425 |
|
|
`endif
|
| 426 |
|
|
|
| 427 |
|
|
|
| 428 |
|
|
|
| 429 |
|
|
);
|
| 430 |
|
|
|
| 431 |
|
|
|
| 432 |
|
|
`ifdef DBG_WISHBONE_SUPPORTED
|
| 433 |
|
|
wb_slave_behavioral wb_slave
|
| 434 |
|
|
(
|
| 435 |
|
|
.CLK_I (wb_clk_i),
|
| 436 |
|
|
.RST_I (rst_i),
|
| 437 |
|
|
.ACK_O (wb_ack_i),
|
| 438 |
|
|
.ADR_I (wb_adr_o),
|
| 439 |
|
|
.CYC_I (wb_cyc_o),
|
| 440 |
|
|
.DAT_O (wb_dat_i),
|
| 441 |
|
|
.DAT_I (wb_dat_o),
|
| 442 |
|
|
.ERR_O (wb_err_i),
|
| 443 |
|
|
.RTY_O (), // NOT USED for now!
|
| 444 |
|
|
.SEL_I (wb_sel_o),
|
| 445 |
|
|
.STB_I (wb_stb_o),
|
| 446 |
|
|
.WE_I (wb_we_o),
|
| 447 |
|
|
.CAB_I (1'b0)
|
| 448 |
|
|
);
|
| 449 |
|
|
`endif
|
| 450 |
|
|
|
| 451 |
|
|
|
| 452 |
|
|
`ifdef DBG_CPU0_SUPPORTED
|
| 453 |
|
|
cpu_behavioral i_cpu0_behavioral
|
| 454 |
|
|
(
|
| 455 |
|
|
// CPU signals
|
| 456 |
|
|
.cpu_rst_i (rst_i),
|
| 457 |
|
|
.cpu_clk_o (cpu0_clk_i),
|
| 458 |
|
|
.cpu_addr_i (cpu0_addr_o),
|
| 459 |
|
|
.cpu_data_o (cpu0_data_i),
|
| 460 |
|
|
.cpu_data_i (cpu0_data_o),
|
| 461 |
|
|
.cpu_bp_o (cpu0_bp_i),
|
| 462 |
|
|
.cpu_stall_i (cpu0_stall_o),
|
| 463 |
|
|
.cpu_stb_i (cpu0_stb_o),
|
| 464 |
|
|
.cpu_we_i (cpu0_we_o),
|
| 465 |
|
|
.cpu_ack_o (cpu0_ack_i),
|
| 466 |
|
|
.cpu_rst_o (cpu0_rst_o)
|
| 467 |
|
|
);
|
| 468 |
|
|
`endif
|
| 469 |
|
|
|
| 470 |
|
|
|
| 471 |
|
|
|
| 472 |
|
|
`ifdef DBG_CPU1_SUPPORTED
|
| 473 |
|
|
cpu_behavioral i_cpu1_behavioral
|
| 474 |
|
|
(
|
| 475 |
|
|
// CPU signals
|
| 476 |
|
|
.cpu_rst_i (rst_i),
|
| 477 |
|
|
.cpu_clk_o (cpu1_clk_i),
|
| 478 |
|
|
.cpu_addr_i (cpu1_addr_o),
|
| 479 |
|
|
.cpu_data_o (cpu1_data_i),
|
| 480 |
|
|
.cpu_data_i (cpu1_data_o),
|
| 481 |
|
|
.cpu_bp_o (cpu1_bp_i),
|
| 482 |
|
|
.cpu_stall_i (cpu1_stall_o),
|
| 483 |
|
|
.cpu_stb_i (cpu1_stb_o),
|
| 484 |
|
|
.cpu_we_i (cpu1_we_o),
|
| 485 |
|
|
.cpu_ack_o (cpu1_ack_i),
|
| 486 |
|
|
.cpu_rst_o (cpu1_rst_o)
|
| 487 |
|
|
);
|
| 488 |
|
|
`endif
|
| 489 |
|
|
|
| 490 |
|
|
|
| 491 |
|
|
|
| 492 |
|
|
// Initial values
|
| 493 |
|
|
initial
|
| 494 |
|
|
begin
|
| 495 |
|
|
trst_pad_i = 1'b1;
|
| 496 |
|
|
tms_pad_i = 1'hz;
|
| 497 |
|
|
tck_pad_i = 1'hz;
|
| 498 |
|
|
tdi_pad_i = 1'hz;
|
| 499 |
|
|
|
| 500 |
|
|
#100;
|
| 501 |
|
|
trst_pad_i = 1'b0;
|
| 502 |
|
|
#100;
|
| 503 |
|
|
trst_pad_i = 1'b1;
|
| 504 |
|
|
end
|
| 505 |
|
|
|
| 506 |
|
|
initial
|
| 507 |
|
|
begin
|
| 508 |
|
|
test_enabled = 1'b0;
|
| 509 |
|
|
rst_i = 1'b0;
|
| 510 |
|
|
#1000;
|
| 511 |
|
|
rst_i = 1'b1;
|
| 512 |
|
|
#1000;
|
| 513 |
|
|
rst_i = 1'b0;
|
| 514 |
|
|
|
| 515 |
|
|
// Initial values for wishbone slave model
|
| 516 |
|
|
`ifdef DBG_WISHBONE_SUPPORTED
|
| 517 |
|
|
// wb_slave.cycle_response(`ACK_RESPONSE, 9'h55, 8'h2); // (`ACK_RESPONSE, wbs_waits, wbs_retries);
|
| 518 |
|
|
wb_slave.cycle_response(`ACK_RESPONSE, 9'h35, 8'h2); // (`ACK_RESPONSE, wbs_waits, wbs_retries);
|
| 519 |
|
|
`endif
|
| 520 |
|
|
#1 test_enabled<=#1 1'b1;
|
| 521 |
|
|
end
|
| 522 |
|
|
|
| 523 |
|
|
`ifdef DBG_WISHBONE_SUPPORTED
|
| 524 |
|
|
initial
|
| 525 |
|
|
begin
|
| 526 |
|
|
wb_clk_i = 1'b0;
|
| 527 |
|
|
forever #5 wb_clk_i = ~wb_clk_i;
|
| 528 |
|
|
end
|
| 529 |
|
|
`endif
|
| 530 |
|
|
|
| 531 |
|
|
always @ (posedge test_enabled)
|
| 532 |
|
|
begin
|
| 533 |
|
|
$display("//////////////////////////////////////////////////////////////////");
|
| 534 |
|
|
$display("// //");
|
| 535 |
|
|
$display("// (%0t) dbg_tb starting //", $time);
|
| 536 |
|
|
$display("// //");
|
| 537 |
|
|
$display("//////////////////////////////////////////////////////////////////");
|
| 538 |
|
|
|
| 539 |
|
|
$display("TEST: DBG_TEST");
|
| 540 |
|
|
|
| 541 |
|
|
|
| 542 |
|
|
initialize_memory(32'h12340000, 32'h00100000); // Initialize 0x100000 bytes starting from address 0x12340000
|
| 543 |
|
|
|
| 544 |
|
|
reset_tap;
|
| 545 |
|
|
|
| 546 |
|
|
#500;
|
| 547 |
|
|
goto_run_test_idle;
|
| 548 |
|
|
|
| 549 |
|
|
// `ifdef DBG_CPU0_SUPPORTED
|
| 550 |
|
|
// // Test stall signal
|
| 551 |
|
|
// stall_test_cpu0;
|
| 552 |
|
|
// `endif
|
| 553 |
|
|
|
| 554 |
|
|
// Testing read and write to internal registers
|
| 555 |
|
|
#10000;
|
| 556 |
|
|
|
| 557 |
|
|
id_test;
|
| 558 |
|
|
|
| 559 |
|
|
set_instruction(`DEBUG);
|
| 560 |
|
|
#10000;
|
| 561 |
|
|
|
| 562 |
|
|
|
| 563 |
|
|
|
| 564 |
|
|
|
| 565 |
|
|
|
| 566 |
|
|
|
| 567 |
|
|
|
| 568 |
|
|
|
| 569 |
|
|
|
| 570 |
|
|
#100000;
|
| 571 |
|
|
`ifdef DBG_WISHBONE_SUPPORTED
|
| 572 |
|
|
module_select(`DBG_TOP_WISHBONE_DEBUG_MODULE, 1'b0); // {module_id, gen_crc_err}
|
| 573 |
|
|
|
| 574 |
|
|
#10000;
|
| 575 |
|
|
debug_wishbone(`DBG_WB_READ32, 1'b0, 32'h12345678, 16'h3, 1'b0, "read32 1"); // {command, ready, addr, length, gen_crc_err, text}
|
| 576 |
|
|
// debug_wishbone(`DBG_WB_WRITE8, 1'b0, 32'h23456788, 16'h7, 1'b0, "write32 1"); // {command, ready, addr, length, gen_crc_err, text}
|
| 577 |
|
|
debug_wishbone(`DBG_WB_WRITE32, 1'b0, 32'h23456788, 16'h7, 1'b0, "write32 1"); // {command, ready, addr, length, gen_crc_err, text}
|
| 578 |
|
|
|
| 579 |
|
|
#10000;
|
| 580 |
|
|
test_text = "debug_wishbone_rd_comm";
|
| 581 |
|
|
debug_wishbone_rd_comm(read_acc_type, read_addr, read_length);
|
| 582 |
|
|
$display("debug_wishbone_rd_comm returns: acc_type = 0x%0x, addr = 0x%0x, length = 0x%0x", read_acc_type, read_addr, read_length);
|
| 583 |
|
|
debug_wishbone_go(1'b0, 1'b0);
|
| 584 |
|
|
debug_wishbone_rd_comm(read_acc_type, read_addr, read_length);
|
| 585 |
|
|
$display("debug_wishbone_rd_comm returns: acc_type = 0x%0x, addr = 0x%0x, length = 0x%0x", read_acc_type, read_addr, read_length);
|
| 586 |
|
|
|
| 587 |
|
|
debug_wishbone_go(1'b0, 1'b0);
|
| 588 |
|
|
|
| 589 |
|
|
#100000;
|
| 590 |
|
|
// debug_wishbone(`DBG_WB_READ32, 1'b0, 32'h12345224, 16'h7, 1'b0, "read32 1"); // {command, ready, addr, length, gen_crc_err, text}
|
| 591 |
|
|
debug_wishbone(`DBG_WB_READ8, 1'b0, 32'h12345223, 16'h8, 1'b0, "read8 1"); // {command, ready, addr, length, gen_crc_err, text}
|
| 592 |
|
|
#100000;
|
| 593 |
|
|
debug_wishbone_go(1'b0, 1'b0);
|
| 594 |
|
|
|
| 595 |
|
|
|
| 596 |
|
|
/*
|
| 597 |
|
|
// debug_wishbone(`DBG_WB_READ8, 1'b0, 32'h12345678, 16'h4, 1'b0, "abc 1"); // {command, ready, addr, length, gen_crc_err, text}
|
| 598 |
|
|
// debug_wishbone(`DBG_WB_READ8, 1'b0, 32'h12345679, 16'h4, 1'b0, "abc 2"); // {command, ready, addr, length, gen_crc_err, text}
|
| 599 |
|
|
// debug_wishbone(`DBG_WB_READ8, 1'b0, 32'h1234567a, 16'h4, 1'b0, "abc 3"); // {command, ready, addr, length, gen_crc_err, text}
|
| 600 |
|
|
//
|
| 601 |
|
|
// debug_wishbone(`DBG_WB_READ16, 1'b0, 32'h12345678, 16'h4, 1'b0, "abc 4"); // {command, ready, addr, length, gen_crc_err, text}
|
| 602 |
|
|
// debug_wishbone(`DBG_WB_READ16, 1'b0, 32'h1234567a, 16'h4, 1'b0, "abc 5"); // {command, ready, addr, length, gen_crc_err, text}
|
| 603 |
|
|
//
|
| 604 |
|
|
debug_wishbone(`DBG_WB_READ32, 1'b0, 32'h12345678, 16'h4, 1'b0, "read32 1"); // {command, ready, addr, length, gen_crc_err, text}
|
| 605 |
|
|
//
|
| 606 |
|
|
// debug_wishbone(`DBG_WB_READ16, 1'b0, 32'h12345679, 16'h4, 1'b0, "abc 6"); // {command, ready, addr, length, gen_crc_err, text}
|
| 607 |
|
|
|
| 608 |
|
|
#10000;
|
| 609 |
|
|
|
| 610 |
|
|
debug_wishbone(`DBG_WB_READ32, 1'b1, 32'h12345678, 16'h4, 1'b0, "read32 2"); // {command, ready, addr, length, gen_crc_err, text}
|
| 611 |
|
|
|
| 612 |
|
|
#10000;
|
| 613 |
|
|
wb_slave.cycle_response(`ACK_RESPONSE, 9'h55, 8'h2); // (`ACK_RESPONSE, wbs_waits, wbs_retries);
|
| 614 |
|
|
debug_wishbone(`DBG_WB_READ32, 1'b1, 32'h12346668, 16'h4, 1'b0, "read32 3"); // {command, ready, addr, length, gen_crc_err, text}
|
| 615 |
|
|
|
| 616 |
|
|
#10000;
|
| 617 |
|
|
wb_slave.cycle_response(`ERR_RESPONSE, 9'h03, 8'h2); // (`ERR_RESPONSE, wbs_waits, wbs_retries);
|
| 618 |
|
|
debug_wishbone(`DBG_WB_READ32, 1'b1, 32'h12346668, 16'h4, 1'b0, "read32 4"); // {command, ready, addr, length, gen_crc_err, text}
|
| 619 |
|
|
|
| 620 |
|
|
#10000;
|
| 621 |
|
|
debug_wishbone(`WB_STATUS, 1'b0, 32'h0, 16'h0, 1'b0, "status 1"); // {command, ready, addr, length, gen_crc_err, text}
|
| 622 |
|
|
|
| 623 |
|
|
#10000;
|
| 624 |
|
|
debug_wishbone(`WB_STATUS, 1'b0, 32'h0, 16'h0, 1'b0, "status 2"); // {command, ready, addr, length, gen_crc_err, text}
|
| 625 |
|
|
|
| 626 |
|
|
#10000;
|
| 627 |
|
|
wb_slave.cycle_response(`ACK_RESPONSE, 9'h012, 8'h2); // (`ACK_RESPONSE, wbs_waits, wbs_retries);
|
| 628 |
|
|
debug_wishbone(`DBG_WB_READ32, 1'b1, 32'h12347778, 16'hc, 1'b0, "read32 5"); // {command, ready, addr, length, gen_crc_err, text}
|
| 629 |
|
|
|
| 630 |
|
|
#10000;
|
| 631 |
|
|
debug_wishbone(`DBG_WB_WRITE32, 1'b0, 32'h12346668, 16'h8, 1'b0, "wr32 len8"); // {command, ready, addr, length, gen_crc_err, text}
|
| 632 |
|
|
|
| 633 |
|
|
#10000;
|
| 634 |
|
|
debug_wishbone(`DBG_WB_WRITE16, 1'b0, 32'h12344446, 16'h8, 1'b0, "wr16 len8"); // {command, ready, addr, length, gen_crc_err, text}
|
| 635 |
|
|
|
| 636 |
|
|
#10000;
|
| 637 |
|
|
debug_wishbone(`DBG_WB_WRITE8, 1'b0, 32'h1234010e, 16'h8, 1'b0, "wr8 len8"); // {command, ready, addr, length, gen_crc_err, text}
|
| 638 |
|
|
|
| 639 |
|
|
#10000;
|
| 640 |
|
|
debug_wishbone(`WB_GO, 1'b0, 32'h0, 16'h0, 1'b0, "go 1"); // {command, ready, addr, length, gen_crc_err, text}
|
| 641 |
|
|
|
| 642 |
|
|
#10000;
|
| 643 |
|
|
debug_wishbone(`DBG_WB_READ32, 1'b1, 32'h12340100, 16'hc, 1'b0, "read32 6"); // {command, ready, addr, length, gen_crc_err, text}
|
| 644 |
|
|
// debug_wishbone(`DBG_WB_READ32, 1'b1, 32'h12340100, 16'hfffc, 1'b0, "read32 6"); // {command, ready, addr, length, gen_crc_err, text}
|
| 645 |
|
|
|
| 646 |
|
|
#10000;
|
| 647 |
|
|
// debug_wishbone(`DBG_WB_READ16, 1'b1, 32'h12340102, 16'he, 1'b0, "read16 7"); // {command, ready, addr, length, gen_crc_err, text}
|
| 648 |
|
|
// debug_wishbone(`DBG_WB_READ16, 1'b1, 32'h12340102, 16'hfffe, 1'b0, "read16 7"); // {command, ready, addr, length, gen_crc_err, text}
|
| 649 |
|
|
|
| 650 |
|
|
#10000;
|
| 651 |
|
|
// debug_wishbone(`DBG_WB_READ8, 1'b1, 32'h12348804, 16'h6, 1'b0, "read8 8"); // {command, ready, addr, length, gen_crc_err, text}
|
| 652 |
|
|
// debug_wishbone(`DBG_WB_READ8, 1'b1, 32'h12348804, 16'hfffc, 1'b0, "read8 8"); // {command, ready, addr, length, gen_crc_err, text}
|
| 653 |
|
|
|
| 654 |
|
|
#10000;
|
| 655 |
|
|
debug_wishbone(`WB_GO, 1'b0, 32'h0, 16'h0, 1'b0, "go 2"); // {command, ready, addr, length, gen_crc_err, text}
|
| 656 |
|
|
*/
|
| 657 |
|
|
`endif // DBG_WISHBONE_SUPPORTED
|
| 658 |
|
|
|
| 659 |
|
|
`ifdef DBG_CPU0_SUPPORTED
|
| 660 |
|
|
#10000;
|
| 661 |
|
|
module_select(`DBG_TOP_CPU0_DEBUG_MODULE, 1'b0); // {module_id, gen_crc_err}
|
| 662 |
|
|
|
| 663 |
|
|
|
| 664 |
|
|
|
| 665 |
|
|
|
| 666 |
|
|
// Select cpu0
|
| 667 |
|
|
|
| 668 |
|
|
#10000;
|
| 669 |
|
|
debug_cpu(`DBG_CPU_WRITE, 1'b0, 32'h23456788, 16'h3, 1'b0, "cpu write 1"); // {command, ready, addr, length, gen_crc_err, text}
|
| 670 |
|
|
|
| 671 |
|
|
#10000;
|
| 672 |
|
|
debug_cpu(`DBG_CPU_READ, 1'b0, 32'h23456788, 16'h3, 1'b0, "cpu read 1"); // {command, ready, addr, length, gen_crc_err, text}
|
| 673 |
|
|
// Read register
|
| 674 |
|
|
#10000;
|
| 675 |
|
|
|
| 676 |
|
|
debug_cpu(`DBG_CPU_WRITE, 1'b0, 32'h32323232, 16'h3, 1'b0, "cpu write 1"); // {command, ready, addr, length, gen_crc_err, text}
|
| 677 |
|
|
|
| 678 |
|
|
#10000;
|
| 679 |
|
|
debug_cpu(`DBG_CPU_READ, 1'b0, 32'h77665544, 16'h3, 1'b0, "cpu read 1"); // {command, ready, addr, length, gen_crc_err, text}
|
| 680 |
|
|
// Read register
|
| 681 |
|
|
#10000;
|
| 682 |
|
|
|
| 683 |
|
|
// Reset cpu on
|
| 684 |
|
|
debug_cpu_wr_ctrl(`DBG_CPU_CTRL_LEN'b10, "rst cpu on"); // {data, text}
|
| 685 |
|
|
#10000;
|
| 686 |
|
|
|
| 687 |
|
|
// Reset cpu off
|
| 688 |
|
|
debug_cpu_wr_ctrl(`DBG_CPU_CTRL_LEN'b00, "rst cpu off"); // {data, text}
|
| 689 |
|
|
#10000;
|
| 690 |
|
|
|
| 691 |
|
|
// Stall cpu
|
| 692 |
|
|
debug_cpu_wr_ctrl(`DBG_CPU_CTRL_LEN'b01, "stall on"); // {data, text}
|
| 693 |
|
|
#10000;
|
| 694 |
|
|
|
| 695 |
|
|
debug_cpu_wr_ctrl(`DBG_CPU_CTRL_LEN'b00, "stall off"); // {data, text}
|
| 696 |
|
|
#10000;
|
| 697 |
|
|
|
| 698 |
|
|
// Stall cpu0
|
| 699 |
|
|
debug_cpu_rd_ctrl(read_ctrl_reg, "read ctrl");
|
| 700 |
|
|
$display("debug_cpu_rd_ctrl returns: read_ctrl_reg = 0x%0x", read_ctrl_reg);
|
| 701 |
|
|
#10000;
|
| 702 |
|
|
|
| 703 |
|
|
debug_cpu(`DBG_CPU_READ, 1'b0, 32'h23456788, 16'h3, 1'b0, "cpu read 2"); // {command, ready, addr, length, gen_crc_err, text}
|
| 704 |
|
|
// write to cpu 32-bit
|
| 705 |
|
|
#10000;
|
| 706 |
|
|
|
| 707 |
|
|
debug_cpu(`DBG_CPU_WRITE, 1'b0, 32'h32323232, 16'hf, 1'b0, "cpu write 2"); // {command, ready, addr, length, gen_crc_err, text}
|
| 708 |
|
|
|
| 709 |
|
|
#10000;
|
| 710 |
|
|
|
| 711 |
|
|
// read from cpu 32-bit
|
| 712 |
|
|
#10000;
|
| 713 |
|
|
|
| 714 |
|
|
#10000;
|
| 715 |
|
|
|
| 716 |
|
|
`endif // DBG_CPU0_SUPPORTED
|
| 717 |
|
|
|
| 718 |
|
|
|
| 719 |
|
|
`ifdef DBG_CPU1_SUPPORTED
|
| 720 |
|
|
#10000;
|
| 721 |
|
|
module_select(`DBG_TOP_CPU1_DEBUG_MODULE, 1'b0); // {module_id, gen_crc_err}
|
| 722 |
|
|
|
| 723 |
|
|
|
| 724 |
|
|
|
| 725 |
|
|
|
| 726 |
|
|
// Select cpu1
|
| 727 |
|
|
|
| 728 |
|
|
#10000;
|
| 729 |
|
|
debug_cpu(`DBG_CPU_WRITE, 1'b0, 32'h23456788, 16'h3, 1'b0, "cpu write 1"); // {command, ready, addr, length, gen_crc_err, text}
|
| 730 |
|
|
|
| 731 |
|
|
#10000;
|
| 732 |
|
|
debug_cpu(`DBG_CPU_READ, 1'b0, 32'h23456788, 16'h3, 1'b0, "cpu read 1"); // {command, ready, addr, length, gen_crc_err, text}
|
| 733 |
|
|
// Read register
|
| 734 |
|
|
#10000;
|
| 735 |
|
|
|
| 736 |
|
|
debug_cpu(`DBG_CPU_WRITE, 1'b0, 32'h32323232, 16'h3, 1'b0, "cpu write 1"); // {command, ready, addr, length, gen_crc_err, text}
|
| 737 |
|
|
|
| 738 |
|
|
#10000;
|
| 739 |
|
|
debug_cpu(`DBG_CPU_READ, 1'b0, 32'h77665544, 16'h3, 1'b0, "cpu read 1"); // {command, ready, addr, length, gen_crc_err, text}
|
| 740 |
|
|
// Read register
|
| 741 |
|
|
#10000;
|
| 742 |
|
|
|
| 743 |
|
|
// Reset cpu on
|
| 744 |
|
|
debug_cpu_wr_ctrl(`DBG_CPU_CTRL_LEN'b10, "rst cpu on"); // {data, text}
|
| 745 |
|
|
#10000;
|
| 746 |
|
|
|
| 747 |
|
|
// Reset cpu off
|
| 748 |
|
|
debug_cpu_wr_ctrl(`DBG_CPU_CTRL_LEN'b00, "rst cpu off"); // {data, text}
|
| 749 |
|
|
#10000;
|
| 750 |
|
|
|
| 751 |
|
|
// Stall cpu
|
| 752 |
|
|
debug_cpu_wr_ctrl(`DBG_CPU_CTRL_LEN'b01, "stall on"); // {data, text}
|
| 753 |
|
|
#10000;
|
| 754 |
|
|
|
| 755 |
|
|
debug_cpu_wr_ctrl(`DBG_CPU_CTRL_LEN'b00, "stall off"); // {data, text}
|
| 756 |
|
|
#10000;
|
| 757 |
|
|
|
| 758 |
|
|
// Stall cpu1
|
| 759 |
|
|
debug_cpu_rd_ctrl(read_ctrl_reg, "read ctrl");
|
| 760 |
|
|
$display("debug_cpu_rd_ctrl returns: read_ctrl_reg = 0x%0x", read_ctrl_reg);
|
| 761 |
|
|
#10000;
|
| 762 |
|
|
|
| 763 |
|
|
debug_cpu(`DBG_CPU_READ, 1'b0, 32'h23456788, 16'h3, 1'b0, "cpu read 2"); // {command, ready, addr, length, gen_crc_err, text}
|
| 764 |
|
|
// write to cpu 32-bit
|
| 765 |
|
|
#10000;
|
| 766 |
|
|
|
| 767 |
|
|
debug_cpu(`DBG_CPU_WRITE, 1'b0, 32'h32323232, 16'hf, 1'b0, "cpu write 2"); // {command, ready, addr, length, gen_crc_err, text}
|
| 768 |
|
|
|
| 769 |
|
|
#10000;
|
| 770 |
|
|
|
| 771 |
|
|
// read from cpu 32-bit
|
| 772 |
|
|
#10000;
|
| 773 |
|
|
|
| 774 |
|
|
#10000;
|
| 775 |
|
|
|
| 776 |
|
|
`endif // DBG_CPU1_SUPPORTED
|
| 777 |
|
|
|
| 778 |
|
|
|
| 779 |
|
|
|
| 780 |
|
|
|
| 781 |
|
|
|
| 782 |
|
|
|
| 783 |
|
|
|
| 784 |
|
|
|
| 785 |
|
|
|
| 786 |
|
|
#5000 gen_clk(1); // One extra TCLK for debugging purposes
|
| 787 |
|
|
$display("STATUS: passed");
|
| 788 |
|
|
$display("\n\nSimulation end.");
|
| 789 |
|
|
#1000 $stop;
|
| 790 |
|
|
|
| 791 |
|
|
end
|
| 792 |
|
|
|
| 793 |
|
|
|
| 794 |
|
|
`ifdef DBG_CPU0_SUPPORTED
|
| 795 |
|
|
task stall_test_cpu0;
|
| 796 |
|
|
integer i;
|
| 797 |
|
|
|
| 798 |
|
|
begin
|
| 799 |
|
|
test_text = "stall_test_cpu0";
|
| 800 |
|
|
$display("\n\n(%0t) stall_test_cpu0 started", $time);
|
| 801 |
|
|
|
| 802 |
|
|
// Set bp_i active for 1 clock cycle and check is stall is set or not
|
| 803 |
|
|
check_stall_cpu0(0); // Should not be set at the beginning
|
| 804 |
|
|
@ (posedge cpu0_clk_i);
|
| 805 |
|
|
#1 dbg_tb.i_cpu0_behavioral.cpu_bp_o = 1'b1;
|
| 806 |
|
|
#1 check_stall_cpu0(1); // set?
|
| 807 |
|
|
@ (posedge cpu0_clk_i);
|
| 808 |
|
|
#1 dbg_tb.i_cpu0_behavioral.cpu_bp_o = 1'b0;
|
| 809 |
|
|
#1 check_stall_cpu0(1); // set?
|
| 810 |
|
|
|
| 811 |
|
|
gen_clk(1);
|
| 812 |
|
|
#1 check_stall_cpu0(1); // set?
|
| 813 |
|
|
|
| 814 |
|
|
// Unstall with register
|
| 815 |
|
|
set_instruction(`DEBUG);
|
| 816 |
|
|
module_select(`DBG_TOP_CPU0_DEBUG_MODULE, 1'b0); // {module_id, gen_crc_err}
|
| 817 |
|
|
#1 check_stall_cpu0(1); // set?
|
| 818 |
|
|
// igor !!! debug_cpu(`CPU_WRITE_REG, `CPU_OP_ADR, 32'h0, 1'b0, result, "clr unstall"); // {command, addr, data, gen_crc_err, result, text}
|
| 819 |
|
|
#1 check_stall_cpu0(1); // set?
|
| 820 |
|
|
debug_cpu(`DBG_CPU_WR_COMM, 32'h0, 32'h0, 1'b0, result, "go cpu"); // {command, addr, data, gen_crc_err, result, text}
|
| 821 |
|
|
#1 check_stall_cpu0(0); // reset?
|
| 822 |
|
|
|
| 823 |
|
|
// Set stall with register
|
| 824 |
|
|
// igor !!! debug_cpu(`CPU_WRITE_REG, `CPU_OP_ADR, 32'h0, 1'b0, result, "clr stall"); // {command, addr, data, gen_crc_err, result, text}
|
| 825 |
|
|
#1 check_stall_cpu0(0); // reset?
|
| 826 |
|
|
debug_cpu(`DBG_CPU_WR_COMM, 32'h0, 32'h1, 1'b0, result, "go cpu"); // {command, addr, data, gen_crc_err, result, text}
|
| 827 |
|
|
#1 check_stall_cpu0(1); // set?
|
| 828 |
|
|
|
| 829 |
|
|
// Unstall with register
|
| 830 |
|
|
// igor !!! debug_cpu(`CPU_WRITE_REG, `CPU_OP_ADR, 32'h0, 1'b0, result, "clr unstall"); // {command, addr, data, gen_crc_err, result, text}
|
| 831 |
|
|
#1 check_stall_cpu0(1); // set?
|
| 832 |
|
|
debug_cpu(`DBG_CPU_WR_COMM, 32'h0, 32'h0, 1'b0, result, "go cpu"); // {command, addr, data, gen_crc_err, result, text}
|
| 833 |
|
|
#1 check_stall_cpu0(0); // reset?
|
| 834 |
|
|
|
| 835 |
|
|
$display("\n\n(%0t) stall_test_cpu0 passed\n\n", $time);
|
| 836 |
|
|
end
|
| 837 |
|
|
endtask // stall_test_cpu0
|
| 838 |
|
|
|
| 839 |
|
|
|
| 840 |
|
|
task check_stall_cpu0;
|
| 841 |
|
|
input should_be_set;
|
| 842 |
|
|
begin
|
| 843 |
|
|
if (should_be_set && (!cpu0_stall_o))
|
| 844 |
|
|
begin
|
| 845 |
|
|
$display ("\t\t(%0t) ERROR: cpu0_stall_o is not set but should be.", $time);
|
| 846 |
|
|
$stop;
|
| 847 |
|
|
end
|
| 848 |
|
|
if ((!should_be_set) && cpu0_stall_o)
|
| 849 |
|
|
begin
|
| 850 |
|
|
$display ("\t\t(%0t) ERROR: cpu0_stall_o set but shouldn't be.", $time);
|
| 851 |
|
|
$stop;
|
| 852 |
|
|
end
|
| 853 |
|
|
end
|
| 854 |
|
|
endtask // check_stall_cpu0
|
| 855 |
|
|
`endif // DBG_CPU0_SUPPORTED
|
| 856 |
|
|
|
| 857 |
|
|
|
| 858 |
|
|
task initialize_memory;
|
| 859 |
|
|
input [31:0] start_addr;
|
| 860 |
|
|
input [31:0] length;
|
| 861 |
|
|
integer i;
|
| 862 |
|
|
reg [31:0] addr;
|
| 863 |
|
|
begin
|
| 864 |
|
|
for (i=0; i<length; i=i+4) // This data will be return from wb slave
|
| 865 |
|
|
begin
|
| 866 |
|
|
addr = start_addr + i;
|
| 867 |
|
|
`ifdef DBG_WISHBONE_SUPPORTED
|
| 868 |
|
|
wb_slave.wr_mem(addr, {addr[7:0], addr[7:0]+2'd1, addr[7:0]+2'd2, addr[7:0]+2'd3}, 4'hf); // adr, data, sel
|
| 869 |
|
|
`endif
|
| 870 |
|
|
end
|
| 871 |
|
|
for (i=0; i<4096; i=i+1) // This data will be written to wb slave
|
| 872 |
|
|
begin
|
| 873 |
|
|
wb_data[i] <= {i[7:0], i[7:0]+2'd1, i[7:0]+2'd2, i[7:0]+2'd3};
|
| 874 |
|
|
end
|
| 875 |
|
|
end
|
| 876 |
|
|
endtask
|
| 877 |
|
|
|
| 878 |
|
|
|
| 879 |
|
|
task id_test;
|
| 880 |
|
|
begin
|
| 881 |
|
|
test_text = "id_test";
|
| 882 |
|
|
$display("\n\n(%0t) TEST: id_test", $time);
|
| 883 |
|
|
|
| 884 |
|
|
set_instruction(`IDCODE);
|
| 885 |
|
|
read_id_code(id);
|
| 886 |
|
|
|
| 887 |
|
|
`ifdef DBG_MORE_INFO
|
| 888 |
|
|
$display("\tRead ID = 0x%0x", id);
|
| 889 |
|
|
$display("\tExpected ID = 0x%0x", `IDCODE_VALUE);
|
| 890 |
|
|
`endif
|
| 891 |
|
|
|
| 892 |
|
|
if (id==`IDCODE_VALUE)
|
| 893 |
|
|
$display("(%0t) STATUS: passed\n", $time);
|
| 894 |
|
|
else
|
| 895 |
|
|
$display("(%0t) STATUS: failed (Read ID = 0x%0x, Expected ID = 0x%0x\n", $time, id, `IDCODE_VALUE);
|
| 896 |
|
|
end
|
| 897 |
|
|
endtask // id_test
|
| 898 |
|
|
|
| 899 |
|
|
|
| 900 |
|
|
// Generation of the TCLK signal
|
| 901 |
|
|
task gen_clk;
|
| 902 |
|
|
input [7:0] num;
|
| 903 |
|
|
integer i;
|
| 904 |
|
|
begin
|
| 905 |
|
|
for(i=0; i<num; i=i+1)
|
| 906 |
|
|
begin
|
| 907 |
|
|
#TCLK tck_pad_i<=1;
|
| 908 |
|
|
#TCLK tck_pad_i<=0;
|
| 909 |
|
|
end
|
| 910 |
|
|
end
|
| 911 |
|
|
endtask
|
| 912 |
|
|
|
| 913 |
|
|
|
| 914 |
|
|
// TAP reset
|
| 915 |
|
|
task reset_tap;
|
| 916 |
|
|
begin
|
| 917 |
|
|
$display("(%0t) Task reset_tap", $time);
|
| 918 |
|
|
tms_pad_i<=#1 1'b1;
|
| 919 |
|
|
gen_clk(5);
|
| 920 |
|
|
end
|
| 921 |
|
|
endtask
|
| 922 |
|
|
|
| 923 |
|
|
|
| 924 |
|
|
// Goes to RunTestIdle state
|
| 925 |
|
|
task goto_run_test_idle;
|
| 926 |
|
|
begin
|
| 927 |
|
|
$display("(%0t) Task goto_run_test_idle", $time);
|
| 928 |
|
|
tms_pad_i<=#1 1'b0;
|
| 929 |
|
|
gen_clk(1);
|
| 930 |
|
|
end
|
| 931 |
|
|
endtask
|
| 932 |
|
|
|
| 933 |
|
|
|
| 934 |
|
|
|
| 935 |
|
|
// sets the instruction to the IR register and goes to the RunTestIdle state
|
| 936 |
|
|
task set_instruction;
|
| 937 |
|
|
input [3:0] instr;
|
| 938 |
|
|
integer i;
|
| 939 |
|
|
|
| 940 |
|
|
begin
|
| 941 |
|
|
case (instr)
|
| 942 |
|
|
`ifdef DBG_MORE_INFO
|
| 943 |
|
|
`EXTEST : $display("(%0t) Task set_instruction (EXTEST)", $time);
|
| 944 |
|
|
`SAMPLE_PRELOAD : $display("(%0t) Task set_instruction (SAMPLE_PRELOAD)", $time);
|
| 945 |
|
|
`IDCODE : $display("(%0t) Task set_instruction (IDCODE)", $time);
|
| 946 |
|
|
`DEBUG : $display("(%0t) Task set_instruction (DEBUG)", $time);
|
| 947 |
|
|
`MBIST : $display("(%0t) Task set_instruction (MBIST)", $time);
|
| 948 |
|
|
`BYPASS : $display("(%0t) Task set_instruction (BYPASS)", $time);
|
| 949 |
|
|
`else
|
| 950 |
|
|
`EXTEST : ;
|
| 951 |
|
|
`SAMPLE_PRELOAD : ;
|
| 952 |
|
|
`IDCODE : ;
|
| 953 |
|
|
`DEBUG : ;
|
| 954 |
|
|
`MBIST : ;
|
| 955 |
|
|
`BYPASS : ;
|
| 956 |
|
|
`endif
|
| 957 |
|
|
default
|
| 958 |
|
|
begin
|
| 959 |
|
|
$display("(*E) (%0t) Task set_instruction: Unsupported instruction !!!", $time);
|
| 960 |
|
|
$stop;
|
| 961 |
|
|
end
|
| 962 |
|
|
endcase
|
| 963 |
|
|
|
| 964 |
|
|
tms_pad_i<=#1 1;
|
| 965 |
|
|
gen_clk(2);
|
| 966 |
|
|
tms_pad_i<=#1 0;
|
| 967 |
|
|
gen_clk(2); // we are in shiftIR
|
| 968 |
|
|
|
| 969 |
|
|
for(i=0; i<`IR_LENGTH-1; i=i+1)
|
| 970 |
|
|
begin
|
| 971 |
|
|
tdi_pad_i<=#1 instr[i];
|
| 972 |
|
|
gen_clk(1);
|
| 973 |
|
|
end
|
| 974 |
|
|
|
| 975 |
|
|
tdi_pad_i<=#1 instr[i]; // last shift
|
| 976 |
|
|
tms_pad_i<=#1 1; // going out of shiftIR
|
| 977 |
|
|
gen_clk(1);
|
| 978 |
|
|
tdi_pad_i<=#1 1'hz; // tri-state
|
| 979 |
|
|
gen_clk(1);
|
| 980 |
|
|
tms_pad_i<=#1 0;
|
| 981 |
|
|
gen_clk(1); // we are in RunTestIdle
|
| 982 |
|
|
end
|
| 983 |
|
|
endtask
|
| 984 |
|
|
|
| 985 |
|
|
|
| 986 |
|
|
// Reads the ID code
|
| 987 |
|
|
task read_id_code;
|
| 988 |
|
|
output [31:0] code;
|
| 989 |
|
|
reg [31:0] code;
|
| 990 |
|
|
begin
|
| 991 |
|
|
`ifdef DBG_MORE_INFO
|
| 992 |
|
|
$display("(%0t) Task read_id_code", $time);
|
| 993 |
|
|
`endif
|
| 994 |
|
|
tms_pad_i<=#1 1;
|
| 995 |
|
|
gen_clk(1);
|
| 996 |
|
|
tms_pad_i<=#1 0;
|
| 997 |
|
|
gen_clk(2); // we are in shiftDR
|
| 998 |
|
|
|
| 999 |
|
|
tdi_pad_i<=#1 0;
|
| 1000 |
|
|
gen_clk(31);
|
| 1001 |
|
|
|
| 1002 |
|
|
tms_pad_i<=#1 1; // going out of shiftIR
|
| 1003 |
|
|
gen_clk(1);
|
| 1004 |
|
|
|
| 1005 |
|
|
code = in_data_le;
|
| 1006 |
|
|
|
| 1007 |
|
|
tdi_pad_i<=#1 1'hz; // tri-state
|
| 1008 |
|
|
gen_clk(1);
|
| 1009 |
|
|
tms_pad_i<=#1 0;
|
| 1010 |
|
|
gen_clk(1); // we are in RunTestIdle
|
| 1011 |
|
|
end
|
| 1012 |
|
|
endtask
|
| 1013 |
|
|
|
| 1014 |
|
|
|
| 1015 |
|
|
// sets the selected module and goes to the RunTestIdle state
|
| 1016 |
|
|
task module_select;
|
| 1017 |
|
|
input [`DBG_TOP_MODULE_ID_LENGTH -1:0] data;
|
| 1018 |
|
|
input gen_crc_err;
|
| 1019 |
|
|
integer i;
|
| 1020 |
|
|
|
| 1021 |
|
|
begin
|
| 1022 |
|
|
case (data)
|
| 1023 |
|
|
`DBG_TOP_CPU0_DEBUG_MODULE : $display("(%0t) Task module_select (DBG_TOP_CPU0_DEBUG_MODULE, gen_crc_err=%0d)", $time, gen_crc_err);
|
| 1024 |
|
|
`DBG_TOP_CPU1_DEBUG_MODULE : $display("(%0t) Task module_select (DBG_TOP_CPU1_DEBUG_MODULE, gen_crc_err=%0d)", $time, gen_crc_err);
|
| 1025 |
|
|
`DBG_TOP_WISHBONE_DEBUG_MODULE : $display("(%0t) Task module_select (DBG_TOP_WISHBONE_DEBUG_MODULE, gen_crc_err=%0d)", $time, gen_crc_err);
|
| 1026 |
|
|
default : $display("(%0t) Task module_select (ERROR!!! Unknown module selected)", $time);
|
| 1027 |
|
|
endcase
|
| 1028 |
|
|
|
| 1029 |
|
|
tms_pad_i<=#1 1'b1;
|
| 1030 |
|
|
gen_clk(1);
|
| 1031 |
|
|
tms_pad_i<=#1 1'b0;
|
| 1032 |
|
|
gen_clk(2); // we are in shiftDR
|
| 1033 |
|
|
|
| 1034 |
|
|
status = {`DBG_TOP_STATUS_LEN{1'b0}}; // Initialize status to all 0's
|
| 1035 |
|
|
crc_out = {`DBG_TOP_CRC_LEN{1'b1}}; // Initialize outgoing CRC to all ff
|
| 1036 |
|
|
tdi_pad_i<=#1 1'b1; // module_select bit
|
| 1037 |
|
|
calculate_crc(1'b1);
|
| 1038 |
|
|
gen_clk(1);
|
| 1039 |
|
|
|
| 1040 |
|
|
for(i=`DBG_TOP_MODULE_ID_LENGTH -1; i>=0; i=i-1) // Shifting module ID
|
| 1041 |
|
|
begin
|
| 1042 |
|
|
tdi_pad_i<=#1 data[i];
|
| 1043 |
|
|
calculate_crc(data[i]);
|
| 1044 |
|
|
gen_clk(1);
|
| 1045 |
|
|
end
|
| 1046 |
|
|
|
| 1047 |
|
|
for(i=`DBG_TOP_CRC_LEN -1; i>=0; i=i-1)
|
| 1048 |
|
|
begin
|
| 1049 |
|
|
if (gen_crc_err & (i==0)) // Generate crc error at last crc bit
|
| 1050 |
|
|
tdi_pad_i<=#1 ~crc_out[i]; // error crc
|
| 1051 |
|
|
else
|
| 1052 |
|
|
tdi_pad_i<=#1 crc_out[i]; // ok crc
|
| 1053 |
|
|
|
| 1054 |
|
|
gen_clk(1);
|
| 1055 |
|
|
end
|
| 1056 |
|
|
|
| 1057 |
|
|
tdi_pad_i<=#1 1'hz; // tri-state
|
| 1058 |
|
|
|
| 1059 |
|
|
crc_in = {`DBG_TOP_CRC_LEN{1'b1}}; // Initialize incoming CRC to all ff
|
| 1060 |
|
|
|
| 1061 |
|
|
for(i=`DBG_TOP_STATUS_LEN -1; i>=0; i=i-1)
|
| 1062 |
|
|
begin
|
| 1063 |
|
|
gen_clk(1); // Generating 1 clock to read out a status bit.
|
| 1064 |
|
|
status[i] = tdo;
|
| 1065 |
|
|
end
|
| 1066 |
|
|
|
| 1067 |
|
|
for(i=0; i<`DBG_TOP_CRC_LEN -1; i=i+1)
|
| 1068 |
|
|
gen_clk(1);
|
| 1069 |
|
|
|
| 1070 |
|
|
tms_pad_i<=#1 1'b1;
|
| 1071 |
|
|
gen_clk(1); // to exit1_dr
|
| 1072 |
|
|
|
| 1073 |
|
|
if (~crc_match_in)
|
| 1074 |
|
|
begin
|
| 1075 |
|
|
$display("(%0t) Incoming CRC failed !!!", $time);
|
| 1076 |
|
|
$stop;
|
| 1077 |
|
|
end
|
| 1078 |
|
|
|
| 1079 |
|
|
tms_pad_i<=#1 1'b1;
|
| 1080 |
|
|
gen_clk(1); // to update_dr
|
| 1081 |
|
|
tms_pad_i<=#1 1'b0;
|
| 1082 |
|
|
gen_clk(1); // to run_test_idle
|
| 1083 |
|
|
|
| 1084 |
|
|
if (|status)
|
| 1085 |
|
|
begin
|
| 1086 |
|
|
$write("(*E) (%0t) Module select error: ", $time);
|
| 1087 |
|
|
casex (status)
|
| 1088 |
|
|
4'b1xxx : $display("CRC error !!!\n\n", $time);
|
| 1089 |
|
|
4'bx1xx : $display("Non-existing module selected !!!\n\n", $time);
|
| 1090 |
|
|
4'bxx1x : $display("Status[1] should be 1'b0 !!!\n\n", $time);
|
| 1091 |
|
|
4'bxxx1 : $display("Status[0] should be 1'b0 !!!\n\n", $time);
|
| 1092 |
|
|
endcase
|
| 1093 |
|
|
$stop;
|
| 1094 |
|
|
end
|
| 1095 |
|
|
end
|
| 1096 |
|
|
endtask // module_select
|
| 1097 |
|
|
|
| 1098 |
|
|
|
| 1099 |
|
|
|
| 1100 |
|
|
|
| 1101 |
|
|
`ifdef DBG_WISHBONE_SUPPORTED
|
| 1102 |
|
|
task debug_wishbone;
|
| 1103 |
|
|
input [`DBG_WB_CMD_LEN -1:0] command;
|
| 1104 |
|
|
input ready;
|
| 1105 |
|
|
input [`DBG_WB_ADR_LEN -1:0] addr;
|
| 1106 |
|
|
input [`DBG_WB_LEN_LEN -1:0] length;
|
| 1107 |
|
|
input gen_crc_err;
|
| 1108 |
|
|
input [99:0] text;
|
| 1109 |
|
|
integer i;
|
| 1110 |
|
|
|
| 1111 |
|
|
begin
|
| 1112 |
|
|
$write("(%0t) Task debug_wishbone: ", $time);
|
| 1113 |
|
|
|
| 1114 |
|
|
test_text = text;
|
| 1115 |
|
|
|
| 1116 |
|
|
case (command)
|
| 1117 |
|
|
`DBG_WB_READ8 :
|
| 1118 |
|
|
begin
|
| 1119 |
|
|
$display("wb_read8 (adr=0x%0x, length=0x%0x, gen_crc_err=%0d (%0s))", addr, length, gen_crc_err, text);
|
| 1120 |
|
|
debug_wishbone_wr_comm(`DBG_WB_READ8, addr, length, gen_crc_err);
|
| 1121 |
|
|
last_wb_cmd = `DBG_WB_READ8; last_wb_cmd_text = "DBG_WB_READ8";
|
| 1122 |
|
|
#10000;
|
| 1123 |
|
|
length_global = length + 1;
|
| 1124 |
|
|
debug_wishbone_go(ready, gen_crc_err);
|
| 1125 |
|
|
end
|
| 1126 |
|
|
`DBG_WB_READ16 :
|
| 1127 |
|
|
begin
|
| 1128 |
|
|
$display("wb_read16 (adr=0x%0x, length=0x%0x, gen_crc_err=%0d (%0s))", addr, length, gen_crc_err, text);
|
| 1129 |
|
|
debug_wishbone_wr_comm(`DBG_WB_READ16, addr, length, gen_crc_err);
|
| 1130 |
|
|
last_wb_cmd = `DBG_WB_READ16; last_wb_cmd_text = "DBG_WB_READ16";
|
| 1131 |
|
|
#10000;
|
| 1132 |
|
|
length_global = length + 1;
|
| 1133 |
|
|
debug_wishbone_go(ready, gen_crc_err);
|
| 1134 |
|
|
end
|
| 1135 |
|
|
`DBG_WB_READ32 :
|
| 1136 |
|
|
begin
|
| 1137 |
|
|
$display("wb_read32 (adr=0x%0x, length=0x%0x, gen_crc_err=%0d (%0s))", addr, length, gen_crc_err, text);
|
| 1138 |
|
|
debug_wishbone_wr_comm(`DBG_WB_READ32, addr, length, gen_crc_err);
|
| 1139 |
|
|
last_wb_cmd = `DBG_WB_READ32; last_wb_cmd_text = "DBG_WB_READ32";
|
| 1140 |
|
|
#10000;
|
| 1141 |
|
|
length_global = length + 1;
|
| 1142 |
|
|
debug_wishbone_go(ready, gen_crc_err);
|
| 1143 |
|
|
end
|
| 1144 |
|
|
`DBG_WB_WRITE8 :
|
| 1145 |
|
|
begin
|
| 1146 |
|
|
$display("wb_write8 (adr=0x%0x, length=0x%0x, gen_crc_err=%0d (%0s))", addr, length, gen_crc_err, text);
|
| 1147 |
|
|
debug_wishbone_wr_comm(`DBG_WB_WRITE8, addr, length, gen_crc_err);
|
| 1148 |
|
|
last_wb_cmd = `DBG_WB_WRITE8; last_wb_cmd_text = "DBG_WB_WRITE8";
|
| 1149 |
|
|
#10000;
|
| 1150 |
|
|
length_global = length + 1;
|
| 1151 |
|
|
debug_wishbone_go(ready, gen_crc_err);
|
| 1152 |
|
|
end
|
| 1153 |
|
|
`DBG_WB_WRITE16 :
|
| 1154 |
|
|
begin
|
| 1155 |
|
|
$display("wb_write16 (adr=0x%0x, length=0x%0x, gen_crc_err=%0d (%0s))", addr, length, gen_crc_err, text);
|
| 1156 |
|
|
debug_wishbone_wr_comm(`DBG_WB_WRITE16, addr, length, gen_crc_err);
|
| 1157 |
|
|
last_wb_cmd = `DBG_WB_WRITE16; last_wb_cmd_text = "DBG_WB_WRITE16";
|
| 1158 |
|
|
#10000;
|
| 1159 |
|
|
length_global = length + 1;
|
| 1160 |
|
|
debug_wishbone_go(ready, gen_crc_err);
|
| 1161 |
|
|
end
|
| 1162 |
|
|
`DBG_WB_WRITE32 :
|
| 1163 |
|
|
begin
|
| 1164 |
|
|
$display("wb_write32 (adr=0x%0x, length=0x%0x, gen_crc_err=%0d (%0s))", addr, length, gen_crc_err, text);
|
| 1165 |
|
|
debug_wishbone_wr_comm(`DBG_WB_WRITE32, addr, length, gen_crc_err);
|
| 1166 |
|
|
last_wb_cmd = `DBG_WB_WRITE32; last_wb_cmd_text = "DBG_WB_WRITE32";
|
| 1167 |
|
|
#10000;
|
| 1168 |
|
|
length_global = length + 1;
|
| 1169 |
|
|
debug_wishbone_go(ready, gen_crc_err);
|
| 1170 |
|
|
end
|
| 1171 |
|
|
default:
|
| 1172 |
|
|
begin
|
| 1173 |
|
|
$display("(*E) debug_wishbone : Unsupported instruction !!!");
|
| 1174 |
|
|
$stop;
|
| 1175 |
|
|
end
|
| 1176 |
|
|
endcase
|
| 1177 |
|
|
end
|
| 1178 |
|
|
endtask // debug_wishbone
|
| 1179 |
|
|
|
| 1180 |
|
|
|
| 1181 |
|
|
|
| 1182 |
|
|
|
| 1183 |
|
|
|
| 1184 |
|
|
|
| 1185 |
|
|
task debug_wishbone_wr_comm;
|
| 1186 |
|
|
input [`DBG_WB_ACC_TYPE_LEN -1:0] acc_type;
|
| 1187 |
|
|
input [`DBG_WB_ADR_LEN -1:0] addr;
|
| 1188 |
|
|
input [`DBG_WB_LEN_LEN -1:0] length;
|
| 1189 |
|
|
input gen_crc_err;
|
| 1190 |
|
|
integer i;
|
| 1191 |
|
|
reg [`DBG_WB_CMD_LEN -1:0] command;
|
| 1192 |
|
|
|
| 1193 |
|
|
begin
|
| 1194 |
|
|
$display("(%0t) Task debug_wishbone_wr_comm: ", $time);
|
| 1195 |
|
|
|
| 1196 |
|
|
command = `DBG_WB_WR_COMM;
|
| 1197 |
|
|
tms_pad_i<=#1 1'b1;
|
| 1198 |
|
|
gen_clk(1);
|
| 1199 |
|
|
tms_pad_i<=#1 1'b0;
|
| 1200 |
|
|
gen_clk(2); // we are in shiftDR
|
| 1201 |
|
|
|
| 1202 |
|
|
crc_out = {`DBG_WB_CRC_LEN{1'b1}}; // Initialize outgoing CRC to all ff
|
| 1203 |
|
|
|
| 1204 |
|
|
tdi_pad_i<=#1 1'b0; // module_select bit = 0
|
| 1205 |
|
|
calculate_crc(1'b0);
|
| 1206 |
|
|
gen_clk(1);
|
| 1207 |
|
|
|
| 1208 |
|
|
for(i=`DBG_WB_CMD_LEN -1; i>=0; i=i-1)
|
| 1209 |
|
|
begin
|
| 1210 |
|
|
tdi_pad_i<=#1 command[i]; // command
|
| 1211 |
|
|
calculate_crc(command[i]);
|
| 1212 |
|
|
gen_clk(1);
|
| 1213 |
|
|
end
|
| 1214 |
|
|
|
| 1215 |
|
|
for(i=`DBG_WB_ACC_TYPE_LEN -1; i>=0; i=i-1)
|
| 1216 |
|
|
begin
|
| 1217 |
|
|
tdi_pad_i<=#1 acc_type[i]; // command
|
| 1218 |
|
|
calculate_crc(acc_type[i]);
|
| 1219 |
|
|
gen_clk(1);
|
| 1220 |
|
|
end
|
| 1221 |
|
|
|
| 1222 |
|
|
for(i=`DBG_WB_ADR_LEN -1; i>=0; i=i-1) // address
|
| 1223 |
|
|
begin
|
| 1224 |
|
|
tdi_pad_i<=#1 addr[i];
|
| 1225 |
|
|
calculate_crc(addr[i]);
|
| 1226 |
|
|
gen_clk(1);
|
| 1227 |
|
|
end
|
| 1228 |
|
|
|
| 1229 |
|
|
for(i=`DBG_WB_LEN_LEN -1; i>=0; i=i-1) // length
|
| 1230 |
|
|
begin
|
| 1231 |
|
|
tdi_pad_i<=#1 length[i];
|
| 1232 |
|
|
calculate_crc(length[i]);
|
| 1233 |
|
|
gen_clk(1);
|
| 1234 |
|
|
end
|
| 1235 |
|
|
|
| 1236 |
|
|
for(i=`DBG_WB_CRC_LEN -1; i>=0; i=i-1)
|
| 1237 |
|
|
begin
|
| 1238 |
|
|
if (gen_crc_err & (i==0)) // Generate crc error at last crc bit
|
| 1239 |
|
|
tdi_pad_i<=#1 ~crc_out[i]; // error crc
|
| 1240 |
|
|
else
|
| 1241 |
|
|
tdi_pad_i<=#1 crc_out[i]; // ok crc
|
| 1242 |
|
|
|
| 1243 |
|
|
gen_clk(1);
|
| 1244 |
|
|
end
|
| 1245 |
|
|
|
| 1246 |
|
|
tdi_pad_i<=#1 1'hz;
|
| 1247 |
|
|
|
| 1248 |
|
|
crc_in = {`DBG_WB_CRC_LEN{1'b1}}; // Initialize incoming CRC to all ff
|
| 1249 |
|
|
|
| 1250 |
|
|
for(i=`DBG_WB_STATUS_LEN -1; i>=0; i=i-1)
|
| 1251 |
|
|
begin
|
| 1252 |
|
|
gen_clk(1); // Generating clock to read out a status bit.
|
| 1253 |
|
|
status_wb[i] = tdo;
|
| 1254 |
|
|
end
|
| 1255 |
|
|
|
| 1256 |
|
|
if (|status_wb)
|
| 1257 |
|
|
begin
|
| 1258 |
|
|
$write("(*E) (%0t) debug_wishbone_wr_comm error: ", $time);
|
| 1259 |
|
|
casex (status_wb)
|
| 1260 |
|
|
4'b1xxx : $display("CRC error !!!\n\n", $time);
|
| 1261 |
|
|
4'bx1xx : $display("Unknown command !!!\n\n", $time);
|
| 1262 |
|
|
4'bxx1x : $display("WISHBONE error !!!\n\n", $time);
|
| 1263 |
|
|
4'bxxx1 : $display("Overrun/Underrun !!!\n\n", $time);
|
| 1264 |
|
|
endcase
|
| 1265 |
|
|
$stop;
|
| 1266 |
|
|
end
|
| 1267 |
|
|
|
| 1268 |
|
|
|
| 1269 |
|
|
for(i=0; i<`DBG_WB_CRC_LEN -1; i=i+1) // Getting in the CRC
|
| 1270 |
|
|
begin
|
| 1271 |
|
|
gen_clk(1);
|
| 1272 |
|
|
end
|
| 1273 |
|
|
|
| 1274 |
|
|
tms_pad_i<=#1 1'b1;
|
| 1275 |
|
|
gen_clk(1); // to exit1_dr
|
| 1276 |
|
|
|
| 1277 |
|
|
if (~crc_match_in)
|
| 1278 |
|
|
begin
|
| 1279 |
|
|
$display("(%0t) Incoming CRC failed !!!", $time);
|
| 1280 |
|
|
$stop;
|
| 1281 |
|
|
end
|
| 1282 |
|
|
|
| 1283 |
|
|
tms_pad_i<=#1 1'b1;
|
| 1284 |
|
|
gen_clk(1); // to update_dr
|
| 1285 |
|
|
tms_pad_i<=#1 1'b0;
|
| 1286 |
|
|
gen_clk(1); // to run_test_idle
|
| 1287 |
|
|
end
|
| 1288 |
|
|
endtask // debug_wishbone_wr_comm
|
| 1289 |
|
|
|
| 1290 |
|
|
|
| 1291 |
|
|
|
| 1292 |
|
|
|
| 1293 |
|
|
|
| 1294 |
|
|
task debug_wishbone_rd_comm;
|
| 1295 |
|
|
output [`DBG_WB_ACC_TYPE_LEN -1:0] acc_type;
|
| 1296 |
|
|
output [`DBG_WB_ADR_LEN -1:0] addr;
|
| 1297 |
|
|
output [`DBG_WB_LEN_LEN -1:0] length;
|
| 1298 |
|
|
integer i;
|
| 1299 |
|
|
reg [`DBG_WB_CMD_LEN -1:0] command;
|
| 1300 |
|
|
|
| 1301 |
|
|
begin
|
| 1302 |
|
|
$display("(%0t) Task debug_wishbone_rd_comm: ", $time);
|
| 1303 |
|
|
|
| 1304 |
|
|
command = `DBG_WB_RD_COMM;
|
| 1305 |
|
|
tms_pad_i<=#1 1'b1;
|
| 1306 |
|
|
gen_clk(1);
|
| 1307 |
|
|
tms_pad_i<=#1 1'b0;
|
| 1308 |
|
|
gen_clk(2); // we are in shiftDR
|
| 1309 |
|
|
|
| 1310 |
|
|
crc_out = {`DBG_WB_CRC_LEN{1'b1}}; // Initialize outgoing CRC to all ff
|
| 1311 |
|
|
|
| 1312 |
|
|
tdi_pad_i<=#1 1'b0; // module_select bit = 0
|
| 1313 |
|
|
calculate_crc(1'b0);
|
| 1314 |
|
|
gen_clk(1);
|
| 1315 |
|
|
|
| 1316 |
|
|
for(i=`DBG_WB_CMD_LEN -1; i>=0; i=i-1)
|
| 1317 |
|
|
begin
|
| 1318 |
|
|
tdi_pad_i<=#1 command[i]; // command
|
| 1319 |
|
|
calculate_crc(command[i]);
|
| 1320 |
|
|
gen_clk(1);
|
| 1321 |
|
|
end
|
| 1322 |
|
|
|
| 1323 |
|
|
for(i=`DBG_WB_CRC_LEN -1; i>=0; i=i-1)
|
| 1324 |
|
|
begin
|
| 1325 |
|
|
tdi_pad_i<=#1 crc_out[i];
|
| 1326 |
|
|
gen_clk(1);
|
| 1327 |
|
|
end
|
| 1328 |
|
|
|
| 1329 |
|
|
tdi_pad_i<=#1 1'hz;
|
| 1330 |
|
|
|
| 1331 |
|
|
crc_in = {`DBG_WB_CRC_LEN{1'b1}}; // Initialize incoming CRC to all ff
|
| 1332 |
|
|
|
| 1333 |
|
|
for(i=`DBG_WB_ACC_TYPE_LEN -1; i>=0; i=i-1)
|
| 1334 |
|
|
begin
|
| 1335 |
|
|
gen_clk(1);
|
| 1336 |
|
|
acc_type[i] = tdo;
|
| 1337 |
|
|
end
|
| 1338 |
|
|
|
| 1339 |
|
|
for(i=`DBG_WB_ADR_LEN -1; i>=0; i=i-1) // address
|
| 1340 |
|
|
begin
|
| 1341 |
|
|
gen_clk(1);
|
| 1342 |
|
|
addr[i] = tdo;
|
| 1343 |
|
|
end
|
| 1344 |
|
|
|
| 1345 |
|
|
for(i=`DBG_WB_LEN_LEN -1; i>=0; i=i-1) // length
|
| 1346 |
|
|
begin
|
| 1347 |
|
|
gen_clk(1);
|
| 1348 |
|
|
length[i] = tdo;
|
| 1349 |
|
|
end
|
| 1350 |
|
|
|
| 1351 |
|
|
for(i=`DBG_WB_STATUS_LEN -1; i>=0; i=i-1)
|
| 1352 |
|
|
begin
|
| 1353 |
|
|
gen_clk(1); // Generating clock to read out a status bit.
|
| 1354 |
|
|
status_wb[i] = tdo;
|
| 1355 |
|
|
end
|
| 1356 |
|
|
|
| 1357 |
|
|
if (|status_wb)
|
| 1358 |
|
|
begin
|
| 1359 |
|
|
$write("(*E) (%0t) debug_wishbone_rd_comm: ", $time);
|
| 1360 |
|
|
casex (status_wb)
|
| 1361 |
|
|
4'b1xxx : $display("CRC error !!!\n\n", $time);
|
| 1362 |
|
|
4'bx1xx : $display("Unknown command !!!\n\n", $time);
|
| 1363 |
|
|
4'bxx1x : $display("Unknown command !!!\n\n", $time);
|
| 1364 |
|
|
4'bxxx1 : $display("Unknown command !!!\n\n", $time);
|
| 1365 |
|
|
endcase
|
| 1366 |
|
|
$stop;
|
| 1367 |
|
|
end
|
| 1368 |
|
|
|
| 1369 |
|
|
|
| 1370 |
|
|
for(i=0; i<`DBG_WB_CRC_LEN -1; i=i+1) // Getting in the CRC
|
| 1371 |
|
|
begin
|
| 1372 |
|
|
gen_clk(1);
|
| 1373 |
|
|
end
|
| 1374 |
|
|
|
| 1375 |
|
|
tms_pad_i<=#1 1'b1;
|
| 1376 |
|
|
gen_clk(1); // to exit1_dr
|
| 1377 |
|
|
|
| 1378 |
|
|
if (~crc_match_in)
|
| 1379 |
|
|
begin
|
| 1380 |
|
|
$display("(%0t) Incoming CRC failed !!!", $time);
|
| 1381 |
|
|
$stop;
|
| 1382 |
|
|
end
|
| 1383 |
|
|
|
| 1384 |
|
|
tms_pad_i<=#1 1'b1;
|
| 1385 |
|
|
gen_clk(1); // to update_dr
|
| 1386 |
|
|
tms_pad_i<=#1 1'b0;
|
| 1387 |
|
|
gen_clk(1); // to run_test_idle
|
| 1388 |
|
|
end
|
| 1389 |
|
|
endtask // debug_wishbone_rd_comm
|
| 1390 |
|
|
|
| 1391 |
|
|
|
| 1392 |
|
|
|
| 1393 |
|
|
|
| 1394 |
|
|
|
| 1395 |
|
|
task debug_wishbone_go;
|
| 1396 |
|
|
input wait_for_wb_ready;
|
| 1397 |
|
|
input gen_crc_err;
|
| 1398 |
|
|
integer i;
|
| 1399 |
|
|
reg [4:0] bit_pointer;
|
| 1400 |
|
|
integer word_pointer;
|
| 1401 |
|
|
reg [31:0] tmp_data;
|
| 1402 |
|
|
reg [`DBG_WB_CMD_LEN -1:0] command;
|
| 1403 |
|
|
|
| 1404 |
|
|
|
| 1405 |
|
|
begin
|
| 1406 |
|
|
$display("(%0t) Task debug_wishbone_go (previous command was %0s): ", $time, last_wb_cmd_text);
|
| 1407 |
|
|
command = `DBG_WB_GO;
|
| 1408 |
|
|
word_pointer = 0;
|
| 1409 |
|
|
|
| 1410 |
|
|
tms_pad_i<=#1 1'b1;
|
| 1411 |
|
|
gen_clk(1);
|
| 1412 |
|
|
tms_pad_i<=#1 1'b0;
|
| 1413 |
|
|
gen_clk(2); // we are in shiftDR
|
| 1414 |
|
|
|
| 1415 |
|
|
crc_out = {`DBG_WB_CRC_LEN{1'b1}}; // Initialize outgoing CRC to all ff
|
| 1416 |
|
|
|
| 1417 |
|
|
tdi_pad_i<=#1 1'b0; // module_select bit = 0
|
| 1418 |
|
|
calculate_crc(1'b0);
|
| 1419 |
|
|
gen_clk(1);
|
| 1420 |
|
|
|
| 1421 |
|
|
for(i=`DBG_WB_CMD_LEN -1; i>=0; i=i-1)
|
| 1422 |
|
|
begin
|
| 1423 |
|
|
tdi_pad_i<=#1 command[i]; // command
|
| 1424 |
|
|
calculate_crc(command[i]);
|
| 1425 |
|
|
gen_clk(1);
|
| 1426 |
|
|
end
|
| 1427 |
|
|
|
| 1428 |
|
|
|
| 1429 |
|
|
if ((last_wb_cmd == `DBG_WB_WRITE8) | (last_wb_cmd == `DBG_WB_WRITE16) | (last_wb_cmd == `DBG_WB_WRITE32)) // When WB_WRITEx was previously activated, data needs to be shifted.
|
| 1430 |
|
|
begin
|
| 1431 |
|
|
for (i=0; i<((length_global) << 3); i=i+1)
|
| 1432 |
|
|
begin
|
| 1433 |
|
|
tmp_data = wb_data[word_pointer];
|
| 1434 |
|
|
if ((!(i%32)) && (i>0))
|
| 1435 |
|
|
begin
|
| 1436 |
|
|
word_pointer = word_pointer + 1;
|
| 1437 |
|
|
end
|
| 1438 |
|
|
bit_pointer = 31-i[4:0];
|
| 1439 |
|
|
tdi_pad_i<=#1 tmp_data[bit_pointer];
|
| 1440 |
|
|
calculate_crc(tmp_data[bit_pointer]);
|
| 1441 |
|
|
gen_clk(1);
|
| 1442 |
|
|
|
| 1443 |
|
|
end
|
| 1444 |
|
|
end
|
| 1445 |
|
|
|
| 1446 |
|
|
for(i=`DBG_WB_CRC_LEN -1; i>=1; i=i-1)
|
| 1447 |
|
|
begin
|
| 1448 |
|
|
tdi_pad_i<=#1 crc_out[i];
|
| 1449 |
|
|
gen_clk(1);
|
| 1450 |
|
|
end
|
| 1451 |
|
|
|
| 1452 |
|
|
if (gen_crc_err) // Generate crc error at last crc bit
|
| 1453 |
|
|
tdi_pad_i<=#1 ~crc_out[0]; // error crc
|
| 1454 |
|
|
else
|
| 1455 |
|
|
tdi_pad_i<=#1 crc_out[0]; // ok crc
|
| 1456 |
|
|
|
| 1457 |
|
|
if (wait_for_wb_ready)
|
| 1458 |
|
|
begin
|
| 1459 |
|
|
tms_pad_i<=#1 1'b1;
|
| 1460 |
|
|
gen_clk(1); // to exit1_dr. Last CRC is shifted on this clk
|
| 1461 |
|
|
tms_pad_i<=#1 1'b0;
|
| 1462 |
|
|
gen_clk(1); // to pause_dr
|
| 1463 |
|
|
|
| 1464 |
|
|
#2; // wait a bit for tdo to activate
|
| 1465 |
|
|
while (tdo) // waiting for wb to send "ready"
|
| 1466 |
|
|
begin
|
| 1467 |
|
|
gen_clk(1); // staying in pause_dr
|
| 1468 |
|
|
end
|
| 1469 |
|
|
|
| 1470 |
|
|
tms_pad_i<=#1 1'b1;
|
| 1471 |
|
|
gen_clk(1); // to exit2_dr
|
| 1472 |
|
|
tms_pad_i<=#1 1'b0;
|
| 1473 |
|
|
gen_clk(1); // to shift_dr
|
| 1474 |
|
|
end
|
| 1475 |
|
|
else
|
| 1476 |
|
|
begin
|
| 1477 |
|
|
gen_clk(1); // Last CRC is shifted on this clk
|
| 1478 |
|
|
end
|
| 1479 |
|
|
|
| 1480 |
|
|
|
| 1481 |
|
|
tdi_pad_i<=#1 1'hz;
|
| 1482 |
|
|
crc_in = {`DBG_WB_CRC_LEN{1'b1}}; // Initialize incoming CRC to all ff
|
| 1483 |
|
|
|
| 1484 |
|
|
if ((last_wb_cmd == `DBG_WB_READ8) | (last_wb_cmd == `DBG_WB_READ16) | (last_wb_cmd == `DBG_WB_READ32)) // When WB_READx was previously activated, data needs to be shifted.
|
| 1485 |
|
|
begin
|
| 1486 |
|
|
$display("\t\tGenerating %0d clocks to read %0d data bytes.", length_global<<3, length_global);
|
| 1487 |
|
|
word_pointer = 0; // Reset pointer
|
| 1488 |
|
|
for (i=0; i<(length_global<<3); i=i+1)
|
| 1489 |
|
|
begin
|
| 1490 |
|
|
gen_clk(1);
|
| 1491 |
|
|
if (i[4:0] == 31) // Latching data
|
| 1492 |
|
|
begin
|
| 1493 |
|
|
wb_data[word_pointer] = in_data_be;
|
| 1494 |
|
|
$display("\t\tin_data_be = 0x%x", in_data_be);
|
| 1495 |
|
|
word_pointer = word_pointer + 1;
|
| 1496 |
|
|
end
|
| 1497 |
|
|
end
|
| 1498 |
|
|
end
|
| 1499 |
|
|
|
| 1500 |
|
|
|
| 1501 |
|
|
for(i=`DBG_WB_STATUS_LEN -1; i>=0; i=i-1)
|
| 1502 |
|
|
begin
|
| 1503 |
|
|
gen_clk(1); // Generating clock to read out a status bit.
|
| 1504 |
|
|
status_wb[i] = tdo;
|
| 1505 |
|
|
end
|
| 1506 |
|
|
|
| 1507 |
|
|
if (|status_wb)
|
| 1508 |
|
|
begin
|
| 1509 |
|
|
$write("(*E) (%0t) debug_wishbone_go error: ", $time);
|
| 1510 |
|
|
casex (status_wb)
|
| 1511 |
|
|
4'b1xxx : $display("CRC error !!!\n\n", $time);
|
| 1512 |
|
|
4'bx1xx : $display("Unknown command !!!\n\n", $time);
|
| 1513 |
|
|
4'bxx1x : $display("WISHBONE error !!!\n\n", $time);
|
| 1514 |
|
|
4'bxxx1 : $display("Overrun/Underrun !!!\n\n", $time);
|
| 1515 |
|
|
endcase
|
| 1516 |
|
|
$stop;
|
| 1517 |
|
|
end
|
| 1518 |
|
|
|
| 1519 |
|
|
|
| 1520 |
|
|
for(i=0; i<`DBG_WB_CRC_LEN -1; i=i+1) // Getting in the CRC
|
| 1521 |
|
|
begin
|
| 1522 |
|
|
gen_clk(1);
|
| 1523 |
|
|
end
|
| 1524 |
|
|
|
| 1525 |
|
|
tms_pad_i<=#1 1'b1;
|
| 1526 |
|
|
gen_clk(1); // to exit1_dr
|
| 1527 |
|
|
|
| 1528 |
|
|
if (~crc_match_in)
|
| 1529 |
|
|
begin
|
| 1530 |
|
|
$display("(%0t) Incoming CRC failed !!!", $time);
|
| 1531 |
|
|
$stop;
|
| 1532 |
|
|
end
|
| 1533 |
|
|
|
| 1534 |
|
|
tms_pad_i<=#1 1'b1;
|
| 1535 |
|
|
gen_clk(1); // to update_dr
|
| 1536 |
|
|
tms_pad_i<=#1 1'b0;
|
| 1537 |
|
|
gen_clk(1); // to run_test_idle
|
| 1538 |
|
|
end
|
| 1539 |
|
|
endtask // debug_wishbone_go
|
| 1540 |
|
|
|
| 1541 |
|
|
|
| 1542 |
|
|
`endif // DBG_WISHBONE_SUPPORTED
|
| 1543 |
|
|
|
| 1544 |
|
|
|
| 1545 |
|
|
`ifdef DBG_CPU_SUPPORTED
|
| 1546 |
|
|
task debug_cpu;
|
| 1547 |
|
|
input [`DBG_CPU_CMD_LEN -1:0] command;
|
| 1548 |
|
|
input ready;
|
| 1549 |
|
|
input [`DBG_CPU_ADR_LEN -1:0] addr;
|
| 1550 |
|
|
input [`DBG_CPU_LEN_LEN -1:0] length;
|
| 1551 |
|
|
input gen_crc_err;
|
| 1552 |
|
|
input [99:0] text;
|
| 1553 |
|
|
integer i;
|
| 1554 |
|
|
|
| 1555 |
|
|
begin
|
| 1556 |
|
|
$write("(%0t) Task debug_cpu: ", $time);
|
| 1557 |
|
|
|
| 1558 |
|
|
test_text = text;
|
| 1559 |
|
|
|
| 1560 |
|
|
case (command)
|
| 1561 |
|
|
`DBG_CPU_READ :
|
| 1562 |
|
|
begin
|
| 1563 |
|
|
$display("cpu_read (adr=0x%0x, length=0x%0x, gen_crc_err=%0d (%0s))", addr, length, gen_crc_err, text);
|
| 1564 |
|
|
debug_cpu_wr_comm(`DBG_CPU_READ, addr, length, gen_crc_err);
|
| 1565 |
|
|
last_cpu_cmd = `DBG_CPU_READ; last_cpu_cmd_text = "DBG_CPU_READ";
|
| 1566 |
|
|
length_global = length + 1;
|
| 1567 |
|
|
#10000;
|
| 1568 |
|
|
debug_cpu_go(ready, gen_crc_err);
|
| 1569 |
|
|
end
|
| 1570 |
|
|
`DBG_CPU_WRITE :
|
| 1571 |
|
|
begin
|
| 1572 |
|
|
$display("cpu_write (adr=0x%0x, length=0x%0x, gen_crc_err=%0d (%0s))", addr, length, gen_crc_err, text);
|
| 1573 |
|
|
debug_cpu_wr_comm(`DBG_CPU_WRITE, addr, length, gen_crc_err);
|
| 1574 |
|
|
last_cpu_cmd = `DBG_CPU_WRITE; last_cpu_cmd_text = "DBG_CPU_WRITE";
|
| 1575 |
|
|
#10000;
|
| 1576 |
|
|
length_global = length + 1;
|
| 1577 |
|
|
debug_cpu_go(ready, gen_crc_err);
|
| 1578 |
|
|
end
|
| 1579 |
|
|
default:
|
| 1580 |
|
|
begin
|
| 1581 |
|
|
$display("(*E) debug_cpu : Unsupported instruction !!!");
|
| 1582 |
|
|
$stop;
|
| 1583 |
|
|
end
|
| 1584 |
|
|
endcase
|
| 1585 |
|
|
end
|
| 1586 |
|
|
endtask // debug_cpu
|
| 1587 |
|
|
|
| 1588 |
|
|
|
| 1589 |
|
|
|
| 1590 |
|
|
task debug_cpu_wr_comm;
|
| 1591 |
|
|
input [`DBG_CPU_ACC_TYPE_LEN -1:0] acc_type;
|
| 1592 |
|
|
input [`DBG_CPU_ADR_LEN -1:0] addr;
|
| 1593 |
|
|
input [`DBG_CPU_LEN_LEN -1:0] length;
|
| 1594 |
|
|
input gen_crc_err;
|
| 1595 |
|
|
integer i;
|
| 1596 |
|
|
reg [`DBG_CPU_CMD_LEN -1:0] command;
|
| 1597 |
|
|
|
| 1598 |
|
|
begin
|
| 1599 |
|
|
$display("(%0t) Task debug_cpu_wr_comm: ", $time);
|
| 1600 |
|
|
|
| 1601 |
|
|
command = `DBG_CPU_WR_COMM;
|
| 1602 |
|
|
tms_pad_i<=#1 1'b1;
|
| 1603 |
|
|
gen_clk(1);
|
| 1604 |
|
|
tms_pad_i<=#1 1'b0;
|
| 1605 |
|
|
gen_clk(2); // we are in shiftDR
|
| 1606 |
|
|
|
| 1607 |
|
|
crc_out = {`DBG_CPU_CRC_LEN{1'b1}}; // Initialize outgoing CRC to all ff
|
| 1608 |
|
|
|
| 1609 |
|
|
tdi_pad_i<=#1 1'b0; // module_select bit = 0
|
| 1610 |
|
|
calculate_crc(1'b0);
|
| 1611 |
|
|
gen_clk(1);
|
| 1612 |
|
|
|
| 1613 |
|
|
for(i=`DBG_CPU_CMD_LEN -1; i>=0; i=i-1)
|
| 1614 |
|
|
begin
|
| 1615 |
|
|
tdi_pad_i<=#1 command[i]; // command
|
| 1616 |
|
|
calculate_crc(command[i]);
|
| 1617 |
|
|
gen_clk(1);
|
| 1618 |
|
|
end
|
| 1619 |
|
|
|
| 1620 |
|
|
for(i=`DBG_CPU_ACC_TYPE_LEN -1; i>=0; i=i-1)
|
| 1621 |
|
|
begin
|
| 1622 |
|
|
tdi_pad_i<=#1 acc_type[i]; // command
|
| 1623 |
|
|
calculate_crc(acc_type[i]);
|
| 1624 |
|
|
gen_clk(1);
|
| 1625 |
|
|
end
|
| 1626 |
|
|
|
| 1627 |
|
|
for(i=`DBG_CPU_ADR_LEN -1; i>=0; i=i-1) // address
|
| 1628 |
|
|
begin
|
| 1629 |
|
|
tdi_pad_i<=#1 addr[i];
|
| 1630 |
|
|
calculate_crc(addr[i]);
|
| 1631 |
|
|
gen_clk(1);
|
| 1632 |
|
|
end
|
| 1633 |
|
|
|
| 1634 |
|
|
for(i=`DBG_CPU_LEN_LEN -1; i>=0; i=i-1) // length
|
| 1635 |
|
|
begin
|
| 1636 |
|
|
tdi_pad_i<=#1 length[i];
|
| 1637 |
|
|
calculate_crc(length[i]);
|
| 1638 |
|
|
gen_clk(1);
|
| 1639 |
|
|
end
|
| 1640 |
|
|
|
| 1641 |
|
|
for(i=`DBG_CPU_CRC_LEN -1; i>=0; i=i-1)
|
| 1642 |
|
|
begin
|
| 1643 |
|
|
if (gen_crc_err & (i==0)) // Generate crc error at last crc bit
|
| 1644 |
|
|
tdi_pad_i<=#1 ~crc_out[i]; // error crc
|
| 1645 |
|
|
else
|
| 1646 |
|
|
tdi_pad_i<=#1 crc_out[i]; // ok crc
|
| 1647 |
|
|
|
| 1648 |
|
|
gen_clk(1);
|
| 1649 |
|
|
end
|
| 1650 |
|
|
|
| 1651 |
|
|
tdi_pad_i<=#1 1'hz;
|
| 1652 |
|
|
|
| 1653 |
|
|
crc_in = {`DBG_CPU_CRC_LEN{1'b1}}; // Initialize incoming CRC to all ff
|
| 1654 |
|
|
|
| 1655 |
|
|
for(i=`DBG_CPU_STATUS_LEN -1; i>=0; i=i-1)
|
| 1656 |
|
|
begin
|
| 1657 |
|
|
gen_clk(1); // Generating clock to read out a status bit.
|
| 1658 |
|
|
status_cpu[i] = tdo;
|
| 1659 |
|
|
end
|
| 1660 |
|
|
|
| 1661 |
|
|
if (|status_cpu)
|
| 1662 |
|
|
begin
|
| 1663 |
|
|
$write("(*E) (%0t) debug_cpu_wr_comm error: ", $time);
|
| 1664 |
|
|
casex (status_cpu)
|
| 1665 |
|
|
4'b1xxx : $display("CRC error !!!\n\n", $time);
|
| 1666 |
|
|
4'bx1xx : $display("Unknown command !!!\n\n", $time);
|
| 1667 |
|
|
4'bxx1x : $display("??? error !!!\n\n", $time);
|
| 1668 |
|
|
4'bxxx1 : $display("Overrun/Underrun !!!\n\n", $time);
|
| 1669 |
|
|
endcase
|
| 1670 |
|
|
$stop;
|
| 1671 |
|
|
end
|
| 1672 |
|
|
|
| 1673 |
|
|
|
| 1674 |
|
|
for(i=0; i<`DBG_CPU_CRC_LEN -1; i=i+1) // Getting in the CRC
|
| 1675 |
|
|
begin
|
| 1676 |
|
|
gen_clk(1);
|
| 1677 |
|
|
end
|
| 1678 |
|
|
|
| 1679 |
|
|
tms_pad_i<=#1 1'b1;
|
| 1680 |
|
|
gen_clk(1); // to exit1_dr
|
| 1681 |
|
|
|
| 1682 |
|
|
if (~crc_match_in)
|
| 1683 |
|
|
begin
|
| 1684 |
|
|
$display("(%0t) Incoming CRC failed !!!", $time);
|
| 1685 |
|
|
$stop;
|
| 1686 |
|
|
end
|
| 1687 |
|
|
|
| 1688 |
|
|
tms_pad_i<=#1 1'b1;
|
| 1689 |
|
|
gen_clk(1); // to update_dr
|
| 1690 |
|
|
tms_pad_i<=#1 1'b0;
|
| 1691 |
|
|
gen_clk(1); // to run_test_idle
|
| 1692 |
|
|
end
|
| 1693 |
|
|
endtask // debug_cpu_wr_comm
|
| 1694 |
|
|
|
| 1695 |
|
|
|
| 1696 |
|
|
|
| 1697 |
|
|
task debug_cpu_wr_ctrl;
|
| 1698 |
|
|
input [`DBG_CPU_CTRL_LEN -1:0] data;
|
| 1699 |
|
|
input [99:0] text;
|
| 1700 |
|
|
integer i;
|
| 1701 |
|
|
reg [`DBG_CPU_CMD_LEN -1:0] command;
|
| 1702 |
|
|
|
| 1703 |
|
|
begin
|
| 1704 |
|
|
test_text = text;
|
| 1705 |
|
|
|
| 1706 |
|
|
$display("(%0t) Task debug_cpu_wr_ctrl (data=0x%0x (%0s))", $time, data, text);
|
| 1707 |
|
|
|
| 1708 |
|
|
command = `DBG_CPU_WR_CTRL;
|
| 1709 |
|
|
tms_pad_i<=#1 1'b1;
|
| 1710 |
|
|
gen_clk(1);
|
| 1711 |
|
|
tms_pad_i<=#1 1'b0;
|
| 1712 |
|
|
gen_clk(2); // we are in shiftDR
|
| 1713 |
|
|
|
| 1714 |
|
|
crc_out = {`DBG_CPU_CRC_LEN{1'b1}}; // Initialize outgoing CRC to all ff
|
| 1715 |
|
|
|
| 1716 |
|
|
tdi_pad_i<=#1 1'b0; // module_select bit = 0
|
| 1717 |
|
|
calculate_crc(1'b0);
|
| 1718 |
|
|
gen_clk(1);
|
| 1719 |
|
|
|
| 1720 |
|
|
for(i=`DBG_CPU_CMD_LEN -1; i>=0; i=i-1)
|
| 1721 |
|
|
begin
|
| 1722 |
|
|
tdi_pad_i<=#1 command[i]; // command
|
| 1723 |
|
|
calculate_crc(command[i]);
|
| 1724 |
|
|
gen_clk(1);
|
| 1725 |
|
|
end
|
| 1726 |
|
|
|
| 1727 |
|
|
for(i=`DBG_CPU_CTRL_LEN -1; i>=0; i=i-1)
|
| 1728 |
|
|
begin
|
| 1729 |
|
|
tdi_pad_i<=#1 data[i]; // data (used cotrol bits
|
| 1730 |
|
|
calculate_crc(data[i]);
|
| 1731 |
|
|
gen_clk(1);
|
| 1732 |
|
|
end
|
| 1733 |
|
|
|
| 1734 |
|
|
for(i=`DBG_CPU_DR_LEN - `DBG_CPU_CTRL_LEN -1; i>=0; i=i-1) // unused control bits
|
| 1735 |
|
|
begin
|
| 1736 |
|
|
tdi_pad_i<=#1 1'b0;
|
| 1737 |
|
|
calculate_crc(1'b0);
|
| 1738 |
|
|
gen_clk(1);
|
| 1739 |
|
|
end
|
| 1740 |
|
|
|
| 1741 |
|
|
for(i=`DBG_CPU_CRC_LEN -1; i>=0; i=i-1)
|
| 1742 |
|
|
begin
|
| 1743 |
|
|
tdi_pad_i<=#1 crc_out[i]; // ok crc
|
| 1744 |
|
|
gen_clk(1);
|
| 1745 |
|
|
end
|
| 1746 |
|
|
|
| 1747 |
|
|
tdi_pad_i<=#1 1'hz;
|
| 1748 |
|
|
|
| 1749 |
|
|
crc_in = {`DBG_CPU_CRC_LEN{1'b1}}; // Initialize incoming CRC to all ff
|
| 1750 |
|
|
|
| 1751 |
|
|
for(i=`DBG_CPU_STATUS_LEN -1; i>=0; i=i-1)
|
| 1752 |
|
|
begin
|
| 1753 |
|
|
gen_clk(1); // Generating clock to read out a status bit.
|
| 1754 |
|
|
status_cpu[i] = tdo;
|
| 1755 |
|
|
end
|
| 1756 |
|
|
|
| 1757 |
|
|
if (|status_cpu)
|
| 1758 |
|
|
begin
|
| 1759 |
|
|
$write("(*E) (%0t) debug_cpu_wr_ctrl error: ", $time);
|
| 1760 |
|
|
casex (status_cpu)
|
| 1761 |
|
|
4'b1xxx : $display("CRC error !!!\n\n", $time);
|
| 1762 |
|
|
4'bx1xx : $display("??? error !!!\n\n", $time);
|
| 1763 |
|
|
4'bxx1x : $display("??? error !!!\n\n", $time);
|
| 1764 |
|
|
4'bxxx1 : $display("??? error !!!\n\n", $time);
|
| 1765 |
|
|
endcase
|
| 1766 |
|
|
$stop;
|
| 1767 |
|
|
end
|
| 1768 |
|
|
|
| 1769 |
|
|
|
| 1770 |
|
|
for(i=0; i<`DBG_CPU_CRC_LEN -1; i=i+1) // Getting in the CRC
|
| 1771 |
|
|
begin
|
| 1772 |
|
|
gen_clk(1);
|
| 1773 |
|
|
end
|
| 1774 |
|
|
|
| 1775 |
|
|
tms_pad_i<=#1 1'b1;
|
| 1776 |
|
|
gen_clk(1); // to exit1_dr
|
| 1777 |
|
|
|
| 1778 |
|
|
if (~crc_match_in)
|
| 1779 |
|
|
begin
|
| 1780 |
|
|
$display("(%0t) Incoming CRC failed !!!", $time);
|
| 1781 |
|
|
$stop;
|
| 1782 |
|
|
end
|
| 1783 |
|
|
|
| 1784 |
|
|
tms_pad_i<=#1 1'b1;
|
| 1785 |
|
|
gen_clk(1); // to update_dr
|
| 1786 |
|
|
tms_pad_i<=#1 1'b0;
|
| 1787 |
|
|
gen_clk(1); // to run_test_idle
|
| 1788 |
|
|
end
|
| 1789 |
|
|
endtask // debug_cpu_wr_ctrl
|
| 1790 |
|
|
|
| 1791 |
|
|
|
| 1792 |
|
|
|
| 1793 |
|
|
task debug_cpu_rd_ctrl;
|
| 1794 |
|
|
output [`DBG_CPU_CTRL_LEN -1:0] data;
|
| 1795 |
|
|
input [99:0] text;
|
| 1796 |
|
|
integer i;
|
| 1797 |
|
|
reg [`DBG_CPU_CMD_LEN -1:0] command;
|
| 1798 |
|
|
|
| 1799 |
|
|
begin
|
| 1800 |
|
|
test_text = text;
|
| 1801 |
|
|
$display("(%0t) Task debug_cpu_rd_ctrl: ", $time);
|
| 1802 |
|
|
|
| 1803 |
|
|
command = `DBG_CPU_RD_CTRL;
|
| 1804 |
|
|
tms_pad_i<=#1 1'b1;
|
| 1805 |
|
|
gen_clk(1);
|
| 1806 |
|
|
tms_pad_i<=#1 1'b0;
|
| 1807 |
|
|
gen_clk(2); // we are in shiftDR
|
| 1808 |
|
|
|
| 1809 |
|
|
crc_out = {`DBG_CPU_CRC_LEN{1'b1}}; // Initialize outgoing CRC to all ff
|
| 1810 |
|
|
|
| 1811 |
|
|
tdi_pad_i<=#1 1'b0; // module_select bit = 0
|
| 1812 |
|
|
calculate_crc(1'b0);
|
| 1813 |
|
|
gen_clk(1);
|
| 1814 |
|
|
|
| 1815 |
|
|
for(i=`DBG_CPU_CMD_LEN -1; i>=0; i=i-1)
|
| 1816 |
|
|
begin
|
| 1817 |
|
|
tdi_pad_i<=#1 command[i]; // command
|
| 1818 |
|
|
calculate_crc(command[i]);
|
| 1819 |
|
|
gen_clk(1);
|
| 1820 |
|
|
end
|
| 1821 |
|
|
|
| 1822 |
|
|
for(i=`DBG_CPU_CRC_LEN -1; i>=0; i=i-1)
|
| 1823 |
|
|
begin
|
| 1824 |
|
|
tdi_pad_i<=#1 crc_out[i];
|
| 1825 |
|
|
gen_clk(1);
|
| 1826 |
|
|
end
|
| 1827 |
|
|
|
| 1828 |
|
|
tdi_pad_i<=#1 1'hz;
|
| 1829 |
|
|
|
| 1830 |
|
|
crc_in = {`DBG_CPU_CRC_LEN{1'b1}}; // Initialize incoming CRC to all ff
|
| 1831 |
|
|
|
| 1832 |
|
|
for(i=`DBG_CPU_CTRL_LEN -1; i>=0; i=i-1) // data (used control bits)
|
| 1833 |
|
|
begin
|
| 1834 |
|
|
gen_clk(1);
|
| 1835 |
|
|
data[i] = tdo;
|
| 1836 |
|
|
end
|
| 1837 |
|
|
|
| 1838 |
|
|
for(i=`DBG_CPU_DR_LEN - `DBG_CPU_CTRL_LEN -1; i>=0; i=i-1) // unused control bits
|
| 1839 |
|
|
begin
|
| 1840 |
|
|
gen_clk(1);
|
| 1841 |
|
|
end
|
| 1842 |
|
|
|
| 1843 |
|
|
for(i=`DBG_CPU_STATUS_LEN -1; i>=0; i=i-1)
|
| 1844 |
|
|
begin
|
| 1845 |
|
|
gen_clk(1); // Generating clock to read out a status bit.
|
| 1846 |
|
|
status_cpu[i] = tdo;
|
| 1847 |
|
|
end
|
| 1848 |
|
|
|
| 1849 |
|
|
if (|status_cpu)
|
| 1850 |
|
|
begin
|
| 1851 |
|
|
$write("(*E) (%0t) debug_cpu_rd_ctrl: ", $time);
|
| 1852 |
|
|
casex (status_cpu)
|
| 1853 |
|
|
4'b1xxx : $display("CRC error !!!\n\n", $time);
|
| 1854 |
|
|
4'bx1xx : $display("Unknown command !!!\n\n", $time);
|
| 1855 |
|
|
4'bxx1x : $display("Unknown command !!!\n\n", $time);
|
| 1856 |
|
|
4'bxxx1 : $display("Unknown command !!!\n\n", $time);
|
| 1857 |
|
|
endcase
|
| 1858 |
|
|
$stop;
|
| 1859 |
|
|
end
|
| 1860 |
|
|
|
| 1861 |
|
|
|
| 1862 |
|
|
for(i=0; i<`DBG_CPU_CRC_LEN -1; i=i+1) // Getting in the CRC
|
| 1863 |
|
|
begin
|
| 1864 |
|
|
gen_clk(1);
|
| 1865 |
|
|
end
|
| 1866 |
|
|
|
| 1867 |
|
|
tms_pad_i<=#1 1'b1;
|
| 1868 |
|
|
gen_clk(1); // to exit1_dr
|
| 1869 |
|
|
|
| 1870 |
|
|
if (~crc_match_in)
|
| 1871 |
|
|
begin
|
| 1872 |
|
|
$display("(%0t) Incoming CRC failed !!!", $time);
|
| 1873 |
|
|
$stop;
|
| 1874 |
|
|
end
|
| 1875 |
|
|
|
| 1876 |
|
|
tms_pad_i<=#1 1'b1;
|
| 1877 |
|
|
gen_clk(1); // to update_dr
|
| 1878 |
|
|
tms_pad_i<=#1 1'b0;
|
| 1879 |
|
|
gen_clk(1); // to run_test_idle
|
| 1880 |
|
|
end
|
| 1881 |
|
|
endtask // debug_cpu_rd_ctrl
|
| 1882 |
|
|
|
| 1883 |
|
|
|
| 1884 |
|
|
|
| 1885 |
|
|
task debug_cpu_go;
|
| 1886 |
|
|
input wait_for_cpu_ready;
|
| 1887 |
|
|
input gen_crc_err;
|
| 1888 |
|
|
integer i;
|
| 1889 |
|
|
reg [4:0] bit_pointer;
|
| 1890 |
|
|
integer word_pointer;
|
| 1891 |
|
|
reg [31:0] tmp_data;
|
| 1892 |
|
|
reg [`DBG_CPU_CMD_LEN -1:0] command;
|
| 1893 |
|
|
|
| 1894 |
|
|
|
| 1895 |
|
|
begin
|
| 1896 |
|
|
$display("(%0t) Task debug_cpu_go (previous command was %0s): ", $time, last_cpu_cmd_text);
|
| 1897 |
|
|
command = `DBG_CPU_GO;
|
| 1898 |
|
|
word_pointer = 0;
|
| 1899 |
|
|
|
| 1900 |
|
|
tms_pad_i<=#1 1'b1;
|
| 1901 |
|
|
gen_clk(1);
|
| 1902 |
|
|
tms_pad_i<=#1 1'b0;
|
| 1903 |
|
|
gen_clk(2); // we are in shiftDR
|
| 1904 |
|
|
|
| 1905 |
|
|
crc_out = {`DBG_CPU_CRC_LEN{1'b1}}; // Initialize outgoing CRC to all ff
|
| 1906 |
|
|
|
| 1907 |
|
|
tdi_pad_i<=#1 1'b0; // module_select bit = 0
|
| 1908 |
|
|
calculate_crc(1'b0);
|
| 1909 |
|
|
gen_clk(1);
|
| 1910 |
|
|
|
| 1911 |
|
|
for(i=`DBG_CPU_CMD_LEN -1; i>=0; i=i-1)
|
| 1912 |
|
|
begin
|
| 1913 |
|
|
tdi_pad_i<=#1 command[i]; // command
|
| 1914 |
|
|
calculate_crc(command[i]);
|
| 1915 |
|
|
gen_clk(1);
|
| 1916 |
|
|
end
|
| 1917 |
|
|
|
| 1918 |
|
|
|
| 1919 |
|
|
if (last_cpu_cmd == `DBG_CPU_WRITE) // When DBG_CPU_WRITE was previously activated, data needs to be shifted.
|
| 1920 |
|
|
begin
|
| 1921 |
|
|
for (i=0; i<((length_global) << 3); i=i+1)
|
| 1922 |
|
|
begin
|
| 1923 |
|
|
tmp_data = wb_data[word_pointer];
|
| 1924 |
|
|
if ((!(i%32)) && (i>0))
|
| 1925 |
|
|
begin
|
| 1926 |
|
|
word_pointer = word_pointer + 1;
|
| 1927 |
|
|
end
|
| 1928 |
|
|
bit_pointer = 31-i[4:0];
|
| 1929 |
|
|
tdi_pad_i<=#1 tmp_data[bit_pointer];
|
| 1930 |
|
|
calculate_crc(tmp_data[bit_pointer]);
|
| 1931 |
|
|
gen_clk(1);
|
| 1932 |
|
|
|
| 1933 |
|
|
end
|
| 1934 |
|
|
end
|
| 1935 |
|
|
|
| 1936 |
|
|
for(i=`DBG_CPU_CRC_LEN -1; i>=1; i=i-1)
|
| 1937 |
|
|
begin
|
| 1938 |
|
|
tdi_pad_i<=#1 crc_out[i];
|
| 1939 |
|
|
gen_clk(1);
|
| 1940 |
|
|
end
|
| 1941 |
|
|
|
| 1942 |
|
|
if (gen_crc_err) // Generate crc error at last crc bit
|
| 1943 |
|
|
tdi_pad_i<=#1 ~crc_out[0]; // error crc
|
| 1944 |
|
|
else
|
| 1945 |
|
|
tdi_pad_i<=#1 crc_out[0]; // ok crc
|
| 1946 |
|
|
|
| 1947 |
|
|
if (wait_for_cpu_ready)
|
| 1948 |
|
|
begin
|
| 1949 |
|
|
tms_pad_i<=#1 1'b1;
|
| 1950 |
|
|
gen_clk(1); // to exit1_dr. Last CRC is shifted on this clk
|
| 1951 |
|
|
tms_pad_i<=#1 1'b0;
|
| 1952 |
|
|
gen_clk(1); // to pause_dr
|
| 1953 |
|
|
|
| 1954 |
|
|
#2; // wait a bit for tdo to activate
|
| 1955 |
|
|
while (tdo) // waiting for wb to send "ready"
|
| 1956 |
|
|
begin
|
| 1957 |
|
|
gen_clk(1); // staying in pause_dr
|
| 1958 |
|
|
end
|
| 1959 |
|
|
|
| 1960 |
|
|
tms_pad_i<=#1 1'b1;
|
| 1961 |
|
|
gen_clk(1); // to exit2_dr
|
| 1962 |
|
|
tms_pad_i<=#1 1'b0;
|
| 1963 |
|
|
gen_clk(1); // to shift_dr
|
| 1964 |
|
|
end
|
| 1965 |
|
|
else
|
| 1966 |
|
|
begin
|
| 1967 |
|
|
gen_clk(1); // Last CRC is shifted on this clk
|
| 1968 |
|
|
end
|
| 1969 |
|
|
|
| 1970 |
|
|
|
| 1971 |
|
|
tdi_pad_i<=#1 1'hz;
|
| 1972 |
|
|
crc_in = {`DBG_CPU_CRC_LEN{1'b1}}; // Initialize incoming CRC to all ff
|
| 1973 |
|
|
|
| 1974 |
|
|
if (last_cpu_cmd == `DBG_CPU_READ) // When DBG_CPU_READ was previously activated, data needs to be shifted.
|
| 1975 |
|
|
begin
|
| 1976 |
|
|
$display("\t\tGenerating %0d clocks to read %0d data bytes.", length_global<<3, length_global);
|
| 1977 |
|
|
word_pointer = 0; // Reset pointer
|
| 1978 |
|
|
for (i=0; i<(length_global<<3); i=i+1)
|
| 1979 |
|
|
begin
|
| 1980 |
|
|
gen_clk(1);
|
| 1981 |
|
|
if (i[4:0] == 31) // Latching data
|
| 1982 |
|
|
begin
|
| 1983 |
|
|
wb_data[word_pointer] = in_data_be;
|
| 1984 |
|
|
$display("\t\tin_data_be = 0x%x", in_data_be);
|
| 1985 |
|
|
word_pointer = word_pointer + 1;
|
| 1986 |
|
|
end
|
| 1987 |
|
|
end
|
| 1988 |
|
|
end
|
| 1989 |
|
|
|
| 1990 |
|
|
|
| 1991 |
|
|
for(i=`DBG_CPU_STATUS_LEN -1; i>=0; i=i-1)
|
| 1992 |
|
|
begin
|
| 1993 |
|
|
gen_clk(1); // Generating clock to read out a status bit.
|
| 1994 |
|
|
status_cpu[i] = tdo;
|
| 1995 |
|
|
end
|
| 1996 |
|
|
|
| 1997 |
|
|
if (|status_cpu)
|
| 1998 |
|
|
begin
|
| 1999 |
|
|
$write("(*E) (%0t) debug_cpu_go error: ", $time);
|
| 2000 |
|
|
casex (status_cpu)
|
| 2001 |
|
|
4'b1xxx : $display("CRC error !!!\n\n", $time);
|
| 2002 |
|
|
4'bx1xx : $display("Unknown command !!!\n\n", $time);
|
| 2003 |
|
|
4'bxx1x : $display("??? error !!!\n\n", $time);
|
| 2004 |
|
|
4'bxxx1 : $display("Overrun/Underrun !!!\n\n", $time);
|
| 2005 |
|
|
endcase
|
| 2006 |
|
|
$stop;
|
| 2007 |
|
|
end
|
| 2008 |
|
|
|
| 2009 |
|
|
|
| 2010 |
|
|
for(i=0; i<`DBG_CPU_CRC_LEN -1; i=i+1) // Getting in the CRC
|
| 2011 |
|
|
begin
|
| 2012 |
|
|
gen_clk(1);
|
| 2013 |
|
|
end
|
| 2014 |
|
|
|
| 2015 |
|
|
tms_pad_i<=#1 1'b1;
|
| 2016 |
|
|
gen_clk(1); // to exit1_dr
|
| 2017 |
|
|
|
| 2018 |
|
|
if (~crc_match_in)
|
| 2019 |
|
|
begin
|
| 2020 |
|
|
$display("(%0t) Incoming CRC failed !!!", $time);
|
| 2021 |
|
|
$stop;
|
| 2022 |
|
|
end
|
| 2023 |
|
|
|
| 2024 |
|
|
tms_pad_i<=#1 1'b1;
|
| 2025 |
|
|
gen_clk(1); // to update_dr
|
| 2026 |
|
|
tms_pad_i<=#1 1'b0;
|
| 2027 |
|
|
gen_clk(1); // to run_test_idle
|
| 2028 |
|
|
end
|
| 2029 |
|
|
endtask // debug_cpu_go
|
| 2030 |
|
|
`endif // DBG_CPU_SUPPORTED
|
| 2031 |
|
|
|
| 2032 |
|
|
|
| 2033 |
|
|
|
| 2034 |
|
|
always @ (posedge tck_pad_i)
|
| 2035 |
|
|
begin
|
| 2036 |
|
|
in_data_be[31:1] <= #1 in_data_be[30:0];
|
| 2037 |
|
|
in_data_be[0] <= #1 tdo;
|
| 2038 |
|
|
|
| 2039 |
|
|
in_data_le[31] <= #1 tdo;
|
| 2040 |
|
|
in_data_le[30:0] <= #1 in_data_le[31:1];
|
| 2041 |
|
|
end
|
| 2042 |
|
|
|
| 2043 |
|
|
|
| 2044 |
|
|
|
| 2045 |
|
|
// Calculating outgoing CRC
|
| 2046 |
|
|
task calculate_crc;
|
| 2047 |
|
|
input data;
|
| 2048 |
|
|
|
| 2049 |
|
|
begin
|
| 2050 |
|
|
crc_out[0] <= #1 data ^ crc_out[31];
|
| 2051 |
|
|
crc_out[1] <= #1 data ^ crc_out[0] ^ crc_out[31];
|
| 2052 |
|
|
crc_out[2] <= #1 data ^ crc_out[1] ^ crc_out[31];
|
| 2053 |
|
|
crc_out[3] <= #1 crc_out[2];
|
| 2054 |
|
|
crc_out[4] <= #1 data ^ crc_out[3] ^ crc_out[31];
|
| 2055 |
|
|
crc_out[5] <= #1 data ^ crc_out[4] ^ crc_out[31];
|
| 2056 |
|
|
crc_out[6] <= #1 crc_out[5];
|
| 2057 |
|
|
crc_out[7] <= #1 data ^ crc_out[6] ^ crc_out[31];
|
| 2058 |
|
|
crc_out[8] <= #1 data ^ crc_out[7] ^ crc_out[31];
|
| 2059 |
|
|
crc_out[9] <= #1 crc_out[8];
|
| 2060 |
|
|
crc_out[10] <= #1 data ^ crc_out[9] ^ crc_out[31];
|
| 2061 |
|
|
crc_out[11] <= #1 data ^ crc_out[10] ^ crc_out[31];
|
| 2062 |
|
|
crc_out[12] <= #1 data ^ crc_out[11] ^ crc_out[31];
|
| 2063 |
|
|
crc_out[13] <= #1 crc_out[12];
|
| 2064 |
|
|
crc_out[14] <= #1 crc_out[13];
|
| 2065 |
|
|
crc_out[15] <= #1 crc_out[14];
|
| 2066 |
|
|
crc_out[16] <= #1 data ^ crc_out[15] ^ crc_out[31];
|
| 2067 |
|
|
crc_out[17] <= #1 crc_out[16];
|
| 2068 |
|
|
crc_out[18] <= #1 crc_out[17];
|
| 2069 |
|
|
crc_out[19] <= #1 crc_out[18];
|
| 2070 |
|
|
crc_out[20] <= #1 crc_out[19];
|
| 2071 |
|
|
crc_out[21] <= #1 crc_out[20];
|
| 2072 |
|
|
crc_out[22] <= #1 data ^ crc_out[21] ^ crc_out[31];
|
| 2073 |
|
|
crc_out[23] <= #1 data ^ crc_out[22] ^ crc_out[31];
|
| 2074 |
|
|
crc_out[24] <= #1 crc_out[23];
|
| 2075 |
|
|
crc_out[25] <= #1 crc_out[24];
|
| 2076 |
|
|
crc_out[26] <= #1 data ^ crc_out[25] ^ crc_out[31];
|
| 2077 |
|
|
crc_out[27] <= #1 crc_out[26];
|
| 2078 |
|
|
crc_out[28] <= #1 crc_out[27];
|
| 2079 |
|
|
crc_out[29] <= #1 crc_out[28];
|
| 2080 |
|
|
crc_out[30] <= #1 crc_out[29];
|
| 2081 |
|
|
crc_out[31] <= #1 crc_out[30];
|
| 2082 |
|
|
end
|
| 2083 |
|
|
endtask // calculate_crc
|
| 2084 |
|
|
|
| 2085 |
|
|
|
| 2086 |
|
|
// Calculating and checking input CRC
|
| 2087 |
|
|
always @(posedge tck_pad_i)
|
| 2088 |
|
|
begin
|
| 2089 |
|
|
crc_in[0] <= #1 tdo ^ crc_in[31];
|
| 2090 |
|
|
crc_in[1] <= #1 tdo ^ crc_in[0] ^ crc_in[31];
|
| 2091 |
|
|
crc_in[2] <= #1 tdo ^ crc_in[1] ^ crc_in[31];
|
| 2092 |
|
|
crc_in[3] <= #1 crc_in[2];
|
| 2093 |
|
|
crc_in[4] <= #1 tdo ^ crc_in[3] ^ crc_in[31];
|
| 2094 |
|
|
crc_in[5] <= #1 tdo ^ crc_in[4] ^ crc_in[31];
|
| 2095 |
|
|
crc_in[6] <= #1 crc_in[5];
|
| 2096 |
|
|
crc_in[7] <= #1 tdo ^ crc_in[6] ^ crc_in[31];
|
| 2097 |
|
|
crc_in[8] <= #1 tdo ^ crc_in[7] ^ crc_in[31];
|
| 2098 |
|
|
crc_in[9] <= #1 crc_in[8];
|
| 2099 |
|
|
crc_in[10] <= #1 tdo ^ crc_in[9] ^ crc_in[31];
|
| 2100 |
|
|
crc_in[11] <= #1 tdo ^ crc_in[10] ^ crc_in[31];
|
| 2101 |
|
|
crc_in[12] <= #1 tdo ^ crc_in[11] ^ crc_in[31];
|
| 2102 |
|
|
crc_in[13] <= #1 crc_in[12];
|
| 2103 |
|
|
crc_in[14] <= #1 crc_in[13];
|
| 2104 |
|
|
crc_in[15] <= #1 crc_in[14];
|
| 2105 |
|
|
crc_in[16] <= #1 tdo ^ crc_in[15] ^ crc_in[31];
|
| 2106 |
|
|
crc_in[17] <= #1 crc_in[16];
|
| 2107 |
|
|
crc_in[18] <= #1 crc_in[17];
|
| 2108 |
|
|
crc_in[19] <= #1 crc_in[18];
|
| 2109 |
|
|
crc_in[20] <= #1 crc_in[19];
|
| 2110 |
|
|
crc_in[21] <= #1 crc_in[20];
|
| 2111 |
|
|
crc_in[22] <= #1 tdo ^ crc_in[21] ^ crc_in[31];
|
| 2112 |
|
|
crc_in[23] <= #1 tdo ^ crc_in[22] ^ crc_in[31];
|
| 2113 |
|
|
crc_in[24] <= #1 crc_in[23];
|
| 2114 |
|
|
crc_in[25] <= #1 crc_in[24];
|
| 2115 |
|
|
crc_in[26] <= #1 tdo ^ crc_in[25] ^ crc_in[31];
|
| 2116 |
|
|
crc_in[27] <= #1 crc_in[26];
|
| 2117 |
|
|
crc_in[28] <= #1 crc_in[27];
|
| 2118 |
|
|
crc_in[29] <= #1 crc_in[28];
|
| 2119 |
|
|
crc_in[30] <= #1 crc_in[29];
|
| 2120 |
|
|
crc_in[31] <= #1 crc_in[30];
|
| 2121 |
|
|
end
|
| 2122 |
|
|
|
| 2123 |
|
|
assign crc_match_in = crc_in == 32'h0;
|
| 2124 |
|
|
|
| 2125 |
|
|
|
| 2126 |
|
|
|
| 2127 |
|
|
/**********************************************************************************
|
| 2128 |
|
|
* *
|
| 2129 |
|
|
* Printing the information to the screen *
|
| 2130 |
|
|
* *
|
| 2131 |
|
|
**********************************************************************************/
|
| 2132 |
|
|
|
| 2133 |
|
|
`ifdef DBG_MORE_INFO
|
| 2134 |
|
|
always @ (posedge tck_pad_i)
|
| 2135 |
|
|
begin
|
| 2136 |
|
|
if(dbg_tb.i_tap_top.update_ir)
|
| 2137 |
|
|
case(dbg_tb.i_tap_top.jtag_ir[`IR_LENGTH-1:0])
|
| 2138 |
|
|
`EXTEST : $display("\tInstruction EXTEST entered");
|
| 2139 |
|
|
`SAMPLE_PRELOAD : $display("\tInstruction SAMPLE_PRELOAD entered");
|
| 2140 |
|
|
`IDCODE : $display("\tInstruction IDCODE entered");
|
| 2141 |
|
|
`MBIST : $display("\tInstruction MBIST entered");
|
| 2142 |
|
|
`DEBUG : $display("\tInstruction DEBUG entered");
|
| 2143 |
|
|
`BYPASS : $display("\tInstruction BYPASS entered");
|
| 2144 |
|
|
default : $display("\n\tInstruction not valid. Instruction BYPASS activated !!!");
|
| 2145 |
|
|
endcase
|
| 2146 |
|
|
end
|
| 2147 |
|
|
`endif
|
| 2148 |
|
|
|
| 2149 |
|
|
|
| 2150 |
|
|
// We never use following states: exit2_ir, exit2_dr, pause_ir or pause_dr
|
| 2151 |
|
|
always @ (posedge tck_pad_i)
|
| 2152 |
|
|
begin
|
| 2153 |
|
|
if(dbg_tb.i_tap_top.pause_ir | dbg_tb.i_tap_top.exit2_ir)
|
| 2154 |
|
|
begin
|
| 2155 |
|
|
$display("\n(%0t) ERROR: State pause_ir or exit2_ir detected.", $time);
|
| 2156 |
|
|
$display("(%0t) Simulation stopped !!!", $time);
|
| 2157 |
|
|
$stop;
|
| 2158 |
|
|
end
|
| 2159 |
|
|
end
|
| 2160 |
|
|
|
| 2161 |
|
|
|
| 2162 |
|
|
|
| 2163 |
|
|
|
| 2164 |
|
|
endmodule // dbg_tb
|
| 2165 |
|
|
|
| 2166 |
|
|
|
