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//////////////////////////////////////////////////////////////////////

////                                                              ////

////  ZBT RAM Controller for RC203 board                          ////

////                                                              ////

////                                                              ////

////  Description                                                 ////

////  Manages access from Wishbone to ZBT external RAM            ////

////                                                              ////

////  To Do:                                                      ////

////   - nothing really                                           ////

////                                                              ////

////  Author(s):                                                  ////

////      - Javier Castillo, javier.castillo@urjc.es              ////

////                                                              ////

//////////////////////////////////////////////////////////////////////

////                                                              ////

//// Copyright (C) 2004 OpenCores                                 ////

////                                                              ////

//// This source file may be used and distributed without         ////

//// restriction provided that this copyright statement is not    ////

//// removed from the file and that any derivative work contains  ////

//// the original copyright notice and the associated disclaimer. ////

////                                                              ////

//// This source file is free software; you can redistribute it   ////

//// and/or modify it under the terms of the GNU Lesser General   ////

//// Public License as published by the Free Software Foundation; ////

//// either version 2.1 of the License, or (at your option) any   ////

//// later version.                                               ////

////                                                              ////

//// This source is distributed in the hope that it will be       ////

//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////

//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////

//// PURPOSE.  See the GNU Lesser General Public License for more ////

//// details.                                                     ////

////                                                              ////

//// You should have received a copy of the GNU Lesser General    ////

//// Public License along with this source; if not, download it   ////

//// from http://www.opencores.org/lgpl.shtml                     ////

////                                                              ////

//////////////////////////////////////////////////////////////////////

//

// CVS Revision History

//

// $Log: not supported by cvs2svn $

// Revision 1.2  2005/09/16 00:39:04  jcastillo

// no message

//

// Revision 1.1.1.1  2004/12/13 17:16:09  jcastillo

// Firt import of OR1200 over Celoxica RC203 platform

//

// synopsys translate_off

`include "timescale.v"

// synopsys translate_on

module wb_zbt_controller(clk,reset,

                         wb_stb_i,wb_dat_o,wb_dat_i,

                         wb_ack_o,wb_adr_i,wb_we_i,

                         wb_cyc_i,wb_sel_i,

                         // Bank 0

                         nRW0,address0,data0,

                         nBW0,nCS0,

                         // Bank 1

                         nRW1,address1,data1,

                         nBW1,nCS1

                        );

input         clk;

input         reset;

//

// WISHBONE INTERFACE

//

input         wb_stb_i;

output [31:0] wb_dat_o;

input  [31:0] wb_dat_i;

output        wb_ack_o;

input  [31:0] wb_adr_i;

input         wb_we_i;

input         wb_cyc_i;

input  [3:0]  wb_sel_i;

//

// RAM PINS Bank 0

//

output        nRW0;

output [19:0] address0;

inout  [31:0] data0;   //INOUT

output [3:0]  nBW0;

output        nCS0;

// 

// RAM PINS Bank 1

//

output        nRW1;

output [19:0] address1;

inout  [31:0] data1;   //INOUT

output [3:0]  nBW1;

output        nCS1;

reg  [31:0]   wb_dat_o;

reg           wb_ack_o;

reg           nRW0;

reg  [19:0]   address0;

reg  [3:0]    nBW0;

wire [31:0]   data0;

wire          nCS0;

reg           nRW1;

reg  [19:0]   address1;

reg  [3:0]    nBW1;

wire [31:0]   data1;

wire          nCS1;

reg   next_bank_select;

reg   bank_select;

reg   next_reading;

reg   reading;

reg   next_writing;

reg   writing;

assign nCS0 = 1'b0;

assign nCS1 = 1'b0;

assign data0 = (writing && !bank_select) ? wb_dat_i : 32'hZ;

assign data1 = (writing && bank_select) ? wb_dat_i : 32'hZ;

//read_data:

always @(posedge clk or posedge reset)

begin

   if(reset==1)

   begin

     wb_ack_o<=#1 1'b0;

     wb_dat_o<=#1 1'b0;

   end

   else

   begin

     wb_dat_o <= #1 1'b0;

     wb_ack_o <= #1 1'b0;

     if (reading)

     begin

       wb_ack_o <= #1 1'b1;

       if(bank_select== 1)

         wb_dat_o <= #1 data1;

       else

         wb_dat_o <= #1 data0;

     end

     else if(writing)

     begin

      wb_ack_o  <= #1 1'b1;

     end

  end

end

reg [31:0] addr_var;

always @(wb_adr_i or wb_stb_i or wb_we_i or wb_cyc_i or

         wb_sel_i or reading or writing or wb_ack_o)

   begin

   next_reading  = 1'b0;

   next_writing  = 1'b0;

   addr_var = wb_adr_i ;

   addr_var = addr_var>>2;

   address0  = addr_var[20:1];

   address1  = addr_var[20:1];

   // We select bank using low bits so people with

   // non-expert versions of the rc20x boards can

   // use both RAM banks without changing any RTL.

   next_bank_select = addr_var[0];

   nRW0  = 1;

   nRW1  = 1;

   nBW0 = ~wb_sel_i ;

   nBW1 = ~wb_sel_i ;

   if(~reading && ~writing && ~wb_ack_o)

   begin

     if (wb_cyc_i && wb_stb_i && !wb_we_i)

     begin

       // Single memory read 

       next_reading  = 1'b1;

     end

     else if (wb_cyc_i && wb_stb_i && wb_we_i)

     begin

       // Single memory write

       if(next_bank_select == 1)

         nRW1 = 0;

       else

         nRW0 = 0;

       next_writing  = 1'b1;

     end

   end

 end

//register_proc:

always @(posedge clk or posedge reset)

   begin

   if (reset )

      begin

      reading  <= #1 1'b0;

      writing  <= #1 1'b0;

      end

   else

      begin

      bank_select <= #1 next_bank_select;

      writing  <= #1 next_writing;

      reading  <= #1 next_reading;

      end

   end

endmodule