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//////////////////////////////////////////////////////////////////////

////                                                              ////

////  OR1200 over a RC203 platform top file                       ////

////                                                              ////

////                                                              ////

////  Description                                                 ////

////  This block connectes the RISC and peripheral controller     ////

////  cores together.                                             ////

////                                                              ////

////  To Do:                                                      ////

////   - nothing really                                           ////

////                                                              ////

////  Author(s):                                                  ////

////      - Javier Castillo, javier.castillo@urjc.es              ////

////                                                              ////

//////////////////////////////////////////////////////////////////////

////                                                              ////

//// Copyright (C) 2004 OpenCores                                 ////

////                                                              ////

//// This source file may be used and distributed without         ////

//// restriction provided that this copyright statement is not    ////

//// removed from the file and that any derivative work contains  ////

//// the original copyright notice and the associated disclaimer. ////

////                                                              ////

//// This source file is free software; you can redistribute it   ////

//// and/or modify it under the terms of the GNU Lesser General   ////

//// Public License as published by the Free Software Foundation; ////

//// either version 2.1 of the License, or (at your option) any   ////

//// later version.                                               ////

////                                                              ////

//// This source is distributed in the hope that it will be       ////

//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////

//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////

//// PURPOSE.  See the GNU Lesser General Public License for more ////

//// details.                                                     ////

////                                                              ////

//// You should have received a copy of the GNU Lesser General    ////

//// Public License along with this source; if not, download it   ////

//// from http://www.opencores.org/lgpl.shtml                     ////

////                                                              ////

//////////////////////////////////////////////////////////////////////

//

// CVS Revision History

//

// $Log: not supported by cvs2svn $

// Revision 1.4  2005/10/27 17:20:50  jcastillo

// Supports two RAM banks by Jacob Bower

//

// Revision 1.3  2005/09/16 00:39:03  jcastillo

// no message

//

// Revision 1.2  2005/05/26 12:25:01  jcastillo

// Added support for ethernet chip

//

// Revision 1.1.1.1  2004/12/13 17:14:31  jcastillo

// Firt import of OR1200 over Celoxica RC203 platform

//

// synopsys translate_off

`include "timescale.v"

// synopsys translate_on

`include "or1200_defines.v"

//

// Platform description

//

`define APP_INT_UART    2

`define APP_INT_ETH         4

`define APP_ADDR_DEC_W  8

`define APP_ADDR_SRAM   `APP_ADDR_DEC_W'h00

`define APP_ADDR_FLASH  `APP_ADDR_DEC_W'hf0

`define APP_ADDR_DECP_W  4

`define APP_ADDR_PERIP  `APP_ADDR_DEC_W'h9

`define APP_ADDR_VGA    `APP_ADDR_DEC_W'h97

`define APP_ADDR_ETH    `APP_ADDR_DEC_W'h92

`define APP_ADDR_AUDIO  `APP_ADDR_DEC_W'h9d

`define APP_ADDR_UART   `APP_ADDR_DEC_W'h90

`define APP_ADDR_PS2    `APP_ADDR_DEC_W'h94

`define APP_ADDR_RES1   `APP_ADDR_DEC_W'h9e

`define APP_ADDR_RES2   `APP_ADDR_DEC_W'h9f

`define APP_ADDR_FAKEMC 4'h6

module soc(

   clk,reset,

   //SRAM Ports

   sram_nRW0,sram_clk0,sram_address0,

   sram_data0,sram_nBW0,sram_nCS0,

   sram_nRW1,sram_clk1,sram_address1,

   sram_data1,sram_nBW1,sram_nCS1,

   //UART ports

   uart_stx,uart_srx,

   //JTAG ports

   jtag_tdi,jtag_tms,jtag_tck,

   jtag_tdo,

   //Ethernet ports

   eth_nREAD,eth_nWRITE,

   eth_address,eth_data,

   eth_nBE,eth_reset,eth_int

   );

   parameter dw = `OR1200_OPERAND_WIDTH;

   parameter aw = `OR1200_OPERAND_WIDTH;

   parameter ppic_ints = `OR1200_PIC_INTS;

   input         clk /* synthesis xc_clockbuftype = "BUFGDLL" */;

   input         reset;

   output        sram_nRW0;

   output [19:0] sram_address0;

   inout  [31:0] sram_data0;

   output [3:0]  sram_nBW0;

   output        sram_nCS0;

   output        sram_clk0;

   output        sram_nRW1;

   output [19:0] sram_address1;

   inout  [31:0] sram_data1;

   output [3:0]  sram_nBW1;

   output        sram_nCS1;

   output        sram_clk1;

   output        uart_stx;

   input         uart_srx;

   input         jtag_tdi;

   input         jtag_tms;

   input         jtag_tck;

   output        jtag_tdo;

   //

   // SMC91111 PINS

   //

   output        eth_nREAD;

   output        eth_nWRITE;

   output [2:0]  eth_address;

   inout  [15:0] eth_data;   //INOUT

   output [1:0]  eth_nBE;

   output        eth_reset;

   input         eth_int;

assign sram_clk0=clk;

assign sram_clk1=clk;

assign pic_ints[`APP_INT_ETH]=eth_int;

//Declaring signals

wire    [1:0]             clmode;        // 00 WB=RISC, 01 WB=RISC/2, 10 N/A, 11 WB=RISC/4

wire    [ppic_ints-1:0]    pic_ints;

//

// Instruction WISHBONE interface

//

wire             iwb_ack;       // normal termination

wire             iwb_err;       // termination w/ error

wire             iwb_rty;       // termination w/ retry

wire  [dw-1:0]   iwb_dat_o;      // reg data bus

wire             iwb_cyc;       // cycle valid wire

wire  [aw-1:0]   iwb_adr;        // address bus wires

wire             iwb_stb;       // strobe wire

wire             iwb_we;        // indicates write transfer

wire  [3:0]      iwb_sel;        // byte select wires

wire  [dw-1:0]   iwb_dat_i;      // wire data bus

wire             iwb_cab;

`ifdef OR1200_WB_B3

wire  [2:0]      iwb_cti;        // cycle type identifier

wire  [1:0]      iwb_bte;        // burst type extension

`endif

//

// Data WISHBONE interface

//

wire               dwb_ack;     // normal termination

wire               dwb_err;     // termination w/ error

wire               dwb_rty;     // termination w/ retry

wire  [dw-1:0]     dwb_dat_i;    // data bus

wire               dwb_cyc;     // cycle valid wire

wire  [aw-1:0]     dwb_adr;      // address bus wires

wire               dwb_stb;     // strobe wire

wire               dwb_we;      // indicates write transfer

wire  [3:0]        dwb_sel;      // byte select wires

wire  [dw-1:0]     dwb_dat_o;    // wire data bus

wire               dwb_cab;

`ifdef OR1200_WB_B3

wire  [2:0]        dwb_cti;      // cycle type identifier

wire  [1:0]        dwb_bte;      // burst type extension

`endif

//

// Power Management

//

wire                       pm_cpustall;

//

//  ZBT SRAM Controller

//

wire  [31:0]  sram_wb_dat_i;

wire  [31:0]  sram_wb_dat_o;

wire  [31:0]  sram_wb_adr;

wire  [3:0]   sram_wb_sel;

wire          sram_wb_we;

wire          sram_wb_cyc;

wire          sram_wb_stb;

wire          sram_wb_ack;

//

//  ROM Controller

//

wire  [31:0]  rom_wb_dat_i;

wire  [31:0]  rom_wb_dat_o;

wire  [31:0]  rom_wb_adr;

wire  [3:0]   rom_wb_sel;

wire          rom_wb_we;

wire          rom_wb_cyc;

wire          rom_wb_stb;

wire          rom_wb_ack;

//

// UART16550 core slave i/f wires

//

wire  [31:0]  wb_us_dat_i;

wire  [31:0]  wb_us_dat_o;

wire  [31:0]  wb_us_adr_i;

wire  [3:0]   wb_us_sel_i;

wire          wb_us_we_i;

wire          wb_us_cyc_i;

wire          wb_us_stb_i;

wire          wb_us_ack_o;

wire          wb_us_err_o;

//

// Wires to internal ROM

//

wire [14:0]   rom_address;

wire [31:0]   rom_data;

//

//  Ethernet Controller

//

wire  [31:0]  eth_wb_dat_i;

wire  [31:0]  eth_wb_dat_o;

wire  [31:0]  eth_wb_adr;

wire  [3:0]   eth_wb_sel;

wire          eth_wb_we;

wire          eth_wb_cyc;

wire          eth_wb_stb;

wire          eth_wb_ack;

//

// Debug core master i/f wires

//

wire  [31:0]  wb_dm_adr_o;

wire  [31:0]  wb_dm_dat_i;

wire  [31:0]  wb_dm_dat_o;

wire  [3:0]   wb_dm_sel_o;

wire          wb_dm_we_o;

wire          wb_dm_stb_o;

wire          wb_dm_cyc_o;

wire          wb_dm_cab_o;

wire          wb_dm_ack_i;

wire          wb_dm_err_i;

//

// Debug <-> RISC wires

//

wire  [3:0]   dbg_lss;

wire  [1:0]   dbg_is;

wire  [10:0]  dbg_wp;

wire          dbg_bp;

wire  [31:0]  dbg_dat_dbg;

wire  [31:0]  dbg_dat_risc;

wire  [31:0]  dbg_adr;

wire          dbg_ewt;

wire          dbg_stall;

wire          dbg_we;

wire          dbg_stb;

wire          dbg_ack;

//

// RISC Instruction address for Flash

//

// Until first access to real Flash area,

// it is always prefixed with Flash area prefix.

// This way we have flash at base address 0x0

// during reset vector execution (boot). First

// access to real Flash area will automatically

// move SRAM to 0x0.

//

reg          prefix_flash;

wire  [31:0] iwb_fake_adr;

wire         dwb_ack_s;

//always @(posedge clk or posedge reset)

//      if (reset)

//      begin

//              prefix_flash <= #1 1'b1;

//      end     

//      else if (iwb_cyc && (iwb_adr[31:32-`APP_ADDR_DEC_W] == `APP_ADDR_FLASH))

//      begin

//              prefix_flash <= #1 1'b0;

//      end     

//assign iwb_fake_adr = prefix_flash ? {`APP_ADDR_FLASH, iwb_adr[31-`APP_ADDR_DEC_W:0]} : iwb_adr;

//assign dwb_ack = (dwb_adr[31:28] == `APP_ADDR_FAKEMC) && dwb_cyc && dwb_stb ? 1'b1 : dwb_ack_s;             

assign iwb_fake_adr = iwb_adr;

assign dwb_ack =  dwb_ack_s;

//

// Instantiation of the Traffic COP

//

tc_top #(`APP_ADDR_DEC_W,

         `APP_ADDR_SRAM,

         `APP_ADDR_DEC_W,

         `APP_ADDR_FLASH,

         `APP_ADDR_DECP_W,

         `APP_ADDR_PERIP,

         `APP_ADDR_DEC_W,

         `APP_ADDR_VGA,

         `APP_ADDR_ETH,

         `APP_ADDR_AUDIO,

         `APP_ADDR_UART,

         `APP_ADDR_PS2,

         `APP_ADDR_RES1,

         `APP_ADDR_RES2

        ) tc_top (

        // WISHBONE common

        .wb_clk_i  ( clk ),

        .wb_rst_i  ( reset ),

        // WISHBONE Initiator 0

        .i0_wb_cyc_i ( 1'b0 ),

        .i0_wb_stb_i ( 1'b0 ),

        .i0_wb_cab_i ( 1'b0 ),

        .i0_wb_adr_i ( 32'h0000_0000 ),

        .i0_wb_sel_i ( 4'b0000 ),

        .i0_wb_we_i  ( 1'b0 ),

        .i0_wb_dat_i ( 32'h0000_0000 ),

        .i0_wb_dat_o ( ),

        .i0_wb_ack_o ( ),

        .i0_wb_err_o ( ),

        // WISHBONE Initiator 1

        .i1_wb_cyc_i ( 1'b0 ),

        .i1_wb_stb_i ( 1'b0 ),

        .i1_wb_cab_i ( 1'b0 ),

        .i1_wb_adr_i ( 32'h0000_0000 ),

        .i1_wb_sel_i ( 4'b0000 ),

        .i1_wb_we_i  ( 1'b0 ),

        .i1_wb_dat_i ( 32'h0000_0000 ),

        .i1_wb_dat_o ( ),

        .i1_wb_ack_o ( ),

        .i1_wb_err_o ( ),

        // WISHBONE Initiator 2

        .i2_wb_cyc_i ( 1'b0 ),

        .i2_wb_stb_i ( 1'b0 ),

        .i2_wb_cab_i ( 1'b0 ),

        .i2_wb_adr_i ( 32'h0000_0000 ),

        .i2_wb_sel_i ( 4'b0000 ),

        .i2_wb_we_i  ( 1'b0 ),

        .i2_wb_dat_i ( 32'h0000_0000 ),

        .i2_wb_dat_o ( ),

        .i2_wb_ack_o ( ),

        .i2_wb_err_o ( ),

        // WISHBONE Initiator 3

        .i3_wb_cyc_i ( wb_dm_cyc_o ),

        .i3_wb_stb_i ( wb_dm_stb_o ),

        .i3_wb_cab_i ( wb_dm_cab_o ),

        .i3_wb_adr_i ( wb_dm_adr_o ),

        .i3_wb_sel_i ( wb_dm_sel_o ),

        .i3_wb_we_i  ( wb_dm_we_o  ),

        .i3_wb_dat_i ( wb_dm_dat_o ),

        .i3_wb_dat_o ( wb_dm_dat_i ),

        .i3_wb_ack_o ( wb_dm_ack_i ),

        .i3_wb_err_o ( ),

        // WISHBONE Initiator 4

        .i4_wb_cyc_i ( dwb_cyc ),

        .i4_wb_stb_i ( dwb_stb ),

        .i4_wb_cab_i ( dwb_cab ),

        .i4_wb_adr_i ( dwb_adr ),

        .i4_wb_sel_i ( dwb_sel ),

        .i4_wb_we_i  ( dwb_we  ),

        .i4_wb_dat_i ( dwb_dat_o),

        .i4_wb_dat_o ( dwb_dat_i ),

        .i4_wb_ack_o ( dwb_ack_s ),

        .i4_wb_err_o ( ),

        // WISHBONE Initiator 5

        .i5_wb_cyc_i ( iwb_cyc ),

        .i5_wb_stb_i ( iwb_stb ),

        .i5_wb_cab_i ( iwb_cab ),

        .i5_wb_adr_i ( iwb_fake_adr ),

        .i5_wb_sel_i ( iwb_sel ),

        .i5_wb_we_i  ( iwb_we  ),

        .i5_wb_dat_i ( iwb_dat_o ),

        .i5_wb_dat_o ( iwb_dat_i ),

        .i5_wb_ack_o ( iwb_ack ),

        .i5_wb_err_o ( ),

        // WISHBONE Initiator 6

        .i6_wb_cyc_i ( 1'b0 ),

        .i6_wb_stb_i ( 1'b0 ),

        .i6_wb_cab_i ( 1'b0 ),

        .i6_wb_adr_i ( 32'h0000_0000 ),

        .i6_wb_sel_i ( 4'b0000 ),

        .i6_wb_we_i  ( 1'b0 ),

        .i6_wb_dat_i ( 32'h0000_0000 ),

        .i6_wb_dat_o ( ),

        .i6_wb_ack_o ( ),

        .i6_wb_err_o ( ),

        // WISHBONE Initiator 7

        .i7_wb_cyc_i ( 1'b0 ),

        .i7_wb_stb_i ( 1'b0 ),

        .i7_wb_cab_i ( 1'b0 ),

        .i7_wb_adr_i ( 32'h0000_0000 ),

        .i7_wb_sel_i ( 4'b0000 ),

        .i7_wb_we_i  ( 1'b0 ),

        .i7_wb_dat_i ( 32'h0000_0000 ),

        .i7_wb_dat_o ( ),

        .i7_wb_ack_o ( ),

        .i7_wb_err_o ( ),

        // WISHBONE Target 0

        .t0_wb_cyc_o ( sram_wb_cyc ),

        .t0_wb_stb_o ( sram_wb_stb ),

        .t0_wb_cab_o ( sram_wb_cab ),

        .t0_wb_adr_o ( sram_wb_adr ),

        .t0_wb_sel_o ( sram_wb_sel ),

        .t0_wb_we_o  ( sram_wb_we  ),

        .t0_wb_dat_o ( sram_wb_dat_i ),

        .t0_wb_dat_i ( sram_wb_dat_o ),

        .t0_wb_ack_i ( sram_wb_ack ),

        .t0_wb_err_i ( 1'b0 ),

        // WISHBONE Target 1

        .t1_wb_cyc_o ( rom_wb_cyc ),

        .t1_wb_stb_o ( rom_wb_stb ),

        .t1_wb_cab_o ( rom_wb_cab ),

        .t1_wb_adr_o ( rom_wb_adr ),

        .t1_wb_sel_o ( rom_wb_sel ),

        .t1_wb_we_o  ( rom_wb_we  ),

        .t1_wb_dat_o ( rom_wb_dat_i ),

        .t1_wb_dat_i ( rom_wb_dat_o ),

        .t1_wb_ack_i ( rom_wb_ack ),

        .t1_wb_err_i ( 1'b0 ),

        // WISHBONE Target 2

        .t2_wb_cyc_o ( ),

        .t2_wb_stb_o ( ),

        .t2_wb_cab_o ( ),

        .t2_wb_adr_o ( ),

        .t2_wb_sel_o ( ),

        .t2_wb_we_o  ( ),

        .t2_wb_dat_o ( ),

        .t2_wb_dat_i ( 32'h0000_0000 ),

        .t2_wb_ack_i ( 1'b0 ),

        .t2_wb_err_i ( 1'b1 ),

        // WISHBONE Target 3

        .t3_wb_cyc_o ( eth_wb_cyc ),

        .t3_wb_stb_o ( eth_wb_stb ),

        .t3_wb_cab_o ( eth_wb_cab ),

        .t3_wb_adr_o ( eth_wb_adr ),

        .t3_wb_sel_o ( eth_wb_sel ),

        .t3_wb_we_o  ( eth_wb_we  ),

        .t3_wb_dat_o ( eth_wb_dat_i ),

        .t3_wb_dat_i ( eth_wb_dat_o ),

        .t3_wb_ack_i ( eth_wb_ack ),

        .t3_wb_err_i ( 1'b0 ),

        // WISHBONE Target 4

        .t4_wb_cyc_o ( ),

        .t4_wb_stb_o ( ),

        .t4_wb_cab_o ( ),

        .t4_wb_adr_o ( ),

        .t4_wb_sel_o ( ),

        .t4_wb_we_o  ( ),

        .t4_wb_dat_o ( ),

        .t4_wb_dat_i ( 32'h0000_0000 ),

        .t4_wb_ack_i ( 1'b0 ),

        .t4_wb_err_i ( 1'b1 ),

        // WISHBONE Target 5

        .t5_wb_cyc_o ( wb_us_cyc_i ),

        .t5_wb_stb_o ( wb_us_stb_i ),

        .t5_wb_cab_o ( wb_us_cab_i ),

        .t5_wb_adr_o ( wb_us_adr_i ),

        .t5_wb_sel_o ( wb_us_sel_i ),

        .t5_wb_we_o  ( wb_us_we_i  ),

        .t5_wb_dat_o ( wb_us_dat_i ),

        .t5_wb_dat_i ( wb_us_dat_o ),

        .t5_wb_ack_i ( wb_us_ack_o ),

        .t5_wb_err_i ( 1'b0 ),

        // WISHBONE Target 6

        .t6_wb_cyc_o ( ),

        .t6_wb_stb_o ( ),

        .t6_wb_cab_o ( ),

        .t6_wb_adr_o ( ),

        .t6_wb_sel_o ( ),

        .t6_wb_we_o  ( ),

        .t6_wb_dat_o ( ),

        .t6_wb_dat_i ( 32'h0000_0000 ),

        .t6_wb_ack_i ( 1'b0 ),

        .t6_wb_err_i ( 1'b1 ),

        // WISHBONE Target 7

        .t7_wb_cyc_o ( ),

        .t7_wb_stb_o ( ),

        .t7_wb_cab_o ( ),

        .t7_wb_adr_o ( ),

        .t7_wb_sel_o ( ),

        .t7_wb_we_o  ( ),

        .t7_wb_dat_o ( ),

        .t7_wb_dat_i ( 32'h0000_0000 ),

        .t7_wb_ack_i ( 1'b0 ),

        .t7_wb_err_i ( 1'b1 ),

        // WISHBONE Target 8

        .t8_wb_cyc_o ( ),

        .t8_wb_stb_o ( ),

        .t8_wb_cab_o ( ),

        .t8_wb_adr_o ( ),

        .t8_wb_sel_o ( ),

        .t8_wb_we_o  ( ),

        .t8_wb_dat_o ( ),

        .t8_wb_dat_i ( 32'h0000_0000 ),

        .t8_wb_ack_i ( 1'b0 ),

        .t8_wb_err_i ( 1'b1 )

);

//OpenRISC 1200 Instantiation

or1200_top or1200_top(

        // System

        .clk_i      ( clk ),

        .rst_i      ( reset ),

        .pic_ints_i ( pic_ints ),

        .clmode_i   ( clmode ),

        // Instruction WISHBONE INTERFACE

        .iwb_clk_i  ( clk ),

        .iwb_rst_i  ( reset ),

        .iwb_ack_i  ( iwb_ack ),

        .iwb_err_i  ( 1'b0 ),

        .iwb_rty_i  ( 1'b0 ),

        .iwb_dat_i  ( iwb_dat_i ),

        .iwb_cyc_o  ( iwb_cyc ),

        .iwb_adr_o  ( iwb_adr ),

        .iwb_stb_o  ( iwb_stb ),

        .iwb_we_o   ( iwb_we ),

        .iwb_sel_o  ( iwb_sel ),

        .iwb_dat_o  ( iwb_dat_o ),

`ifdef OR1200_WB_CAB

        .iwb_cab_o  ( iwb_cab ),

`endif

`ifdef OR1200_WB_B3

        .iwb_cti_o  ( iwb_cti ),

        .iwb_bte_o  ( iwb_bte ),

`endif

   //Data WISHBONE INTERFACE

        .dwb_clk_i  ( clk ),

        .dwb_rst_i  ( reset ),

        .dwb_ack_i  ( dwb_ack ),

        .dwb_err_i  ( 1'b0 ),

        .dwb_rty_i  ( 1'b0 ),

        .dwb_dat_i  ( dwb_dat_i ),

        .dwb_cyc_o  ( dwb_cyc ),

        .dwb_adr_o  ( dwb_adr ),

        .dwb_stb_o  ( dwb_stb ),

        .dwb_we_o   ( dwb_we ),

        .dwb_sel_o  ( dwb_sel ),

        .dwb_dat_o  ( dwb_dat_o ),

`ifdef OR1200_WB_CAB

        .dwb_cab_o  ( dwb_cab ),

`endif

`ifdef OR1200_WB_B3

        .dwb_cti_o  ( dwb_cti ),

        .dwb_bte_o  ( dwb_bte ),

`endif

        // Debug

        .dbg_stall_i ( dbg_stall ),

        .dbg_dat_i   ( dbg_dat_dbg ),

        .dbg_adr_i   ( dbg_adr ),

        .dbg_ewt_i   ( 1'b0 ),

        .dbg_lss_o   (  ),

        .dbg_is_o    (  ),

        .dbg_wp_o    (  ),

        .dbg_bp_o    ( dbg_bp ),

        .dbg_dat_o   ( dbg_dat_risc ),

        .dbg_ack_o   ( dbg_ack ),

        .dbg_stb_i   ( dbg_stb ),

        .dbg_we_i    ( dbg_we ),

        // Power Management

        .pm_cpustall_i(pm_cpustall),

        .pm_clksd_o( ),

        .pm_dc_gate_o( ),

        .pm_ic_gate_o( ),

        .pm_dmmu_gate_o( ),

        .pm_immu_gate_o( ),

        .pm_tt_gate_o( ),

        .pm_cpu_gate_o( ),

        .pm_wakeup_o( ),

        .pm_lvolt_o( )

);

//

// TAP<->dbg_interface

//      

wire debug_select;

wire debug_tdi;

wire debug_tdo;

wire shift_dr;

wire pause_dr;

wire update_dr;

//

// Instantiation of the development i/f

//

dbg_top dbg_top  (

        // JTAG pins

      .tck_i    ( jtag_tck ),

      .tdi_i    ( debug_tdi ),

      .tdo_o    ( debug_tdo ),

      .rst_i    ( reset ),

        // Boundary Scan signals

      .shift_dr_i  ( shift_dr ),

      .pause_dr_i  ( pause_dr ),

      .update_dr_i ( update_dr ),

      .debug_select_i( debug_select) ,

        // WISHBONE common

      .wb_clk_i   ( clk ),

      // WISHBONE master interface

      .wb_adr_o  ( wb_dm_adr_o ),

      .wb_dat_i  ( wb_dm_dat_i ),

      .wb_dat_o  ( wb_dm_dat_o ),

      .wb_sel_o  ( wb_dm_sel_o ),

      .wb_we_o   ( wb_dm_we_o  ),

      .wb_stb_o  ( wb_dm_stb_o ),

      .wb_cyc_o  ( wb_dm_cyc_o ),

      .wb_cab_o  ( wb_dm_cab_o ),

      .wb_ack_i  ( wb_dm_ack_i ),

      .wb_err_i  ( wb_dm_err_i ),

      .wb_cti_o  ( ),

      .wb_bte_o  ( ),

      // RISC signals

      .cpu0_clk_i  ( clk ),

      .cpu0_addr_o ( dbg_adr ),

      .cpu0_data_i ( dbg_dat_risc ),

      .cpu0_data_o ( dbg_dat_dbg ),

      .cpu0_bp_i   ( dbg_bp ),

      .cpu0_stall_o( dbg_stall ),

      .cpu0_stb_o  ( dbg_stb ),

      .cpu0_we_o   ( dbg_we ),

      .cpu0_ack_i  ( dbg_ack),

      .cpu0_rst_o  ( )

);

//

// JTAG TAP controller instantiation

//

tap_top tap_top(

   .tms_pad_i   ( jtag_tms ),

   .tck_pad_i   ( jtag_tck ),