| 1 |
1327 |
jcastillo |
//////////////////////////////////////////////////////////////////////
|
| 2 |
|
|
//// ////
|
| 3 |
|
|
//// uart_receiver.v ////
|
| 4 |
|
|
//// ////
|
| 5 |
|
|
//// ////
|
| 6 |
|
|
//// This file is part of the "UART 16550 compatible" project ////
|
| 7 |
|
|
//// http://www.opencores.org/cores/uart16550/ ////
|
| 8 |
|
|
//// ////
|
| 9 |
|
|
//// Documentation related to this project: ////
|
| 10 |
|
|
//// - http://www.opencores.org/cores/uart16550/ ////
|
| 11 |
|
|
//// ////
|
| 12 |
|
|
//// Projects compatibility: ////
|
| 13 |
|
|
//// - WISHBONE ////
|
| 14 |
|
|
//// RS232 Protocol ////
|
| 15 |
|
|
//// 16550D uart (mostly supported) ////
|
| 16 |
|
|
//// ////
|
| 17 |
|
|
//// Overview (main Features): ////
|
| 18 |
|
|
//// UART core receiver logic ////
|
| 19 |
|
|
//// ////
|
| 20 |
|
|
//// Known problems (limits): ////
|
| 21 |
|
|
//// None known ////
|
| 22 |
|
|
//// ////
|
| 23 |
|
|
//// To Do: ////
|
| 24 |
|
|
//// Thourough testing. ////
|
| 25 |
|
|
//// ////
|
| 26 |
|
|
//// Author(s): ////
|
| 27 |
|
|
//// - gorban@opencores.org ////
|
| 28 |
|
|
//// - Jacob Gorban ////
|
| 29 |
|
|
//// - Igor Mohor (igorm@opencores.org) ////
|
| 30 |
|
|
//// ////
|
| 31 |
|
|
//// Created: 2001/05/12 ////
|
| 32 |
|
|
//// Last Updated: 2001/05/17 ////
|
| 33 |
|
|
//// (See log for the revision history) ////
|
| 34 |
|
|
//// ////
|
| 35 |
|
|
//// ////
|
| 36 |
|
|
//////////////////////////////////////////////////////////////////////
|
| 37 |
|
|
//// ////
|
| 38 |
|
|
//// Copyright (C) 2000, 2001 Authors ////
|
| 39 |
|
|
//// ////
|
| 40 |
|
|
//// This source file may be used and distributed without ////
|
| 41 |
|
|
//// restriction provided that this copyright statement is not ////
|
| 42 |
|
|
//// removed from the file and that any derivative work contains ////
|
| 43 |
|
|
//// the original copyright notice and the associated disclaimer. ////
|
| 44 |
|
|
//// ////
|
| 45 |
|
|
//// This source file is free software; you can redistribute it ////
|
| 46 |
|
|
//// and/or modify it under the terms of the GNU Lesser General ////
|
| 47 |
|
|
//// Public License as published by the Free Software Foundation; ////
|
| 48 |
|
|
//// either version 2.1 of the License, or (at your option) any ////
|
| 49 |
|
|
//// later version. ////
|
| 50 |
|
|
//// ////
|
| 51 |
|
|
//// This source is distributed in the hope that it will be ////
|
| 52 |
|
|
//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
|
| 53 |
|
|
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
|
| 54 |
|
|
//// PURPOSE. See the GNU Lesser General Public License for more ////
|
| 55 |
|
|
//// details. ////
|
| 56 |
|
|
//// ////
|
| 57 |
|
|
//// You should have received a copy of the GNU Lesser General ////
|
| 58 |
|
|
//// Public License along with this source; if not, download it ////
|
| 59 |
|
|
//// from http://www.opencores.org/lgpl.shtml ////
|
| 60 |
|
|
//// ////
|
| 61 |
|
|
//////////////////////////////////////////////////////////////////////
|
| 62 |
|
|
//
|
| 63 |
|
|
// CVS Revision History
|
| 64 |
|
|
//
|
| 65 |
|
|
// $Log: not supported by cvs2svn $
|
| 66 |
|
|
// Revision 1.31 2004/06/18 14:46:15 tadejm
|
| 67 |
|
|
// Brandl Tobias repaired a bug regarding frame error in receiver when brake is received.
|
| 68 |
|
|
//
|
| 69 |
|
|
// Revision 1.29 2002/07/29 21:16:18 gorban
|
| 70 |
|
|
// The uart_defines.v file is included again in sources.
|
| 71 |
|
|
//
|
| 72 |
|
|
// Revision 1.28 2002/07/22 23:02:23 gorban
|
| 73 |
|
|
// Bug Fixes:
|
| 74 |
|
|
// * Possible loss of sync and bad reception of stop bit on slow baud rates fixed.
|
| 75 |
|
|
// Problem reported by Kenny.Tung.
|
| 76 |
|
|
// * Bad (or lack of ) loopback handling fixed. Reported by Cherry Withers.
|
| 77 |
|
|
//
|
| 78 |
|
|
// Improvements:
|
| 79 |
|
|
// * Made FIFO's as general inferrable memory where possible.
|
| 80 |
|
|
// So on FPGA they should be inferred as RAM (Distributed RAM on Xilinx).
|
| 81 |
|
|
// This saves about 1/3 of the Slice count and reduces P&R and synthesis times.
|
| 82 |
|
|
//
|
| 83 |
|
|
// * Added optional baudrate output (baud_o).
|
| 84 |
|
|
// This is identical to BAUDOUT* signal on 16550 chip.
|
| 85 |
|
|
// It outputs 16xbit_clock_rate - the divided clock.
|
| 86 |
|
|
// It's disabled by default. Define UART_HAS_BAUDRATE_OUTPUT to use.
|
| 87 |
|
|
//
|
| 88 |
|
|
// Revision 1.27 2001/12/30 20:39:13 mohor
|
| 89 |
|
|
// More than one character was stored in case of break. End of the break
|
| 90 |
|
|
// was not detected correctly.
|
| 91 |
|
|
//
|
| 92 |
|
|
// Revision 1.26 2001/12/20 13:28:27 mohor
|
| 93 |
|
|
// Missing declaration of rf_push_q fixed.
|
| 94 |
|
|
//
|
| 95 |
|
|
// Revision 1.25 2001/12/20 13:25:46 mohor
|
| 96 |
|
|
// rx push changed to be only one cycle wide.
|
| 97 |
|
|
//
|
| 98 |
|
|
// Revision 1.24 2001/12/19 08:03:34 mohor
|
| 99 |
|
|
// Warnings cleared.
|
| 100 |
|
|
//
|
| 101 |
|
|
// Revision 1.23 2001/12/19 07:33:54 mohor
|
| 102 |
|
|
// Synplicity was having troubles with the comment.
|
| 103 |
|
|
//
|
| 104 |
|
|
// Revision 1.22 2001/12/17 14:46:48 mohor
|
| 105 |
|
|
// overrun signal was moved to separate block because many sequential lsr
|
| 106 |
|
|
// reads were preventing data from being written to rx fifo.
|
| 107 |
|
|
// underrun signal was not used and was removed from the project.
|
| 108 |
|
|
//
|
| 109 |
|
|
// Revision 1.21 2001/12/13 10:31:16 mohor
|
| 110 |
|
|
// timeout irq must be set regardless of the rda irq (rda irq does not reset the
|
| 111 |
|
|
// timeout counter).
|
| 112 |
|
|
//
|
| 113 |
|
|
// Revision 1.20 2001/12/10 19:52:05 gorban
|
| 114 |
|
|
// Igor fixed break condition bugs
|
| 115 |
|
|
//
|
| 116 |
|
|
// Revision 1.19 2001/12/06 14:51:04 gorban
|
| 117 |
|
|
// Bug in LSR[0] is fixed.
|
| 118 |
|
|
// All WISHBONE signals are now sampled, so another wait-state is introduced on all transfers.
|
| 119 |
|
|
//
|
| 120 |
|
|
// Revision 1.18 2001/12/03 21:44:29 gorban
|
| 121 |
|
|
// Updated specification documentation.
|
| 122 |
|
|
// Added full 32-bit data bus interface, now as default.
|
| 123 |
|
|
// Address is 5-bit wide in 32-bit data bus mode.
|
| 124 |
|
|
// Added wb_sel_i input to the core. It's used in the 32-bit mode.
|
| 125 |
|
|
// Added debug interface with two 32-bit read-only registers in 32-bit mode.
|
| 126 |
|
|
// Bits 5 and 6 of LSR are now only cleared on TX FIFO write.
|
| 127 |
|
|
// My small test bench is modified to work with 32-bit mode.
|
| 128 |
|
|
//
|
| 129 |
|
|
// Revision 1.17 2001/11/28 19:36:39 gorban
|
| 130 |
|
|
// Fixed: timeout and break didn't pay attention to current data format when counting time
|
| 131 |
|
|
//
|
| 132 |
|
|
// Revision 1.16 2001/11/27 22:17:09 gorban
|
| 133 |
|
|
// Fixed bug that prevented synthesis in uart_receiver.v
|
| 134 |
|
|
//
|
| 135 |
|
|
// Revision 1.15 2001/11/26 21:38:54 gorban
|
| 136 |
|
|
// Lots of fixes:
|
| 137 |
|
|
// Break condition wasn't handled correctly at all.
|
| 138 |
|
|
// LSR bits could lose their values.
|
| 139 |
|
|
// LSR value after reset was wrong.
|
| 140 |
|
|
// Timing of THRE interrupt signal corrected.
|
| 141 |
|
|
// LSR bit 0 timing corrected.
|
| 142 |
|
|
//
|
| 143 |
|
|
// Revision 1.14 2001/11/10 12:43:21 gorban
|
| 144 |
|
|
// Logic Synthesis bugs fixed. Some other minor changes
|
| 145 |
|
|
//
|
| 146 |
|
|
// Revision 1.13 2001/11/08 14:54:23 mohor
|
| 147 |
|
|
// Comments in Slovene language deleted, few small fixes for better work of
|
| 148 |
|
|
// old tools. IRQs need to be fix.
|
| 149 |
|
|
//
|
| 150 |
|
|
// Revision 1.12 2001/11/07 17:51:52 gorban
|
| 151 |
|
|
// Heavily rewritten interrupt and LSR subsystems.
|
| 152 |
|
|
// Many bugs hopefully squashed.
|
| 153 |
|
|
//
|
| 154 |
|
|
// Revision 1.11 2001/10/31 15:19:22 gorban
|
| 155 |
|
|
// Fixes to break and timeout conditions
|
| 156 |
|
|
//
|
| 157 |
|
|
// Revision 1.10 2001/10/20 09:58:40 gorban
|
| 158 |
|
|
// Small synopsis fixes
|
| 159 |
|
|
//
|
| 160 |
|
|
// Revision 1.9 2001/08/24 21:01:12 mohor
|
| 161 |
|
|
// Things connected to parity changed.
|
| 162 |
|
|
// Clock devider changed.
|
| 163 |
|
|
//
|
| 164 |
|
|
// Revision 1.8 2001/08/23 16:05:05 mohor
|
| 165 |
|
|
// Stop bit bug fixed.
|
| 166 |
|
|
// Parity bug fixed.
|
| 167 |
|
|
// WISHBONE read cycle bug fixed,
|
| 168 |
|
|
// OE indicator (Overrun Error) bug fixed.
|
| 169 |
|
|
// PE indicator (Parity Error) bug fixed.
|
| 170 |
|
|
// Register read bug fixed.
|
| 171 |
|
|
//
|
| 172 |
|
|
// Revision 1.6 2001/06/23 11:21:48 gorban
|
| 173 |
|
|
// DL made 16-bit long. Fixed transmission/reception bugs.
|
| 174 |
|
|
//
|
| 175 |
|
|
// Revision 1.5 2001/06/02 14:28:14 gorban
|
| 176 |
|
|
// Fixed receiver and transmitter. Major bug fixed.
|
| 177 |
|
|
//
|
| 178 |
|
|
// Revision 1.4 2001/05/31 20:08:01 gorban
|
| 179 |
|
|
// FIFO changes and other corrections.
|
| 180 |
|
|
//
|
| 181 |
|
|
// Revision 1.3 2001/05/27 17:37:49 gorban
|
| 182 |
|
|
// Fixed many bugs. Updated spec. Changed FIFO files structure. See CHANGES.txt file.
|
| 183 |
|
|
//
|
| 184 |
|
|
// Revision 1.2 2001/05/21 19:12:02 gorban
|
| 185 |
|
|
// Corrected some Linter messages.
|
| 186 |
|
|
//
|
| 187 |
|
|
// Revision 1.1 2001/05/17 18:34:18 gorban
|
| 188 |
|
|
// First 'stable' release. Should be sythesizable now. Also added new header.
|
| 189 |
|
|
//
|
| 190 |
|
|
// Revision 1.0 2001-05-17 21:27:11+02 jacob
|
| 191 |
|
|
// Initial revision
|
| 192 |
|
|
//
|
| 193 |
|
|
//
|
| 194 |
|
|
|
| 195 |
|
|
// synopsys translate_off
|
| 196 |
|
|
`include "timescale.v"
|
| 197 |
|
|
// synopsys translate_on
|
| 198 |
|
|
|
| 199 |
|
|
`include "uart_defines.v"
|
| 200 |
|
|
|
| 201 |
|
|
module uart_receiver (clk, wb_rst_i, lcr, rf_pop, srx_pad_i, enable,
|
| 202 |
|
|
counter_t, rf_count, rf_data_out, rf_error_bit, rf_overrun, rx_reset, lsr_mask, rstate, rf_push_pulse);
|
| 203 |
|
|
|
| 204 |
|
|
input clk;
|
| 205 |
|
|
input wb_rst_i;
|
| 206 |
|
|
input [7:0] lcr;
|
| 207 |
|
|
input rf_pop;
|
| 208 |
|
|
input srx_pad_i;
|
| 209 |
|
|
input enable;
|
| 210 |
|
|
input rx_reset;
|
| 211 |
|
|
input lsr_mask;
|
| 212 |
|
|
|
| 213 |
|
|
output [9:0] counter_t;
|
| 214 |
|
|
output [`UART_FIFO_COUNTER_W-1:0] rf_count;
|
| 215 |
|
|
output [`UART_FIFO_REC_WIDTH-1:0] rf_data_out;
|
| 216 |
|
|
output rf_overrun;
|
| 217 |
|
|
output rf_error_bit;
|
| 218 |
|
|
output [3:0] rstate;
|
| 219 |
|
|
output rf_push_pulse;
|
| 220 |
|
|
|
| 221 |
|
|
reg [3:0] rstate;
|
| 222 |
|
|
reg [3:0] rcounter16;
|
| 223 |
|
|
reg [2:0] rbit_counter;
|
| 224 |
|
|
reg [7:0] rshift; // receiver shift register
|
| 225 |
|
|
reg rparity; // received parity
|
| 226 |
|
|
reg rparity_error;
|
| 227 |
|
|
reg rframing_error; // framing error flag
|
| 228 |
|
|
reg rbit_in;
|
| 229 |
|
|
reg rparity_xor;
|
| 230 |
|
|
reg [7:0] counter_b; // counts the 0 (low) signals
|
| 231 |
|
|
reg rf_push_q;
|
| 232 |
|
|
|
| 233 |
|
|
// RX FIFO signals
|
| 234 |
|
|
reg [`UART_FIFO_REC_WIDTH-1:0] rf_data_in;
|
| 235 |
|
|
wire [`UART_FIFO_REC_WIDTH-1:0] rf_data_out;
|
| 236 |
|
|
wire rf_push_pulse;
|
| 237 |
|
|
reg rf_push;
|
| 238 |
|
|
wire rf_pop;
|
| 239 |
|
|
wire rf_overrun;
|
| 240 |
|
|
wire [`UART_FIFO_COUNTER_W-1:0] rf_count;
|
| 241 |
|
|
wire rf_error_bit; // an error (parity or framing) is inside the fifo
|
| 242 |
|
|
wire break_error = (counter_b == 0);
|
| 243 |
|
|
|
| 244 |
|
|
// RX FIFO instance
|
| 245 |
|
|
uart_rfifo #(`UART_FIFO_REC_WIDTH) fifo_rx(
|
| 246 |
|
|
.clk( clk ),
|
| 247 |
|
|
.wb_rst_i( wb_rst_i ),
|
| 248 |
|
|
.data_in( rf_data_in ),
|
| 249 |
|
|
.data_out( rf_data_out ),
|
| 250 |
|
|
.push( rf_push_pulse ),
|
| 251 |
|
|
.pop( rf_pop ),
|
| 252 |
|
|
.overrun( rf_overrun ),
|
| 253 |
|
|
.count( rf_count ),
|
| 254 |
|
|
.error_bit( rf_error_bit ),
|
| 255 |
|
|
.fifo_reset( rx_reset ),
|
| 256 |
|
|
.reset_status(lsr_mask)
|
| 257 |
|
|
);
|
| 258 |
|
|
|
| 259 |
|
|
wire rcounter16_eq_7 = (rcounter16 == 4'd7);
|
| 260 |
|
|
wire rcounter16_eq_0 = (rcounter16 == 4'd0);
|
| 261 |
|
|
wire rcounter16_eq_1 = (rcounter16 == 4'd1);
|
| 262 |
|
|
|
| 263 |
|
|
wire [3:0] rcounter16_minus_1 = rcounter16 - 1'b1;
|
| 264 |
|
|
|
| 265 |
|
|
parameter sr_idle = 4'd0;
|
| 266 |
|
|
parameter sr_rec_start = 4'd1;
|
| 267 |
|
|
parameter sr_rec_bit = 4'd2;
|
| 268 |
|
|
parameter sr_rec_parity = 4'd3;
|
| 269 |
|
|
parameter sr_rec_stop = 4'd4;
|
| 270 |
|
|
parameter sr_check_parity = 4'd5;
|
| 271 |
|
|
parameter sr_rec_prepare = 4'd6;
|
| 272 |
|
|
parameter sr_end_bit = 4'd7;
|
| 273 |
|
|
parameter sr_ca_lc_parity = 4'd8;
|
| 274 |
|
|
parameter sr_wait1 = 4'd9;
|
| 275 |
|
|
parameter sr_push = 4'd10;
|
| 276 |
|
|
|
| 277 |
|
|
|
| 278 |
|
|
always @(posedge clk or posedge wb_rst_i)
|
| 279 |
|
|
begin
|
| 280 |
|
|
if (wb_rst_i)
|
| 281 |
|
|
begin
|
| 282 |
|
|
rstate <= #1 sr_idle;
|
| 283 |
|
|
rbit_in <= #1 1'b0;
|
| 284 |
|
|
rcounter16 <= #1 0;
|
| 285 |
|
|
rbit_counter <= #1 0;
|
| 286 |
|
|
rparity_xor <= #1 1'b0;
|
| 287 |
|
|
rframing_error <= #1 1'b0;
|
| 288 |
|
|
rparity_error <= #1 1'b0;
|
| 289 |
|
|
rparity <= #1 1'b0;
|
| 290 |
|
|
rshift <= #1 0;
|
| 291 |
|
|
rf_push <= #1 1'b0;
|
| 292 |
|
|
rf_data_in <= #1 0;
|
| 293 |
|
|
end
|
| 294 |
|
|
else
|
| 295 |
|
|
if (enable)
|
| 296 |
|
|
begin
|
| 297 |
|
|
case (rstate)
|
| 298 |
|
|
sr_idle : begin
|
| 299 |
|
|
rf_push <= #1 1'b0;
|
| 300 |
|
|
rf_data_in <= #1 0;
|
| 301 |
|
|
rcounter16 <= #1 4'b1110;
|
| 302 |
|
|
if (srx_pad_i==1'b0 & ~break_error) // detected a pulse (start bit?)
|
| 303 |
|
|
begin
|
| 304 |
|
|
rstate <= #1 sr_rec_start;
|
| 305 |
|
|
end
|
| 306 |
|
|
end
|
| 307 |
|
|
sr_rec_start : begin
|
| 308 |
|
|
rf_push <= #1 1'b0;
|
| 309 |
|
|
if (rcounter16_eq_7) // check the pulse
|
| 310 |
|
|
if (srx_pad_i==1'b1) // no start bit
|
| 311 |
|
|
rstate <= #1 sr_idle;
|
| 312 |
|
|
else // start bit detected
|
| 313 |
|
|
rstate <= #1 sr_rec_prepare;
|
| 314 |
|
|
rcounter16 <= #1 rcounter16_minus_1;
|
| 315 |
|
|
end
|
| 316 |
|
|
sr_rec_prepare:begin
|
| 317 |
|
|
case (lcr[/*`UART_LC_BITS*/1:0]) // number of bits in a word
|
| 318 |
|
|
2'b00 : rbit_counter <= #1 3'b100;
|
| 319 |
|
|
2'b01 : rbit_counter <= #1 3'b101;
|
| 320 |
|
|
2'b10 : rbit_counter <= #1 3'b110;
|
| 321 |
|
|
2'b11 : rbit_counter <= #1 3'b111;
|
| 322 |
|
|
endcase
|
| 323 |
|
|
if (rcounter16_eq_0)
|
| 324 |
|
|
begin
|
| 325 |
|
|
rstate <= #1 sr_rec_bit;
|
| 326 |
|
|
rcounter16 <= #1 4'b1110;
|
| 327 |
|
|
rshift <= #1 0;
|
| 328 |
|
|
end
|
| 329 |
|
|
else
|
| 330 |
|
|
rstate <= #1 sr_rec_prepare;
|
| 331 |
|
|
rcounter16 <= #1 rcounter16_minus_1;
|
| 332 |
|
|
end
|
| 333 |
|
|
sr_rec_bit : begin
|
| 334 |
|
|
if (rcounter16_eq_0)
|
| 335 |
|
|
rstate <= #1 sr_end_bit;
|
| 336 |
|
|
if (rcounter16_eq_7) // read the bit
|
| 337 |
|
|
case (lcr[/*`UART_LC_BITS*/1:0]) // number of bits in a word
|
| 338 |
|
|
2'b00 : rshift[4:0] <= #1 {srx_pad_i, rshift[4:1]};
|
| 339 |
|
|
2'b01 : rshift[5:0] <= #1 {srx_pad_i, rshift[5:1]};
|
| 340 |
|
|
2'b10 : rshift[6:0] <= #1 {srx_pad_i, rshift[6:1]};
|
| 341 |
|
|
2'b11 : rshift[7:0] <= #1 {srx_pad_i, rshift[7:1]};
|
| 342 |
|
|
endcase
|
| 343 |
|
|
rcounter16 <= #1 rcounter16_minus_1;
|
| 344 |
|
|
end
|
| 345 |
|
|
sr_end_bit : begin
|
| 346 |
|
|
if (rbit_counter==3'b0) // no more bits in word
|
| 347 |
|
|
if (lcr[`UART_LC_PE]) // choose state based on parity
|
| 348 |
|
|
rstate <= #1 sr_rec_parity;
|
| 349 |
|
|
else
|
| 350 |
|
|
begin
|
| 351 |
|
|
rstate <= #1 sr_rec_stop;
|
| 352 |
|
|
rparity_error <= #1 1'b0; // no parity - no error :)
|
| 353 |
|
|
end
|
| 354 |
|
|
else // else we have more bits to read
|
| 355 |
|
|
begin
|
| 356 |
|
|
rstate <= #1 sr_rec_bit;
|
| 357 |
|
|
rbit_counter <= #1 rbit_counter - 1'b1;
|
| 358 |
|
|
end
|
| 359 |
|
|
rcounter16 <= #1 4'b1110;
|
| 360 |
|
|
end
|
| 361 |
|
|
sr_rec_parity: begin
|
| 362 |
|
|
if (rcounter16_eq_7) // read the parity
|
| 363 |
|
|
begin
|
| 364 |
|
|
rparity <= #1 srx_pad_i;
|
| 365 |
|
|
rstate <= #1 sr_ca_lc_parity;
|
| 366 |
|
|
end
|
| 367 |
|
|
rcounter16 <= #1 rcounter16_minus_1;
|
| 368 |
|
|
end
|
| 369 |
|
|
sr_ca_lc_parity : begin // rcounter equals 6
|
| 370 |
|
|
rcounter16 <= #1 rcounter16_minus_1;
|
| 371 |
|
|
rparity_xor <= #1 ^{rshift,rparity}; // calculate parity on all incoming data
|
| 372 |
|
|
rstate <= #1 sr_check_parity;
|
| 373 |
|
|
end
|
| 374 |
|
|
sr_check_parity: begin // rcounter equals 5
|
| 375 |
|
|
case ({lcr[`UART_LC_EP],lcr[`UART_LC_SP]})
|
| 376 |
|
|
2'b00: rparity_error <= #1 rparity_xor == 0; // no error if parity 1
|
| 377 |
|
|
2'b01: rparity_error <= #1 ~rparity; // parity should sticked to 1
|
| 378 |
|
|
2'b10: rparity_error <= #1 rparity_xor == 1; // error if parity is odd
|
| 379 |
|
|
2'b11: rparity_error <= #1 rparity; // parity should be sticked to 0
|
| 380 |
|
|
endcase
|
| 381 |
|
|
rcounter16 <= #1 rcounter16_minus_1;
|
| 382 |
|
|
rstate <= #1 sr_wait1;
|
| 383 |
|
|
end
|
| 384 |
|
|
sr_wait1 : if (rcounter16_eq_0)
|
| 385 |
|
|
begin
|
| 386 |
|
|
rstate <= #1 sr_rec_stop;
|
| 387 |
|
|
rcounter16 <= #1 4'b1110;
|
| 388 |
|
|
end
|
| 389 |
|
|
else
|
| 390 |
|
|
rcounter16 <= #1 rcounter16_minus_1;
|
| 391 |
|
|
sr_rec_stop : begin
|
| 392 |
|
|
if (rcounter16_eq_7) // read the parity
|
| 393 |
|
|
begin
|
| 394 |
|
|
rframing_error <= #1 !srx_pad_i; // no framing error if input is 1 (stop bit)
|
| 395 |
|
|
rstate <= #1 sr_push;
|
| 396 |
|
|
end
|
| 397 |
|
|
rcounter16 <= #1 rcounter16_minus_1;
|
| 398 |
|
|
end
|
| 399 |
|
|
sr_push : begin
|
| 400 |
|
|
///////////////////////////////////////
|
| 401 |
|
|
// $display($time, ": received: %b", rf_data_in);
|
| 402 |
|
|
if(srx_pad_i | break_error)
|
| 403 |
|
|
begin
|
| 404 |
|
|
if(break_error)
|
| 405 |
|
|
rf_data_in <= #1 {8'b0, 3'b100}; // break input (empty character) to receiver FIFO
|
| 406 |
|
|
else
|
| 407 |
|
|
rf_data_in <= #1 {rshift, 1'b0, rparity_error, rframing_error};
|
| 408 |
|
|
rf_push <= #1 1'b1;
|
| 409 |
|
|
rstate <= #1 sr_idle;
|
| 410 |
|
|
end
|
| 411 |
|
|
else if(~rframing_error) // There's always a framing before break_error -> wait for break or srx_pad_i
|
| 412 |
|
|
begin
|
| 413 |
|
|
rf_data_in <= #1 {rshift, 1'b0, rparity_error, rframing_error};
|
| 414 |
|
|
rf_push <= #1 1'b1;
|
| 415 |
|
|
rcounter16 <= #1 4'b1110;
|
| 416 |
|
|
rstate <= #1 sr_rec_start;
|
| 417 |
|
|
end
|
| 418 |
|
|
|
| 419 |
|
|
end
|
| 420 |
|
|
default : rstate <= #1 sr_idle;
|
| 421 |
|
|
endcase
|
| 422 |
|
|
end // if (enable)
|
| 423 |
|
|
end // always of receiver
|
| 424 |
|
|
|
| 425 |
|
|
always @ (posedge clk or posedge wb_rst_i)
|
| 426 |
|
|
begin
|
| 427 |
|
|
if(wb_rst_i)
|
| 428 |
|
|
rf_push_q <= 0;
|
| 429 |
|
|
else
|
| 430 |
|
|
rf_push_q <= #1 rf_push;
|
| 431 |
|
|
end
|
| 432 |
|
|
|
| 433 |
|
|
assign rf_push_pulse = rf_push & ~rf_push_q;
|
| 434 |
|
|
|
| 435 |
|
|
|
| 436 |
|
|
//
|
| 437 |
|
|
// Break condition detection.
|
| 438 |
|
|
// Works in conjuction with the receiver state machine
|
| 439 |
|
|
|
| 440 |
|
|
reg [9:0] toc_value; // value to be set to timeout counter
|
| 441 |
|
|
|
| 442 |
|
|
always @(lcr)
|
| 443 |
|
|
case (lcr[3:0])
|
| 444 |
|
|
4'b0000 : toc_value = 447; // 7 bits
|
| 445 |
|
|
4'b0100 : toc_value = 479; // 7.5 bits
|
| 446 |
|
|
4'b0001, 4'b1000 : toc_value = 511; // 8 bits
|
| 447 |
|
|
4'b1100 : toc_value = 543; // 8.5 bits
|
| 448 |
|
|
4'b0010, 4'b0101, 4'b1001 : toc_value = 575; // 9 bits
|
| 449 |
|
|
4'b0011, 4'b0110, 4'b1010, 4'b1101 : toc_value = 639; // 10 bits
|
| 450 |
|
|
4'b0111, 4'b1011, 4'b1110 : toc_value = 703; // 11 bits
|
| 451 |
|
|
4'b1111 : toc_value = 767; // 12 bits
|
| 452 |
|
|
endcase // case(lcr[3:0])
|
| 453 |
|
|
|
| 454 |
|
|
wire [7:0] brc_value; // value to be set to break counter
|
| 455 |
|
|
assign brc_value = toc_value[9:2]; // the same as timeout but 1 insead of 4 character times
|
| 456 |
|
|
|
| 457 |
|
|
always @(posedge clk or posedge wb_rst_i)
|
| 458 |
|
|
begin
|
| 459 |
|
|
if (wb_rst_i)
|
| 460 |
|
|
counter_b <= #1 8'd159;
|
| 461 |
|
|
else
|
| 462 |
|
|
if (srx_pad_i)
|
| 463 |
|
|
counter_b <= #1 brc_value; // character time length - 1
|
| 464 |
|
|
else
|
| 465 |
|
|
if(enable & counter_b != 8'b0) // only work on enable times break not reached.
|
| 466 |
|
|
counter_b <= #1 counter_b - 1; // decrement break counter
|
| 467 |
|
|
end // always of break condition detection
|
| 468 |
|
|
|
| 469 |
|
|
///
|
| 470 |
|
|
/// Timeout condition detection
|
| 471 |
|
|
reg [9:0] counter_t; // counts the timeout condition clocks
|
| 472 |
|
|
|
| 473 |
|
|
always @(posedge clk or posedge wb_rst_i)
|
| 474 |
|
|
begin
|
| 475 |
|
|
if (wb_rst_i)
|
| 476 |
|
|
counter_t <= #1 10'd639; // 10 bits for the default 8N1
|
| 477 |
|
|
else
|
| 478 |
|
|
if(rf_push_pulse || rf_pop || rf_count == 0) // counter is reset when RX FIFO is empty, accessed or above trigger level
|
| 479 |
|
|
counter_t <= #1 toc_value;
|
| 480 |
|
|
else
|
| 481 |
|
|
if (enable && counter_t != 10'b0) // we don't want to underflow
|
| 482 |
|
|
counter_t <= #1 counter_t - 1;
|
| 483 |
|
|
end
|
| 484 |
|
|
|
| 485 |
|
|
endmodule
|
