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[/] [or1k_old/] [trunk/] [rc203soc/] [sw/] [uClinux/] [arch/] [armnommu/] [drivers/] [char/] [serialecho.c] - Blame information for rev 1782

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/*
 * linux/arch/arm/drivers/char/serialecho.c
 *
 * Serial echoing for kernel console messages.
 */
#if defined (CONFIG_ARCH_A5K) || defined (CONFIG_ARCH_RPC) || defined(CONFIG_ARCH_EBSA110)
 
#include <asm/io.h>
 
#include <linux/serial_reg.h>
 
extern int serial_echo_init (int base);
extern int serial_echo_print (const char *s);
 
/*
 * this defines the address for the port to which printk echoing is done
 *  when CONFIG_SERIAL_ECHO is defined
 */
#ifndef SERIAL_ECHO_PORT
#define SERIAL_ECHO_PORT        0x3f8   /* internal serial port */
#endif
 
#ifndef SERIAL_ECHO_DIVISOR
#define SERIAL_ECHO_DIVISOR     12      /* 9600 baud */
#endif
 
static int serial_echo_port = 0;
 
#define serial_echo_outb(v,a) outb((v),(a)+serial_echo_port)
#define serial_echo_inb(a)    inb((a)+serial_echo_port)
 
#define BOTH_EMPTY (UART_LSR_TEMT | UART_LSR_THRE)
 
/* wait for the transmitter & holding register to empty */
#define WAIT_FOR_XMITR \
 do { \
        lsr = serial_echo_inb (UART_LSR); \
 } while ((lsr & BOTH_EMPTY) != BOTH_EMPTY)
 
/*
 * These two functions abstract the actual communications with the
 * debug port.  This is so we can change the underlying communications
 * mechanism without modifying the rest of the code.
 */
int serial_echo_print (const char *s)
{
        int lsr, ier;
        int i;
 
        if (!serial_echo_port)
                return 0;
 
        /*
         * First save the IER then disable interrupts
         */
        ier = serial_echo_inb (UART_IER);
        serial_echo_outb (0x00, UART_IER);
 
        /*
         * Now do each character
         */
        for (i = 0; *s; i++, s++) {
                WAIT_FOR_XMITR;
 
                /* send the character out. */
                serial_echo_outb (*s, UART_TX);
 
                /* if a LF, also do CR... */
                if (*s == 10) {
                        WAIT_FOR_XMITR;
                        serial_echo_outb (13, UART_TX);
                }
        }
 
        /*
         * Finally, wait for transmitter & holding register to empty
         *  and restore the IER.
         */
        WAIT_FOR_XMITR;
        serial_echo_outb (ier, UART_IER);
 
        return 0;
}
 
int serial_echo_init (int base)
{
        int comstat, hi, lo;
 
        if (base != 0x3f8 && base != 0x2f8) {
                serial_echo_port = 0;
                return 0;
        } else
                serial_echo_port = base;
 
        /*
         * Read the Divisor Latch
         */
        comstat = serial_echo_inb (UART_LCR);
        serial_echo_outb (comstat | UART_LCR_DLAB, UART_LCR);
        hi = serial_echo_inb (UART_DLM);
        lo = serial_echo_inb (UART_DLL);
        serial_echo_outb (comstat, UART_LCR);
 
        /*
         * now do a hardwired init
         */
        serial_echo_outb (0x03, UART_LCR); /* No parity, 8 bits, 1 stop */
        serial_echo_outb (0x83, UART_LCR); /* Access divisor latch */
        serial_echo_outb (SERIAL_ECHO_DIVISOR >> 8, UART_DLM);
        serial_echo_outb (SERIAL_ECHO_DIVISOR & 0xff, UART_DLL);
        serial_echo_outb (0x03, UART_LCR); /* Done with divisor */
 
        /* Prior to disabling interrupts, read the LSR and RBR
         * registers
         */
        comstat = serial_echo_inb (UART_LSR); /* COM? LSR */
        comstat = serial_echo_inb (UART_RX);  /* COM? RBR */
        serial_echo_outb (0x00, UART_IER);    /* Disable all interrupts */
 
        return 0;
}
 
#endif
 

Line No.	Rev	Author	Line
1	1622	jcastillo	`/*`
2			`* linux/arch/arm/drivers/char/serialecho.c`
3			`*`
4			`* Serial echoing for kernel console messages.`
5			`*/`
6			`#if defined (CONFIG_ARCH_A5K) \|\| defined (CONFIG_ARCH_RPC) \|\| defined(CONFIG_ARCH_EBSA110)`
7
8			`#include <asm/io.h>`
9
10			`#include <linux/serial_reg.h>`
11
12			`extern int serial_echo_init (int base);`
13			`extern int serial_echo_print (const char *s);`
14
15			`/*`
16			`* this defines the address for the port to which printk echoing is done`
17			`* when CONFIG_SERIAL_ECHO is defined`
18			`*/`
19			`#ifndef SERIAL_ECHO_PORT`
20			`#define SERIAL_ECHO_PORT 0x3f8 /* internal serial port */`
21			`#endif`
22
23			`#ifndef SERIAL_ECHO_DIVISOR`
24			`#define SERIAL_ECHO_DIVISOR 12 /* 9600 baud */`
25			`#endif`
26
27			`static int serial_echo_port = 0;`
28
29			`#define serial_echo_outb(v,a) outb((v),(a)+serial_echo_port)`
30			`#define serial_echo_inb(a) inb((a)+serial_echo_port)`
31
32			`#define BOTH_EMPTY (UART_LSR_TEMT \| UART_LSR_THRE)`
33
34			`/* wait for the transmitter & holding register to empty */`
35			`#define WAIT_FOR_XMITR \`
36			`do { \`
37			`lsr = serial_echo_inb (UART_LSR); \`
38			`} while ((lsr & BOTH_EMPTY) != BOTH_EMPTY)`
39
40			`/*`
41			`* These two functions abstract the actual communications with the`
42			`* debug port. This is so we can change the underlying communications`
43			`* mechanism without modifying the rest of the code.`
44			`*/`
45			`int serial_echo_print (const char *s)`
46			`{`
47			`int lsr, ier;`
48			`int i;`
49
50			`if (!serial_echo_port)`
51			`return 0;`
52
53			`/*`
54			`* First save the IER then disable interrupts`
55			`*/`
56			`ier = serial_echo_inb (UART_IER);`
57			`serial_echo_outb (0x00, UART_IER);`
58
59			`/*`
60			`* Now do each character`
61			`*/`
62			`for (i = 0; *s; i++, s++) {`
63			`WAIT_FOR_XMITR;`
64
65			`/* send the character out. */`
66			`serial_echo_outb (*s, UART_TX);`
67
68			`/* if a LF, also do CR... */`
69			`if (*s == 10) {`
70			`WAIT_FOR_XMITR;`
71			`serial_echo_outb (13, UART_TX);`
72			`}`
73			`}`
74
75			`/*`
76			`* Finally, wait for transmitter & holding register to empty`
77			`* and restore the IER.`
78			`*/`
79			`WAIT_FOR_XMITR;`
80			`serial_echo_outb (ier, UART_IER);`
81
82			`return 0;`
83			`}`
84
85			`int serial_echo_init (int base)`
86			`{`
87			`int comstat, hi, lo;`
88
89			`if (base != 0x3f8 && base != 0x2f8) {`
90			`serial_echo_port = 0;`
91			`return 0;`
92			`} else`
93			`serial_echo_port = base;`
94
95			`/*`
96			`* Read the Divisor Latch`
97			`*/`
98			`comstat = serial_echo_inb (UART_LCR);`
99			`serial_echo_outb (comstat \| UART_LCR_DLAB, UART_LCR);`
100			`hi = serial_echo_inb (UART_DLM);`
101			`lo = serial_echo_inb (UART_DLL);`
102			`serial_echo_outb (comstat, UART_LCR);`
103
104			`/*`
105			`* now do a hardwired init`
106			`*/`
107			`serial_echo_outb (0x03, UART_LCR); /* No parity, 8 bits, 1 stop */`
108			`serial_echo_outb (0x83, UART_LCR); /* Access divisor latch */`
109			`serial_echo_outb (SERIAL_ECHO_DIVISOR >> 8, UART_DLM);`
110			`serial_echo_outb (SERIAL_ECHO_DIVISOR & 0xff, UART_DLL);`
111			`serial_echo_outb (0x03, UART_LCR); /* Done with divisor */`
112
113			`/* Prior to disabling interrupts, read the LSR and RBR`
114			`* registers`
115			`*/`
116			`comstat = serial_echo_inb (UART_LSR); /* COM? LSR */`
117			`comstat = serial_echo_inb (UART_RX); /* COM? RBR */`
118			`serial_echo_outb (0x00, UART_IER); /* Disable all interrupts */`
119
120			`return 0;`
121			`}`
122
123			`#endif`
124

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[/] [or1k_old/] [trunk/] [rc203soc/] [sw/] [uClinux/] [arch/] [armnommu/] [drivers/] [char/] [serialecho.c] - Blame information for rev 1782