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[/] [or1k_old/] [trunk/] [rc203soc/] [sw/] [uClinux/] [arch/] [armnommu/] [kernel/] [head-arm-aplio.S] - Blame information for rev 1782

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/*
 * linux/arch/armnommu/kernel/head-arm-trio.S
 *
 * Copyright (C) 1999 Aplio SA
 *
 * Kernel 32 bit startup code for APLIO Trio chip
 */
#include 
#include 
#include 
 
                .text
                .align
 
 
/*----------------------------------
 * DMC & SMC Base Addresses
 * ----------------------------------
 */
 
#define ARM_MODE_SVC    0x13
#define DRAM_BASE     0x00000000
#define DRAM_SIZE     0x400000
#define DRAM_LIMIT    (DRAM_BASE + DRAM_SIZE)
 
 
                .globl  __entry,_entry
                .globl  __stext,_stext
                .globl _start,start
 
start:
_start:
_stext:
_entry:
__stext:
__entry:
 
                bl config_timer1
 
#if 0
/*
   | Initialise the Memory Controller
   | ---------------------------------
   | Copy the Image of the SMC & DMC Memory Controller
*/
        adr     r10, InitTableSMC    /* ; get the address of the SMC chip select image */
        adr     r11, InitTableDMC    /* ; get the address of the DMC chip select image  */
 
/*
;- | Load the address where to jump, Zero out the most significant bits.
*/
#if 0
    ldr     r0, =InitRemap        /* ; get the real jump address ( after remap ) */
        mov     r0, r0, LSL #12
        mov     r0, r0, LSR #12
 
/*
;- | Calculate new PC after the SMC and DMC have been reconfigured.
*/
        ldr r1, [r10]
        ldr r2, =0xFFF00000
        and r1, r2, r1
 
        add r12, r0, r1
#endif
 
/*
;- | Copy The SMC Image into registers 0,1,2
*/
        ldmia   r10!, {r0-r3}
 
 
/*
;- | Copy The DMC Image into registers 3,4,5
*/
        ldmia   r11!, {r4-r7}
 
/*
;- Store the SMC values (r3 contains the base address of the SMC controller)
*/
        stmia   r3!, {r0-r2}
/*
;- Store the DMC values (r7 contains the base address of the DMC controller)
*/
        stmia   r7!, {r4-r6}
 
/*
;- | Jump to ROM at its new address
*/
new_remap_entry:
#if 0
         mov         pc, r12             /* jump and break the pipeline */
#endif
 
 
#endif
/* we get here when RAM is mapped to address 0 */
InitRemap:
 
/*
; Setup the SVC mode and stack pointer on the top of the internal RAM
*/
    mov r0, #(ARM_MODE_SVC | I_BIT | F_BIT ) /* ; No interrupts */
    msr cpsr, r0
    ldr r13, =DRAM_LIMIT
 
/*
;------------------------------------------------------------------------------
;
; Call the Config routines...
;
;------------------------------------------------------------------------------
*/
 
    bl config_PIO
 
        adr     r5, LC0
        ldmia   r5, {r5, r6, r8, sp}                    @ Setup stack
        mov     r4, #0
1:      cmp     r5, r8                                  @ Clear BSS
        strcc   r4, [r5],#4
        bcc     1b
 
 
/*
    bl config_usart0
    bl config_usart1
*/
        ldr r2,=0x41007000
        str r2,[r6]
 
        mov     fp, #0
        b       start_kernel
 
 
 
 
LC0:            .long   edata
                .long   arm_id
                .long   end
                .long   init_user_stack + 4096
 
 
 
 
 
 
InitTableDMC:
                .long   0x0000000D      /* DMC MRO */
                .long   0x1000000D      /* DMC MR1 */
                .long   0x03            /* DMC CR */
                .long   DMC_BASE       /* DMC Base Address */
 
 
InitTableSMC:
                .long   0x40003125      /* SMC CSR0 */
                .long   0                                  /* SMC CSR1 */
                .long   0                                 /* SMC CSR2 */
                .long   SMC_BASE                  /* SMC Base Address */
 
 
 
InitPIOs:
/*
;- |
;- | Driving a Low to any of these lines switches the LEDs on.
;- |
;- | PIOA 9     OUTPUT  LED D28
;- | PIOA 10-20 OUTPUT  LED D17-27
;- | PIOA 21-31 OUTPUT  LED D29-D39
;- | PIOB 10-15 OUTPUT  LED D40-D45
*/
 
config_PIO:
/*
;- Configure PIOA
*/
    ldr r1, PIOA_Enable_Reg
    ldr r2, PIOA_Enable_Value
    str r2, [r1]
 
    ldr r1, PIOA_Disable_Reg
    ldr r2, PIOA_Disable_Value
    str r2, [r1]
 
    ldr r1, PIOA_COD_Reg
    ldr r2, PIOA_COD_Value
    str r2, [r1]
 
    ldr r1, PIOA_OE_Reg
    ldr r2, PIOA_OE_Value
    str r2, [r1]
 
    ldr r1, PIOA_OD_Reg
    ldr r2, PIOA_OD_Value
    str r2, [r1]
 
/*
;- Configure PIOB
*/
    ldr r1, PIOB_Enable_Reg
    ldr r2, PIOB_Enable_Value
    str r2, [r1]
 
    ldr r1, PIOB_Disable_Reg
    ldr r2, PIOB_Disable_Value
    str r2, [r1]
 
    ldr r1, PIOB_COD_Reg
    ldr r2, PIOB_COD_Value
    str r2, [r1]
 
    ldr r1, PIOB_OE_Reg
    ldr r2, PIOB_OE_Value
    str r2, [r1]
 
    ldr r1, PIOB_OD_Reg
    ldr r2, PIOB_OD_Value
    str r2, [r1]
 
    mov pc,lr
 
/*
;------------------------------------------------------------------------------
;
; PIO configuration details
;
;------------------------------------------------------------------------------
*/
PIOA_Enable_Reg:
    .long 0xFF00C000
PIOA_Enable_Value:
    .long 0xFFFFFFFF
PIOA_Disable_Reg:
    .long 0xFF00C004
PIOA_Disable_Value:
    .long 0x00000000
PIOA_OE_Reg:
    .long 0xFF00C010
PIOA_OE_Value:
    .long 0xFFFFFFFF
PIOA_OD_Reg:
    .long 0xFF00C014
PIOA_OD_Value:
    .long 0x00000000
PIOA_COD_Reg:
    .long 0xFF00C034
PIOA_COD_Value:
    .long 0xFFFFFFFF
 
PIOB_Enable_Reg:
    .long 0xFF010000
PIOB_Enable_Value:
    .long 0xFFFFFFFF
PIOB_Disable_Reg:
    .long 0xFF010004
PIOB_Disable_Value:
    .long 0x000003FF
PIOB_OE_Reg:
    .long 0xFF010010
PIOB_OE_Value:
    .long 0x0000FE4B
PIOB_OD_Reg:
    .long 0xFF010014
PIOB_OD_Value:
    .long 0x000001B4
PIOB_COD_Reg:
    .long 0xFF00C034
PIOB_COD_Value:
    .long 0xFFFFFFFF
 
/*
;------------------------------------------------------------------------------
;
; Configure timer 1, This timer channel is connected to DRAM controller
; and is used as the trigger for a DRAM refresh cycle.
; Trashes r1, r2
;
;------------------------------------------------------------------------------
*/
config_timer1:
    ldr r1, TC_CMR_REG
    ldr r2, TC_CMR_Value
    str r2, [r1]
 
    ldr r1, TC_RA_REG
    ldr r2, TC_RA_Value
    str r2, [r1]
 
    ldr r1, TC_RC_REG
    ldr r2, TC_RC_Value
    str r2, [r1]
 
    ldr r1, TC_CCR_REG
    ldr r2, TC_CCR_Value
    str r2, [r1]
 
    ldr r1, TC_BCR_REG
    ldr r2, TC_CCR_Value
    str r2, [r1]
 
    mov pc, lr
 
/*
;------------------------------------------------------------------------------
;
; Timer Control Configuration Data
;
;------------------------------------------------------------------------------
*/
 
TC_CMR_REG:
    .long 0xFF014004
TC_CMR_Value:
    .long 0xFFFFC000
TC_RA_REG:
    .long 0xFF014014
TC_RA_Value:
    .long 0x00000047
TC_RC_REG:
    .long 0xFF01401C
TC_RC_Value:
    .long 0x00000047
TC_CCR_REG:
    .long 0xFF014000
TC_CCR_Value:
    .long 0x00000001
TC_BCR_REG:
    .long 0xFF0140C0
 
 

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[/] [or1k_old/] [trunk/] [rc203soc/] [sw/] [uClinux/] [arch/] [armnommu/] [kernel/] [head-arm-aplio.S] - Blame information for rev 1782

Line No.	Rev	Author	Line
1	1622	jcastillo	`/*`
2			`* linux/arch/armnommu/kernel/head-arm-trio.S`
3			`*`
4			`* Copyright (C) 1999 Aplio SA`
5			`*`
6			`* Kernel 32 bit startup code for APLIO Trio chip`
7			`*/`
8			`#include`
9			`#include`
10			`#include`
11
12			`.text`
13			`.align`
14
15
16			`/*----------------------------------`
17			`* DMC & SMC Base Addresses`
18			`* ----------------------------------`
19			`*/`
20
21			`#define ARM_MODE_SVC 0x13`
22			`#define DRAM_BASE 0x00000000`
23			`#define DRAM_SIZE 0x400000`
24			`#define DRAM_LIMIT (DRAM_BASE + DRAM_SIZE)`
25
26
27			`.globl __entry,_entry`
28			`.globl __stext,_stext`
29			`.globl _start,start`
30
31			`start:`
32			`_start:`
33			`_stext:`
34			`_entry:`
35			`__stext:`
36			`__entry:`
37
38			`bl config_timer1`
39
40			`#if 0`
41			`/*`
42			`\| Initialise the Memory Controller`
43			`\| ---------------------------------`
44			`\| Copy the Image of the SMC & DMC Memory Controller`
45			`*/`
46			`adr r10, InitTableSMC /* ; get the address of the SMC chip select image */`
47			`adr r11, InitTableDMC /* ; get the address of the DMC chip select image */`
48
49			`/*`
50			`;- \| Load the address where to jump, Zero out the most significant bits.`
51			`*/`
52			`#if 0`
53			`ldr r0, =InitRemap /* ; get the real jump address ( after remap ) */`
54			`mov r0, r0, LSL #12`
55			`mov r0, r0, LSR #12`
56
57			`/*`
58			`;- \| Calculate new PC after the SMC and DMC have been reconfigured.`
59			`*/`
60			`ldr r1, [r10]`
61			`ldr r2, =0xFFF00000`
62			`and r1, r2, r1`
63
64			`add r12, r0, r1`
65			`#endif`
66
67			`/*`
68			`;- \| Copy The SMC Image into registers 0,1,2`
69			`*/`
70			`ldmia r10!, {r0-r3}`
71
72
73			`/*`
74			`;- \| Copy The DMC Image into registers 3,4,5`
75			`*/`
76			`ldmia r11!, {r4-r7}`
77
78			`/*`
79			`;- Store the SMC values (r3 contains the base address of the SMC controller)`
80			`*/`
81			`stmia r3!, {r0-r2}`
82			`/*`
83			`;- Store the DMC values (r7 contains the base address of the DMC controller)`
84			`*/`
85			`stmia r7!, {r4-r6}`
86
87			`/*`
88			`;- \| Jump to ROM at its new address`
89			`*/`
90			`new_remap_entry:`
91			`#if 0`
92			`mov pc, r12 /* jump and break the pipeline */`
93			`#endif`
94
95
96			`#endif`
97			`/* we get here when RAM is mapped to address 0 */`
98			`InitRemap:`
99
100			`/*`
101			`; Setup the SVC mode and stack pointer on the top of the internal RAM`
102			`*/`
103			`mov r0, #(ARM_MODE_SVC \| I_BIT \| F_BIT ) /* ; No interrupts */`
104			`msr cpsr, r0`
105			`ldr r13, =DRAM_LIMIT`
106
107			`/*`
108			`;------------------------------------------------------------------------------`
109			`;`
110			`; Call the Config routines...`
111			`;`
112			`;------------------------------------------------------------------------------`
113			`*/`
114
115			`bl config_PIO`
116
117			`adr r5, LC0`
118			`ldmia r5, {r5, r6, r8, sp} @ Setup stack`
119			`mov r4, #0`
120			`1: cmp r5, r8 @ Clear BSS`
121			`strcc r4, [r5],#4`
122			`bcc 1b`
123
124
125			`/*`
126			`bl config_usart0`
127			`bl config_usart1`
128			`*/`
129			`ldr r2,=0x41007000`
130			`str r2,[r6]`
131
132			`mov fp, #0`
133			`b start_kernel`
134
135
136
137
138			`LC0: .long edata`
139			`.long arm_id`
140			`.long end`
141			`.long init_user_stack + 4096`
142
143
144
145
146
147
148			`InitTableDMC:`
149			`.long 0x0000000D /* DMC MRO */`
150			`.long 0x1000000D /* DMC MR1 */`
151			`.long 0x03 /* DMC CR */`
152			`.long DMC_BASE /* DMC Base Address */`
153
154
155			`InitTableSMC:`
156			`.long 0x40003125 /* SMC CSR0 */`
157			`.long 0 /* SMC CSR1 */`
158			`.long 0 /* SMC CSR2 */`
159			`.long SMC_BASE /* SMC Base Address */`
160
161
162
163			`InitPIOs:`
164			`/*`
165			`;- \|`
166			`;- \| Driving a Low to any of these lines switches the LEDs on.`
167			`;- \|`
168			`;- \| PIOA 9 OUTPUT LED D28`
169			`;- \| PIOA 10-20 OUTPUT LED D17-27`
170			`;- \| PIOA 21-31 OUTPUT LED D29-D39`
171			`;- \| PIOB 10-15 OUTPUT LED D40-D45`
172			`*/`
173
174			`config_PIO:`
175			`/*`
176			`;- Configure PIOA`
177			`*/`
178			`ldr r1, PIOA_Enable_Reg`
179			`ldr r2, PIOA_Enable_Value`
180			`str r2, [r1]`
181
182			`ldr r1, PIOA_Disable_Reg`
183			`ldr r2, PIOA_Disable_Value`
184			`str r2, [r1]`
185
186			`ldr r1, PIOA_COD_Reg`
187			`ldr r2, PIOA_COD_Value`
188			`str r2, [r1]`
189
190			`ldr r1, PIOA_OE_Reg`
191			`ldr r2, PIOA_OE_Value`
192			`str r2, [r1]`
193
194			`ldr r1, PIOA_OD_Reg`
195			`ldr r2, PIOA_OD_Value`
196			`str r2, [r1]`
197
198			`/*`
199			`;- Configure PIOB`
200			`*/`
201			`ldr r1, PIOB_Enable_Reg`
202			`ldr r2, PIOB_Enable_Value`
203			`str r2, [r1]`
204
205			`ldr r1, PIOB_Disable_Reg`
206			`ldr r2, PIOB_Disable_Value`
207			`str r2, [r1]`
208
209			`ldr r1, PIOB_COD_Reg`
210			`ldr r2, PIOB_COD_Value`
211			`str r2, [r1]`
212
213			`ldr r1, PIOB_OE_Reg`
214			`ldr r2, PIOB_OE_Value`
215			`str r2, [r1]`
216
217			`ldr r1, PIOB_OD_Reg`
218			`ldr r2, PIOB_OD_Value`
219			`str r2, [r1]`
220
221			`mov pc,lr`
222
223			`/*`
224			`;------------------------------------------------------------------------------`
225			`;`
226			`; PIO configuration details`
227			`;`
228			`;------------------------------------------------------------------------------`
229			`*/`
230			`PIOA_Enable_Reg:`
231			`.long 0xFF00C000`
232			`PIOA_Enable_Value:`
233			`.long 0xFFFFFFFF`
234			`PIOA_Disable_Reg:`
235			`.long 0xFF00C004`
236			`PIOA_Disable_Value:`
237			`.long 0x00000000`
238			`PIOA_OE_Reg:`
239			`.long 0xFF00C010`
240			`PIOA_OE_Value:`
241			`.long 0xFFFFFFFF`
242			`PIOA_OD_Reg:`
243			`.long 0xFF00C014`
244			`PIOA_OD_Value:`
245			`.long 0x00000000`
246			`PIOA_COD_Reg:`
247			`.long 0xFF00C034`
248			`PIOA_COD_Value:`
249			`.long 0xFFFFFFFF`
250
251			`PIOB_Enable_Reg:`
252			`.long 0xFF010000`
253			`PIOB_Enable_Value:`
254			`.long 0xFFFFFFFF`
255			`PIOB_Disable_Reg:`
256			`.long 0xFF010004`
257			`PIOB_Disable_Value:`
258			`.long 0x000003FF`
259			`PIOB_OE_Reg:`
260			`.long 0xFF010010`
261			`PIOB_OE_Value:`
262			`.long 0x0000FE4B`
263			`PIOB_OD_Reg:`
264			`.long 0xFF010014`
265			`PIOB_OD_Value:`
266			`.long 0x000001B4`
267			`PIOB_COD_Reg:`
268			`.long 0xFF00C034`
269			`PIOB_COD_Value:`
270			`.long 0xFFFFFFFF`
271
272			`/*`
273			`;------------------------------------------------------------------------------`
274			`;`
275			`; Configure timer 1, This timer channel is connected to DRAM controller`
276			`; and is used as the trigger for a DRAM refresh cycle.`
277			`; Trashes r1, r2`
278			`;`
279			`;------------------------------------------------------------------------------`
280			`*/`
281			`config_timer1:`
282			`ldr r1, TC_CMR_REG`
283			`ldr r2, TC_CMR_Value`
284			`str r2, [r1]`
285
286			`ldr r1, TC_RA_REG`
287			`ldr r2, TC_RA_Value`
288			`str r2, [r1]`
289
290			`ldr r1, TC_RC_REG`
291			`ldr r2, TC_RC_Value`
292			`str r2, [r1]`
293
294			`ldr r1, TC_CCR_REG`
295			`ldr r2, TC_CCR_Value`
296			`str r2, [r1]`
297
298			`ldr r1, TC_BCR_REG`
299			`ldr r2, TC_CCR_Value`
300			`str r2, [r1]`
301
302			`mov pc, lr`
303
304			`/*`
305			`;------------------------------------------------------------------------------`
306			`;`
307			`; Timer Control Configuration Data`
308			`;`
309			`;------------------------------------------------------------------------------`
310			`*/`
311
312			`TC_CMR_REG:`
313			`.long 0xFF014004`
314			`TC_CMR_Value:`
315			`.long 0xFFFFC000`
316			`TC_RA_REG:`
317			`.long 0xFF014014`
318			`TC_RA_Value:`
319			`.long 0x00000047`
320			`TC_RC_REG:`
321			`.long 0xFF01401C`
322			`TC_RC_Value:`
323			`.long 0x00000047`
324			`TC_CCR_REG:`
325			`.long 0xFF014000`
326			`TC_CCR_Value:`
327			`.long 0x00000001`
328			`TC_BCR_REG:`
329			`.long 0xFF0140C0`
330
331