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Line No.	Rev	Author	Line
1	1622	jcastillo	`/*`
2			`* linux/arch/arm/lib/iputils.S`
3			`*`
4			`* Copyright (C) 1995, 1996 Russell King`
5			`*/`
6
7			`#include`
8			`.text`
9			`@ r0 = buffer`
10			`@ r1 = len`
11			`@ r2 = sum`
12			`.global _csum_partial,csum_partial`
13			`csum_partial:`
14			`_csum_partial: tst r0, #2`
15			`beq Lalignok`
16			`subs r1, r1, #2`
17			`addmi r1, r1, #2`
18			`bmi Lnobits32`
19			`bic r0, r0, #3`
20			`ldr r3, [r0], #4`
21			`adds r2, r2, r3, lsr #16`
22			`adcs r2, r2, #0`
23			`Lalignok: adds r2, r2, #0`
24			`bics ip, r1, #31`
25			`beq Lnobits32`
26			`stmfd sp!, {r4 - r6}`
27			`Llp32: ldmia r0!, {r3 - r6}`
28			`adcs r2, r2, r3`
29			`adcs r2, r2, r4`
30			`adcs r2, r2, r5`
31			`adcs r2, r2, r6`
32			`ldmia r0!, {r3 - r6}`
33			`adcs r2, r2, r3`
34			`adcs r2, r2, r4`
35			`adcs r2, r2, r5`
36			`adcs r2, r2, r6`
37			`sub ip, ip, #32`
38			`teq ip, #0`
39			`bne Llp32`
40			`adcs r2, r2, #0`
41			`ldmfd sp!, {r4 - r6}`
42			`Lnobits32: ands ip, r1, #0x1c`
43			`beq Lnobits4`
44			`Lbits32lp: ldr r3, [r0], #4`
45			`adcs r2, r2, r3`
46			`sub ip, ip, #4`
47			`teq ip, #0`
48			`bne Lbits32lp`
49			`adcs r2, r2, #0`
50			`Lnobits4: ands ip, r1, #3`
51			`moveq r0, r2`
52			`RETINSTR(moveq,pc,lr)`
53			`mov ip, ip, lsl #3`
54			`rsb ip, ip, #32`
55			`ldr r3, [r0]`
56			`mov r3, r3, lsl ip`
57			`adds r2, r2, r3, lsr ip`
58			`adc r0, r2, #0`
59			`RETINSTR(mov,pc,lr)`
60
61			`@ r0 = src`
62			`@ r1 = dst (should be aligned on 16-bit)`
63			`@ r2 = len`
64			`@ r3 = sum`
65			`.global ___csum_partial_copy_fromuser,__csum_partial_copy_fromuser`
66			`__csum_partial_copy_fromuser:`
67			`___csum_partial_copy_fromuser:`
68			`mov ip, sp`
69			`stmfd sp!, {r4 - r8, fp, ip, lr, pc}`
70			`sub fp, ip, #4`
71			`cmp r2, #4`
72			`blt Ltoo_small_user`
73			`tst r1, #2 @ Test destination alignment`
74			`beq Ldst_aligned_user`
75			`subs r2, r2, #2 @ We dont know if SRC is aligned...`
76			`ldrbt ip, [r0], #1`
77			`ldrbt r8, [r0], #1`
78			`orr ip, ip, r8, lsl #8`
79			`adds r3, r3, ip`
80			`adcs r3, r3, #0`
81			`strb ip, [r1], #1`
82			`mov ip, ip, lsr #8`
83			`strb ip, [r1], #1 @ Destination now aligned`
84			`Ldst_aligned_user:`
85			`tst r0, #3`
86			`bne Lsrc_not_aligned_user`
87			`adds r3, r3, #0`
88			`bics ip, r2, #15 @ Routine for src & dst aligned`
89			`beq 2f`
90			`1: ldrt r4, [r0], #4`
91			`ldrt r5, [r0], #4`
92			`ldrt r6, [r0], #4`
93			`ldrt r7, [r0], #4`
94			`stmia r1!, {r4, r5, r6, r7}`
95			`adcs r3, r3, r4`
96			`adcs r3, r3, r5`
97			`adcs r3, r3, r6`
98			`adcs r3, r3, r7`
99			`sub ip, ip, #16`
100			`teq ip, #0`
101			`bne 1b`
102			`2: ands ip, r2, #12`
103			`beq 4f`
104			`tst ip, #8`
105			`beq 3f`
106			`ldrt r4, [r0], #4`
107			`ldrt r5, [r0], #4`
108			`stmia r1!, {r4, r5}`
109			`adcs r3, r3, r4`
110			`adcs r3, r3, r5`
111			`tst ip, #4`
112			`beq 4f`
113			`3: ldrt r4, [r0], #4`
114			`str r4, [r1], #4`
115			`adcs r3, r3, r4`
116			`4: ands r2, r2, #3`
117			`adceq r0, r3, #0`
118			`LOADREGS(eqea,fp,{r4 - r8, fp, sp, pc})`
119			`ldrt r4, [r0], #4`
120			`tst r2, #2`
121			`beq Lexit`
122			`adcs r3, r3, r4, lsl #16`
123			`strb r4, [r1], #1`
124			`mov r4, r4, lsr #8`
125			`strb r4, [r1], #1`
126			`mov r4, r4, lsr #8`
127			`Lexit: tst r2, #1`
128			`strneb r4, [r1], #1`
129			`andne r4, r4, #255`
130			`adcnes r3, r3, r4`
131			`adcs r0, r3, #0`
132			`LOADREGS(ea,fp,{r4 - r8, fp, sp, pc})`
133
134			`Ltoo_small_user:`
135			`teq r2, #0`
136			`LOADREGS(eqea,fp,{r4 - r8, fp, sp, pc})`
137			`cmp r2, #2`
138			`blt Ltoo_small_user1`
139			`ldrbt ip, [r0], #1`
140			`ldrbt r8, [r0], #1`
141			`orr ip, ip, r8, lsl #8`
142			`adds r3, r3, ip`
143			`strb ip, [r1], #1`
144			`strb r8, [r1], #1`
145			`tst r2, #1`
146			`Ltoo_small_user1:`
147			`ldrnebt ip, [r0], #1`
148			`strneb ip, [r1], #1`
149			`adcnes r3, r3, ip`
150			`adcs r0, r3, #0`
151			`LOADREGS(ea,fp,{r4 - r8, fp, sp, pc})`
152
153			`Lsrc_not_aligned_user:`
154			`cmp r2, #4`
155			`blt Ltoo_small_user`
156			`and ip, r0, #3`
157			`bic r0, r0, #3`
158			`ldrt r4, [r0], #4`
159			`cmp ip, #2`
160			`beq Lsrc2_aligned_user`
161			`bhi Lsrc3_aligned_user`
162			`mov r4, r4, lsr #8`
163			`adds r3, r3, #0`
164			`bics ip, r2, #15`
165			`beq 2f`
166			`1: ldrt r5, [r0], #4`
167			`ldrt r6, [r0], #4`
168			`ldrt r7, [r0], #4`
169			`ldrt r8, [r0], #4`
170			`orr r4, r4, r5, lsl #24`
171			`mov r5, r5, lsr #8`
172			`orr r5, r5, r6, lsl #24`
173			`mov r6, r6, lsr #8`
174			`orr r6, r6, r7, lsl #24`
175			`mov r7, r7, lsr #8`
176			`orr r7, r7, r8, lsl #24`
177			`stmia r1!, {r4, r5, r6, r7}`
178			`adcs r3, r3, r4`
179			`adcs r3, r3, r5`
180			`adcs r3, r3, r6`
181			`adcs r3, r3, r7`
182			`mov r4, r8, lsr #8`
183			`sub ip, ip, #16`
184			`teq ip, #0`
185			`bne 1b`
186			`2: ands ip, r2, #12`
187			`beq 4f`
188			`tst ip, #8`
189			`beq 3f`
190			`ldrt r5, [r0], #4`
191			`ldrt r6, [r0], #4`
192			`orr r4, r4, r5, lsl #24`
193			`mov r5, r5, lsr #8`
194			`orr r5, r5, r6, lsl #24`
195			`stmia r1!, {r4, r5}`
196			`adcs r3, r3, r4`
197			`adcs r3, r3, r5`
198			`mov r4, r6, lsr #8`
199			`tst ip, #4`
200			`beq 4f`
201			`3: ldrt r5, [r0], #4`
202			`orr r4, r4, r5, lsl #24`
203			`str r4, [r1], #4`
204			`adcs r3, r3, r4`
205			`mov r4, r5, lsr #8`
206			`4: ands r2, r2, #3`
207			`adceq r0, r3, #0`
208			`LOADREGS(eqea,fp,{r4 - r8, fp, sp, pc})`
209			`tst r2, #2`
210			`beq Lexit`
211			`adcs r3, r3, r4, lsl #16`
212			`strb r4, [r1], #1`
213			`mov r4, r4, lsr #8`
214			`strb r4, [r1], #1`
215			`mov r4, r4, lsr #8`
216			`b Lexit`
217
218			`Lsrc2_aligned_user:`
219			`mov r4, r4, lsr #16`
220			`adds r3, r3, #0`
221			`bics ip, r2, #15`
222			`beq 2f`
223			`1: ldrt r5, [r0], #4`
224			`ldrt r6, [r0], #4`
225			`ldrt r7, [r0], #4`
226			`ldrt r8, [r0], #4`
227			`orr r4, r4, r5, lsl #16`
228			`mov r5, r5, lsr #16`
229			`orr r5, r5, r6, lsl #16`
230			`mov r6, r6, lsr #16`
231			`orr r6, r6, r7, lsl #16`
232			`mov r7, r7, lsr #16`
233			`orr r7, r7, r8, lsl #16`
234			`stmia r1!, {r4, r5, r6, r7}`
235			`adcs r3, r3, r4`
236			`adcs r3, r3, r5`
237			`adcs r3, r3, r6`
238			`adcs r3, r3, r7`
239			`mov r4, r8, lsr #16`
240			`sub ip, ip, #16`
241			`teq ip, #0`
242			`bne 1b`
243			`2: ands ip, r2, #12`
244			`beq 4f`
245			`tst ip, #8`
246			`beq 3f`
247			`ldrt r5, [r0], #4`
248			`ldrt r6, [r0], #4`
249			`orr r4, r4, r5, lsl #16`
250			`mov r5, r5, lsr #16`
251			`orr r5, r5, r6, lsl #16`
252			`stmia r1!, {r4, r5}`
253			`adcs r3, r3, r4`
254			`adcs r3, r3, r5`
255			`mov r4, r6, lsr #16`
256			`tst ip, #4`
257			`beq 4f`
258			`3: ldrt r5, [r0], #4`
259			`orr r4, r4, r5, lsl #16`
260			`str r4, [r1], #4`
261			`adcs r3, r3, r4`
262			`mov r4, r5, lsr #16`
263			`4: ands r2, r2, #3`
264			`adceq r0, r3, #0`
265			`LOADREGS(eqea,fp,{r4 - r8, fp, sp, pc})`
266			`tst r2, #2`
267			`beq Lexit`
268			`adcs r3, r3, r4, lsl #16`
269			`strb r4, [r1], #1`
270			`mov r4, r4, lsr #8`
271			`strb r4, [r1], #1`
272			`ldrb r4, [r0], #1`
273			`b Lexit`
274
275			`Lsrc3_aligned_user:`
276			`mov r4, r4, lsr #24`
277			`adds r3, r3, #0`
278			`bics ip, r2, #15`
279			`beq 2f`
280			`1: ldrt r5, [r0], #4`
281			`ldrt r6, [r0], #4`
282			`ldrt r7, [r0], #4`
283			`ldrt r8, [r0], #4`
284			`orr r4, r4, r5, lsl #8`
285			`mov r5, r5, lsr #24`
286			`orr r5, r5, r6, lsl #8`
287			`mov r6, r6, lsr #24`
288			`orr r6, r6, r7, lsl #8`
289			`mov r7, r7, lsr #24`
290			`orr r7, r7, r8, lsl #8`
291			`stmia r1!, {r4, r5, r6, r7}`
292			`adcs r3, r3, r4`
293			`adcs r3, r3, r5`
294			`adcs r3, r3, r6`
295			`adcs r3, r3, r7`
296			`mov r4, r8, lsr #24`
297			`sub ip, ip, #16`
298			`teq ip, #0`
299			`bne 1b`
300			`2: ands ip, r2, #12`
301			`beq 4f`
302			`tst ip, #8`
303			`beq 3f`
304			`ldrt r5, [r0], #4`
305			`ldrt r6, [r0], #4`
306			`orr r4, r4, r5, lsl #8`
307			`mov r5, r5, lsr #24`
308			`orr r5, r5, r6, lsl #8`
309			`stmia r1!, {r4, r5}`
310			`adcs r3, r3, r4`
311			`adcs r3, r3, r5`
312			`mov r4, r6, lsr #24`
313			`tst ip, #4`
314			`beq 4f`
315			`3: ldrt r5, [r0], #4`
316			`orr r4, r4, r5, lsl #8`
317			`str r4, [r1], #4`
318			`adcs r3, r3, r4`
319			`mov r4, r5, lsr #24`
320			`4: ands r2, r2, #3`
321			`adceq r0, r3, #0`
322			`LOADREGS(eqea,fp,{r4 - r8, fp, sp, pc})`
323			`tst r2, #2`
324			`beq Lexit`
325			`adcs r3, r3, r4, lsl #16`
326			`strb r4, [r1], #1`
327			`ldrt r4, [r0], #4`
328			`strb r4, [r1], #1`
329			`adcs r3, r3, r4, lsl #24`
330			`mov r4, r4, lsr #8`
331			`b Lexit`
332
333			`@ r0 = src`
334			`@ r1 = dst`
335			`@ r2 = len`
336			`@ r3 = sum`
337
338			`.global _csum_partial_copy,csum_partial_copy`
339			`csum_partial_copy:`
340			`_csum_partial_copy:`
341			`mov ip, sp`
342			`stmfd sp!, {r4 - r8, fp, ip, lr, pc}`
343			`sub fp, ip, #4`
344			`cmp r2, #4`
345			`blt Ltoo_small`
346			`tst r1, #2 @ Test destination alignment`
347			`beq Ldst_aligned`
348			`subs r2, r2, #2 @ We dont know if SRC is aligned...`
349			`ldrb ip, [r0], #1`
350			`ldrb r8, [r0], #1`
351			`orr ip, ip, r8, lsl #8`
352			`adds r3, r3, ip`
353			`adcs r3, r3, #0`
354			`strb ip, [r1], #1`
355			`mov ip, ip, lsr #8`
356			`strb ip, [r1], #1 @ Destination now aligned`
357			`Ldst_aligned: tst r0, #3`
358			`bne Lsrc_not_aligned`
359			`adds r3, r3, #0`
360			`bics ip, r2, #15 @ Routine for src & dst aligned`
361			`beq 3f`
362			`1: ldmia r0!, {r4, r5, r6, r7}`
363			`stmia r1!, {r4, r5, r6, r7}`
364			`adcs r3, r3, r4`
365			`adcs r3, r3, r5`
366			`adcs r3, r3, r6`
367			`adcs r3, r3, r7`
368			`sub ip, ip, #16`
369			`teq ip, #0`
370			`bne 1b`
371			`3: ands ip, r2, #12`
372			`beq 5f`
373			`tst ip, #8`
374			`beq 4f`
375			`ldmia r0!, {r4, r5}`
376			`stmia r1!, {r4, r5}`
377			`adcs r3, r3, r4`
378			`adcs r3, r3, r5`
379			`tst ip, #4`
380			`beq 5f`
381			`4: ldr r4, [r0], #4`
382			`str r4, [r1], #4`
383			`adcs r3, r3, r4`
384			`5: ands r2, r2, #3`
385			`adceq r0, r3, #0`
386			`LOADREGS(eqea,fp,{r4 - r8, fp, sp, pc})`
387			`ldr r4, [r0], #4`
388			`tst r2, #2`
389			`beq Lexit`
390			`adcs r3, r3, r4, lsl #16`
391			`strb r4, [r1], #1`
392			`mov r4, r4, lsr #8`
393			`strb r4, [r1], #1`
394			`mov r4, r4, lsr #8`
395			`b Lexit`
396
397			`Ltoo_small: teq r2, #0`
398			`LOADREGS(eqea,fp,{r8, fp, sp, pc})`
399			`cmp r2, #2`
400			`blt Ltoo_small1`
401			`ldrb ip, [r0], #1`
402			`ldrb r8, [r0], #1`
403			`orr ip, ip, r8, lsl #8`
404			`adds r3, r3, ip`
405			`strb ip, [r1], #1`
406			`strb r8, [r1], #1`
407			`tst r2, #1`
408			`Ltoo_small1: ldrneb ip, [r0], #1`
409			`strneb ip, [r1], #1`
410			`adcnes r3, r3, ip`
411			`adcs r0, r3, #0`
412			`LOADREGS(ea,fp,{r8, fp, sp, pc})`
413
414			`Lsrc_not_aligned:`
415			`cmp r2, #4`
416			`blt Ltoo_small`
417			`and ip, r0, #3`
418			`bic r0, r0, #3`
419			`ldr r4, [r0], #4`
420			`cmp ip, #2`
421			`beq Lsrc2_aligned`
422			`bhi Lsrc3_aligned`
423			`mov r4, r4, lsr #8`
424			`adds r3, r3, #0`
425			`bics ip, r2, #15`
426			`beq 2f`
427			`1: ldmia r0!, {r5, r6, r7, r8}`
428			`orr r4, r4, r5, lsl #24`
429			`mov r5, r5, lsr #8`
430			`orr r5, r5, r6, lsl #24`
431			`mov r6, r6, lsr #8`
432			`orr r6, r6, r7, lsl #24`
433			`mov r7, r7, lsr #8`
434			`orr r7, r7, r8, lsl #24`
435			`stmia r1!, {r4, r5, r6, r7}`
436			`adcs r3, r3, r4`
437			`adcs r3, r3, r5`
438			`adcs r3, r3, r6`
439			`adcs r3, r3, r7`
440			`mov r4, r8, lsr #8`
441			`sub ip, ip, #16`
442			`teq ip, #0`
443			`bne 1b`
444			`2: ands ip, r2, #12`
445			`beq 4f`
446			`tst ip, #8`
447			`beq 3f`
448			`ldmia r0!, {r5, r6}`
449			`orr r4, r4, r5, lsl #24`
450			`mov r5, r5, lsr #8`
451			`orr r5, r5, r6, lsl #24`
452			`stmia r1!, {r4, r5}`
453			`adcs r3, r3, r4`
454			`adcs r3, r3, r5`
455			`mov r4, r6, lsr #8`
456			`tst ip, #4`
457			`beq 4f`
458			`3: ldr r5, [r0], #4`
459			`orr r4, r4, r5, lsl #24`
460			`str r4, [r1], #4`
461			`adcs r3, r3, r4`
462			`mov r4, r5, lsr #8`
463			`4: ands r2, r2, #3`
464			`adceq r0, r3, #0`
465			`LOADREGS(eqea,fp,{r4 - r8, fp, sp, pc})`
466			`tst r2, #2`
467			`beq Lexit`
468			`adcs r3, r3, r4, lsl #16`
469			`strb r4, [r1], #1`
470			`mov r4, r4, lsr #8`
471			`strb r4, [r1], #1`
472			`mov r4, r4, lsr #8`
473			`b Lexit`
474
475			`Lsrc2_aligned: mov r4, r4, lsr #16`
476			`adds r3, r3, #0`
477			`bics ip, r2, #15`
478			`beq 2f`
479			`1: ldmia r0!, {r5, r6, r7, r8}`
480			`orr r4, r4, r5, lsl #16`
481			`mov r5, r5, lsr #16`
482			`orr r5, r5, r6, lsl #16`
483			`mov r6, r6, lsr #16`
484			`orr r6, r6, r7, lsl #16`
485			`mov r7, r7, lsr #16`
486			`orr r7, r7, r8, lsl #16`
487			`stmia r1!, {r4, r5, r6, r7}`
488			`adcs r3, r3, r4`
489			`adcs r3, r3, r5`
490			`adcs r3, r3, r6`
491			`adcs r3, r3, r7`
492			`mov r4, r8, lsr #16`
493			`sub ip, ip, #16`
494			`teq ip, #0`
495			`bne 1b`
496			`2: ands ip, r2, #12`
497			`beq 4f`
498			`tst ip, #8`
499			`beq 3f`
500			`ldmia r0!, {r5, r6}`
501			`orr r4, r4, r5, lsl #16`
502			`mov r5, r5, lsr #16`
503			`orr r5, r5, r6, lsl #16`
504			`stmia r1!, {r4, r5}`
505			`adcs r3, r3, r4`
506			`adcs r3, r3, r5`
507			`mov r4, r6, lsr #16`
508			`tst ip, #4`
509			`beq 4f`
510			`3: ldr r5, [r0], #4`
511			`orr r4, r4, r5, lsl #16`
512			`str r4, [r1], #4`
513			`adcs r3, r3, r4`
514			`mov r4, r5, lsr #16`
515			`4: ands r2, r2, #3`
516			`adceq r0, r3, #0`
517			`LOADREGS(eqea,fp,{r4 - r8, fp, sp, pc})`
518			`tst r2, #2`
519			`beq Lexit`
520			`adcs r3, r3, r4, lsl #16`
521			`strb r4, [r1], #1`
522			`mov r4, r4, lsr #8`
523			`strb r4, [r1], #1`
524			`ldrb r4, [r0], #1`
525			`b Lexit`
526
527			`Lsrc3_aligned: mov r4, r4, lsr #24`
528			`adds r3, r3, #0`
529			`bics ip, r2, #15`
530			`beq 2f`
531			`1: ldmia r0!, {r5, r6, r7, r8}`
532			`orr r4, r4, r5, lsl #8`
533			`mov r5, r5, lsr #24`
534			`orr r5, r5, r6, lsl #8`
535			`mov r6, r6, lsr #24`
536			`orr r6, r6, r7, lsl #8`
537			`mov r7, r7, lsr #24`
538			`orr r7, r7, r8, lsl #8`
539			`stmia r1!, {r4, r5, r6, r7}`
540			`adcs r3, r3, r4`
541			`adcs r3, r3, r5`
542			`adcs r3, r3, r6`
543			`adcs r3, r3, r7`
544			`mov r4, r8, lsr #24`
545			`sub ip, ip, #16`
546			`teq ip, #0`
547			`bne 1b`
548			`2: ands ip, r2, #12`
549			`beq 4f`
550			`tst ip, #8`
551			`beq 3f`
552			`ldmia r0!, {r5, r6}`
553			`orr r4, r4, r5, lsl #8`
554			`mov r5, r5, lsr #24`
555			`orr r5, r5, r6, lsl #8`
556			`stmia r1!, {r4, r5}`
557			`adcs r3, r3, r4`
558			`adcs r3, r3, r5`
559			`mov r4, r6, lsr #24`
560			`tst ip, #4`
561			`beq 4f`
562			`3: ldr r5, [r0], #4`
563			`orr r4, r4, r5, lsl #8`
564			`str r4, [r1], #4`
565			`adcs r3, r3, r4`
566			`mov r4, r5, lsr #24`
567			`4: ands r2, r2, #3`
568			`adceq r0, r3, #0`
569			`LOADREGS(eqea,fp,{r4 - r8, fp, sp, pc})`
570			`tst r2, #2`
571			`beq Lexit`
572			`adcs r3, r3, r4, lsl #16`
573			`strb r4, [r1], #1`
574			`ldr r4, [r0], #4`
575			`strb r4, [r1], #1`
576			`adcs r3, r3, r4, lsl #24`
577			`mov r4, r4, lsr #8`
578			`b Lexit`

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