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1622 |
jcastillo |
/*
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* linux/arch/arm/mm/arm2,3.S: MMU functions for ARM2,3
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*
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* (C) 1997 Russell King
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*
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* These are the low level assembler for performing cache
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* and memory functions on ARM2, ARM250 and ARM3 processors.
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*/
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#include
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#include "../lib/constants.h"
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/*
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* Code common to all processors - MEMC specific not processor
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* specific!
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*/
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LC1: .word _page_nr
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/*
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* Function: arm2_3_update_map (struct task_struct *tsk)
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*
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* Params : tsk Task structure to be updated
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*
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* Purpose : Re-generate memc maps for task from its pseudo page tables
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*/
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_arm2_3_update_map:
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mov ip, sp
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stmfd sp!, {r4 - r6, fp, ip, lr, pc}
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sub fp, ip, #4
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add r1, r0, #TSS_MEMCMAP
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ldr r2, LC1
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ldr r2, [r2]
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mov r3, #0x03f00000
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orr r3, r3, #0x00000f00
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orr r4, r3, #1
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orr r5, r3, #2
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orr r6, r3, #3
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1: stmia r1!, {r3, r4, r5, r6} @ Default mapping (null mapping)
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add r3, r3, #4
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add r4, r4, #4
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add r5, r5, #4
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add r6, r6, #4
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stmia r1!, {r3, r4, r5, r6} @ Default mapping (null mapping)
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add r3, r3, #4
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add r4, r4, #4
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add r5, r5, #4
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add r6, r6, #4
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subs r2, r2, #8
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bhi 1b
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adr r2, Lphystomemc32 @ r2 = conversion table to logical page number
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ldr r4, [r0, #TSS_MEMMAP] @ r4 = active mem map
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add r5, r4, #32 << 2 @ r5 = end of active mem map
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add r0, r0, #TSS_MEMCMAP @ r0 = memc map
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mov r6, #0
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2: ldmia r4!, {r1, r3}
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tst r1, #PAGE_PRESENT
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blne update_map_pgd
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add r6, r6, #32 << 2
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tst r3, #PAGE_PRESENT
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blne update_map_pgd3
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add r6, r6, #32 << 2
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cmp r4, r5
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blt 2b
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ldmea fp, {r4 - r6, fp, sp, pc}^
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@ r0,r2,r3,r4,r5 = preserve
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@ r1,ip = available
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@ r0 = memc map
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@ r1 = pgd entry
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@ r2 = conversion table
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@ r6 = logical page no << 2
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update_map_pgd3:
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mov r1, r3
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update_map_pgd: stmfd sp!, {r3, r4, r5, lr}
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bic r4, r1, #3 @ r4 = page table
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sub r5, r6, #1 << 2
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add ip, r4, #32 << 2 @ ip = end of page table
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1: ldr r1, [r4], #4 @ get entry
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add r5, r5, #1 << 2
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tst r1, #PAGE_PRESENT @ page present?
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blne Lconvertmemc @ yes
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ldr r1, [r4], #4 @ get entry
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add r5, r5, #1 << 2
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tst r1, #PAGE_PRESENT @ page present?
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blne Lconvertmemc @ yes
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ldr r1, [r4], #4 @ get entry
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add r5, r5, #1 << 2
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tst r1, #PAGE_PRESENT @ page present?
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blne Lconvertmemc @ yes
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ldr r1, [r4], #4 @ get entry
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add r5, r5, #1 << 2
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tst r1, #PAGE_PRESENT @ page present?
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blne Lconvertmemc @ yes
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cmp r4, ip
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blt 1b
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ldmfd sp!, {r3, r4, r5, pc}^
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Lconvertmemc: mov r3, r1, lsr #13 @
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and r3, r3, #0x3fc @ Convert to memc physical page no
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ldr r3, [r2, r3] @
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tst r1, #PAGE_OLD|PAGE_NOT_USER @ check for MEMC read
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biceq r3, r3, #0x200 @
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tsteq r1, #PAGE_READONLY|PAGE_CLEAN @ check for MEMC write
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biceq r3, r3, #0x300 @
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orr r3, r3, r5, lsl #13
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and r1, r5, #0x01800000 >> 13
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orr r3, r3, r1
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and r1, r3, #255
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str r3, [r0, r1, lsl #2]
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movs pc, lr
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/*
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* Function: arm2_3_update_cache (struct task_struct *tsk, unsigned long addr, pte_t pte)
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* Params : tsk Task to update
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* address Address of fault.
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* pte New PTE at address
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* Purpose : Update the mapping for this address.
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* Notes : does the ARM3 run faster if you dont use the result in the next instruction?
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*/
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_arm2_3_update_cache:
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tst r2, #PAGE_PRESENT
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moveqs pc, lr
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mov r3, r2, lsr #13 @ Physical page no.
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adr ip, Lphystomemc32 @ Convert to logical page number
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and r3, r3, #0x3fc
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mov r1, r1, lsr #15
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ldr r3, [ip, r3] @ Convert to memc phys page no.
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tst r2, #PAGE_OLD|PAGE_NOT_USER
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biceq r3, r3, #0x200
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tsteq r2, #PAGE_READONLY|PAGE_CLEAN
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biceq r3, r3, #0x300
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ldr ip, [pc, #LC0 - . - 8]
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orr r3, r3, r1, lsl #15
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and r1, r1, #0x300
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ldr ip, [ip]
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orr r3, r3, r1, lsl #2
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teq ip, r0
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and r2, r3, #255
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add r0, r0, #TSS_MEMCMAP
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streqb r3, [r3]
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str r3, [r0, r2, lsl #2]
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movs pc, lr
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#define PCD(a0, a1, a2, a3, a4, a5, a6, a7, a8, a9, aa, ab, ac, ad, ae, af) \
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.long a0| 0x03800300; .long a1| 0x03800300;\
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.long a2| 0x03800300; .long a3| 0x03800300;\
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.long a4| 0x03800300; .long a5| 0x03800300;\
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.long a6| 0x03800300; .long a7| 0x03800300;\
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.long a8| 0x03800300; .long a9| 0x03800300;\
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.long aa| 0x03800300; .long ab| 0x03800300;\
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.long ac| 0x03800300; .long ad| 0x03800300;\
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.long ae| 0x03800300; .long af| 0x03800300
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@ Table to map from page number to vidc page number
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Lphystomemc32: PCD(0x00,0x08,0x10,0x18,0x20,0x28,0x30,0x38,0x40,0x48,0x50,0x58,0x60,0x68,0x70,0x78)
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PCD(0x01,0x09,0x11,0x19,0x21,0x29,0x31,0x39,0x41,0x49,0x51,0x59,0x61,0x69,0x71,0x79)
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PCD(0x04,0x0C,0x14,0x1C,0x24,0x2C,0x34,0x3C,0x44,0x4C,0x54,0x5C,0x64,0x6C,0x74,0x7C)
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PCD(0x05,0x0D,0x15,0x1D,0x25,0x2D,0x35,0x3D,0x45,0x4D,0x55,0x5D,0x65,0x6D,0x75,0x7D)
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PCD(0x02,0x0A,0x12,0x1A,0x22,0x2A,0x32,0x3A,0x42,0x4A,0x52,0x5A,0x62,0x6A,0x72,0x7A)
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PCD(0x03,0x0B,0x13,0x1B,0x23,0x2B,0x33,0x3B,0x43,0x4B,0x53,0x5B,0x63,0x6B,0x73,0x7B)
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PCD(0x06,0x0E,0x16,0x1E,0x26,0x2E,0x36,0x3E,0x46,0x4E,0x56,0x5E,0x66,0x6E,0x76,0x7E)
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PCD(0x07,0x0F,0x17,0x1F,0x27,0x2F,0x37,0x3F,0x47,0x4F,0x57,0x5F,0x67,0x6F,0x77,0x7F)
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PCD(0x80,0x88,0x90,0x98,0xA0,0xA8,0xB0,0xB8,0xC0,0xC8,0xD0,0xD8,0xE0,0xE8,0xF0,0xF8)
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PCD(0x81,0x89,0x91,0x99,0xA1,0xA9,0xB1,0xB9,0xC1,0xC9,0xD1,0xD9,0xE1,0xE9,0xF1,0xF9)
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PCD(0x84,0x8C,0x94,0x9C,0xA4,0xAC,0xB4,0xBC,0xC4,0xCC,0xD4,0xDC,0xE4,0xEC,0xF4,0xFC)
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PCD(0x85,0x8D,0x95,0x9D,0xA5,0xAD,0xB5,0xBD,0xC5,0xCD,0xD5,0xDD,0xE5,0xED,0xF5,0xFD)
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PCD(0x82,0x8A,0x92,0x9A,0xA2,0xAA,0xB2,0xBA,0xC2,0xCA,0xD2,0xDA,0xE2,0xEA,0xF2,0xFA)
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PCD(0x83,0x8B,0x93,0x9B,0xA3,0xAB,0xB3,0xBB,0xC3,0xCB,0xD3,0xDB,0xE3,0xEB,0xF3,0xFB)
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PCD(0x86,0x8E,0x96,0x9E,0xA6,0xAE,0xB6,0xBE,0xC6,0xCE,0xD6,0xDE,0xE6,0xEE,0xF6,0xFE)
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PCD(0x87,0x8F,0x97,0x9F,0xA7,0xAF,0xB7,0xBF,0xC7,0xCF,0xD7,0xDF,0xE7,0xEF,0xF7,0xFF)
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/*
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* Function: arm2_3_data_abort ()
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*
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* Params : r0 = address of aborted instruction
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*
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* Purpose :
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*
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* Returns : r0 = address of abort
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* : r1 = FSR
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* : r2 != 0 if writing
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*/
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_arm2_3_data_abort:
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movs pc, lr
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_arm2_3_check_bugs:
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movs pc, lr
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/*
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* Processor specific - ARM2
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*/
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LC0: .word _current
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.word _page_nr
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/*
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* Function: arm2_switch_to (struct task_struct *prev, struct task_struct *next)
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*
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* Params : prev Old task structure
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* : next New task structure for process to run
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*
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* Purpose : Perform a task switch, saving the old processes state, and restoring
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* the new.
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*
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* Notes : We don't fiddle with the FP registers here - we postpone this until
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* the new task actually uses FP. This way, we don't swap FP for tasks
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* that do not require it.
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*/
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_arm2_switch_to:
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stmfd sp!, {r4 - r9, fp, lr} @ Store most regs on stack
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str sp, [r0, #TSS_SAVE] @ Save sp_SVC
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ldr r2, LC0
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str r1, [r2]
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ldr sp, [r1, #TSS_SAVE] @ Get saved sp_SVC
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mov r4, r1
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add r0, r1, #TSS_MEMCMAP @ Remap MEMC
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ldr r1, LC0 + 4
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ldr r1, [r1]
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1: ldmia r0!, {r2, r3, r5, r6}
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strb r2, [r2]
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strb r3, [r3]
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strb r5, [r5]
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strb r6, [r6]
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ldmia r0!, {r2, r3, r5, r6}
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strb r2, [r2]
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| 233 |
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strb r3, [r3]
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| 234 |
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strb r5, [r5]
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strb r6, [r6]
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subs r1, r1, #8
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bhi 1b
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ldmfd sp!, {r4 - r9, fp, pc}^ @ Load all regs saved previously
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/*
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| 241 |
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* Function: arm2_remap_memc (struct task_struct *tsk)
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| 242 |
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*
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| 243 |
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* Params : tsk Task structure specifing the new mapping structure
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| 244 |
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*
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| 245 |
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* Purpose : remap MEMC tables
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*/
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| 247 |
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_arm2_remap_memc:
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| 248 |
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stmfd sp!, {lr}
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| 249 |
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add r0, r0, #TSS_MEMCMAP
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| 250 |
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ldr r1, LC0 + 4
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ldr r1, [r1]
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| 252 |
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1: ldmia r0!, {r2, r3, ip, lr}
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| 253 |
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strb r2, [r2]
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strb r3, [r3]
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| 255 |
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strb ip, [ip]
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| 256 |
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strb lr, [lr]
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| 257 |
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ldmia r0!, {r2, r3, ip, lr}
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| 258 |
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strb r2, [r2]
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| 259 |
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strb r3, [r3]
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strb ip, [ip]
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| 261 |
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strb lr, [lr]
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| 262 |
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subs r1, r1, #8
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| 263 |
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bhi 1b
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| 264 |
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ldmfd sp!, {pc}^
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/*
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| 267 |
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* Function: arm2_xchg_1 (int new, volatile void *ptr)
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| 268 |
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*
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| 269 |
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* Params : new New value to store at...
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| 270 |
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* : ptr pointer to byte-wide location
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| 271 |
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*
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| 272 |
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* Purpose : Performs an exchange operation
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| 273 |
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*
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| 274 |
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* Returns : Original byte data at 'ptr'
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| 275 |
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*
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| 276 |
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* Notes : This will have to be changed if we ever use multi-processing using these
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| 277 |
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* processors, but that is very unlikely...
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| 278 |
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*/
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| 279 |
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_arm2_xchg_1: mov r2, pc
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| 280 |
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orr r2, r2, #I_BIT
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| 281 |
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teqp r2, #0
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| 282 |
|
|
ldrb r2, [r1]
|
| 283 |
|
|
strb r0, [r1]
|
| 284 |
|
|
mov r0, r2
|
| 285 |
|
|
movs pc, lr
|
| 286 |
|
|
|
| 287 |
|
|
/*
|
| 288 |
|
|
* Function: arm2_xchg_4 (int new, volatile void *ptr)
|
| 289 |
|
|
*
|
| 290 |
|
|
* Params : new New value to store at...
|
| 291 |
|
|
* : ptr pointer to word-wide location
|
| 292 |
|
|
*
|
| 293 |
|
|
* Purpose : Performs an exchange operation
|
| 294 |
|
|
*
|
| 295 |
|
|
* Returns : Original word data at 'ptr'
|
| 296 |
|
|
*
|
| 297 |
|
|
* Notes : This will have to be changed if we ever use multi-processing using these
|
| 298 |
|
|
* processors, but that is very unlikely...
|
| 299 |
|
|
*/
|
| 300 |
|
|
_arm2_xchg_4: mov r2, pc
|
| 301 |
|
|
orr r2, r2, #I_BIT
|
| 302 |
|
|
teqp r2, #0
|
| 303 |
|
|
ldr r2, [r1]
|
| 304 |
|
|
str r0, [r1]
|
| 305 |
|
|
mov r0, r2
|
| 306 |
|
|
/*
|
| 307 |
|
|
* fall through
|
| 308 |
|
|
*/
|
| 309 |
|
|
/*
|
| 310 |
|
|
* Function: arm2_proc_init (void)
|
| 311 |
|
|
* : arm2_proc_fin (void)
|
| 312 |
|
|
*
|
| 313 |
|
|
* Purpose : Initialise / finalise processor specifics (none required)
|
| 314 |
|
|
*/
|
| 315 |
|
|
_arm2_proc_init:
|
| 316 |
|
|
_arm2_proc_fin: movs pc, lr
|
| 317 |
|
|
/*
|
| 318 |
|
|
* Function: arm3_switch_to (struct task_struct *prev, struct task_struct *next)
|
| 319 |
|
|
*
|
| 320 |
|
|
* Params : prev Old task structure
|
| 321 |
|
|
* : next New task structure for process to run
|
| 322 |
|
|
*
|
| 323 |
|
|
* Purpose : Perform a task switch, saving the old processes state, and restoring
|
| 324 |
|
|
* the new.
|
| 325 |
|
|
*
|
| 326 |
|
|
* Notes : We don't fiddle with the FP registers here - we postpone this until
|
| 327 |
|
|
* the new task actually uses FP. This way, we don't swap FP for tasks
|
| 328 |
|
|
* that do not require it.
|
| 329 |
|
|
*/
|
| 330 |
|
|
_arm3_switch_to:
|
| 331 |
|
|
stmfd sp!, {r4 - r9, fp, lr} @ Store most regs on stack
|
| 332 |
|
|
str sp, [r0, #TSS_SAVE] @ Save sp_SVC
|
| 333 |
|
|
ldr r2, LC0
|
| 334 |
|
|
str r1, [r2]
|
| 335 |
|
|
ldr sp, [r1, #TSS_SAVE] @ Get saved sp_SVC
|
| 336 |
|
|
mov r4, r1
|
| 337 |
|
|
add r0, r1, #TSS_MEMCMAP @ Remap MEMC
|
| 338 |
|
|
ldr r1, LC0 + 4
|
| 339 |
|
|
ldr r1, [r1]
|
| 340 |
|
|
1: ldmia r0!, {r2, r3, r5, r6}
|
| 341 |
|
|
strb r2, [r2]
|
| 342 |
|
|
strb r3, [r3]
|
| 343 |
|
|
strb r5, [r5]
|
| 344 |
|
|
strb r6, [r6]
|
| 345 |
|
|
ldmia r0!, {r2, r3, r5, r6}
|
| 346 |
|
|
strb r2, [r2]
|
| 347 |
|
|
strb r3, [r3]
|
| 348 |
|
|
strb r5, [r5]
|
| 349 |
|
|
strb r6, [r6]
|
| 350 |
|
|
subs r1, r1, #8
|
| 351 |
|
|
bhi 1b
|
| 352 |
|
|
mcr p15, 0, r0, c1, c0, 0 @ flush cache
|
| 353 |
|
|
ldmfd sp!, {r4 - r9, fp, pc}^ @ Load all regs saved previously
|
| 354 |
|
|
/*
|
| 355 |
|
|
* Function: arm2_remap_memc (struct task_struct *tsk)
|
| 356 |
|
|
*
|
| 357 |
|
|
* Params : tsk Task structure specifing the new mapping structure
|
| 358 |
|
|
*
|
| 359 |
|
|
* Purpose : remap MEMC tables
|
| 360 |
|
|
*/
|
| 361 |
|
|
_arm3_remap_memc:
|
| 362 |
|
|
stmfd sp!, {lr}
|
| 363 |
|
|
add r0, r0, #TSS_MEMCMAP
|
| 364 |
|
|
ldr r1, LC0 + 4
|
| 365 |
|
|
ldr r1, [r1]
|
| 366 |
|
|
1: ldmia r0!, {r2, r3, ip, lr}
|
| 367 |
|
|
strb r2, [r2]
|
| 368 |
|
|
strb r3, [r3]
|
| 369 |
|
|
strb ip, [ip]
|
| 370 |
|
|
strb lr, [lr]
|
| 371 |
|
|
ldmia r0!, {r2, r3, ip, lr}
|
| 372 |
|
|
strb r2, [r2]
|
| 373 |
|
|
strb r3, [r3]
|
| 374 |
|
|
strb ip, [ip]
|
| 375 |
|
|
strb lr, [lr]
|
| 376 |
|
|
subs r1, r1, #8
|
| 377 |
|
|
bhi 1b
|
| 378 |
|
|
mcr p15, 0, r0, c1, c0, 0 @ flush cache
|
| 379 |
|
|
ldmfd sp!, {pc}^
|
| 380 |
|
|
|
| 381 |
|
|
/*
|
| 382 |
|
|
* Function: arm3_proc_init (void)
|
| 383 |
|
|
*
|
| 384 |
|
|
* Purpose : Initialise the cache control registers
|
| 385 |
|
|
*/
|
| 386 |
|
|
_arm3_proc_init:
|
| 387 |
|
|
mov r0, #0x001f0000
|
| 388 |
|
|
orr r0, r0, #0x0000ff00
|
| 389 |
|
|
orr r0, r0, #0x000000ff
|
| 390 |
|
|
mcr p15, 0, r0, c3, c0
|
| 391 |
|
|
mcr p15, 0, r0, c4, c0
|
| 392 |
|
|
mov r0, #0
|
| 393 |
|
|
mcr p15, 0, r0, c5, c0
|
| 394 |
|
|
mov r0, #3
|
| 395 |
|
|
mcr p15, 0, r0, c1, c0
|
| 396 |
|
|
mcr p15, 0, r0, c2, c0
|
| 397 |
|
|
movs pc, lr
|
| 398 |
|
|
|
| 399 |
|
|
/*
|
| 400 |
|
|
* Function: arm3_proc_fin (void)
|
| 401 |
|
|
*
|
| 402 |
|
|
* Purpose : Finalise processor (disable caches)
|
| 403 |
|
|
*/
|
| 404 |
|
|
_arm3_proc_fin: mov r0, #2
|
| 405 |
|
|
mcr p15, 0, r0, c2, c0
|
| 406 |
|
|
movs pc, lr
|
| 407 |
|
|
|
| 408 |
|
|
/*
|
| 409 |
|
|
* Function: arm3_xchg_1 (int new, volatile void *ptr)
|
| 410 |
|
|
*
|
| 411 |
|
|
* Params : new New value to store at...
|
| 412 |
|
|
* : ptr pointer to byte-wide location
|
| 413 |
|
|
*
|
| 414 |
|
|
* Purpose : Performs an exchange operation
|
| 415 |
|
|
*
|
| 416 |
|
|
* Returns : Original byte data at 'ptr'
|
| 417 |
|
|
*/
|
| 418 |
|
|
_arm3_xchg_1: swpb r0, r0, [r1]
|
| 419 |
|
|
movs pc, lr
|
| 420 |
|
|
|
| 421 |
|
|
/*
|
| 422 |
|
|
* Function: arm3_xchg_4 (int new, volatile void *ptr)
|
| 423 |
|
|
*
|
| 424 |
|
|
* Params : new New value to store at...
|
| 425 |
|
|
* : ptr pointer to word-wide location
|
| 426 |
|
|
*
|
| 427 |
|
|
* Purpose : Performs an exchange operation
|
| 428 |
|
|
*
|
| 429 |
|
|
* Returns : Original word data at 'ptr'
|
| 430 |
|
|
*/
|
| 431 |
|
|
_arm3_xchg_4: swp r0, r0, [r1]
|
| 432 |
|
|
movs pc, lr
|
| 433 |
|
|
|
| 434 |
|
|
|
| 435 |
|
|
/*
|
| 436 |
|
|
* Purpose : Function pointers used to access above functions - all calls
|
| 437 |
|
|
* come through these
|
| 438 |
|
|
*/
|
| 439 |
|
|
_arm2_name:
|
| 440 |
|
|
.ascii "arm2\0"
|
| 441 |
|
|
.align
|
| 442 |
|
|
|
| 443 |
|
|
.globl _arm2_processor_functions
|
| 444 |
|
|
_arm2_processor_functions:
|
| 445 |
|
|
.word _arm2_name @ 0
|
| 446 |
|
|
.word _arm2_switch_to @ 4
|
| 447 |
|
|
.word _arm2_3_data_abort @ 8
|
| 448 |
|
|
.word _arm2_3_check_bugs @ 12
|
| 449 |
|
|
.word _arm2_proc_init @ 16
|
| 450 |
|
|
.word _arm2_proc_fin @ 20
|
| 451 |
|
|
|
| 452 |
|
|
.word _arm2_remap_memc @ 24
|
| 453 |
|
|
.word _arm2_3_update_map @ 28
|
| 454 |
|
|
.word _arm2_3_update_cache @ 32
|
| 455 |
|
|
.word _arm2_xchg_1 @ 36
|
| 456 |
|
|
.word _abort @ 40
|
| 457 |
|
|
.word _arm2_xchg_4 @ 44
|
| 458 |
|
|
|
| 459 |
|
|
_arm250_name:
|
| 460 |
|
|
.ascii "arm250\0"
|
| 461 |
|
|
.align
|
| 462 |
|
|
|
| 463 |
|
|
.globl _arm250_processor_functions
|
| 464 |
|
|
_arm250_processor_functions:
|
| 465 |
|
|
.word _arm250_name @ 0
|
| 466 |
|
|
.word _arm2_switch_to @ 4
|
| 467 |
|
|
.word _arm2_3_data_abort @ 8
|
| 468 |
|
|
.word _arm2_3_check_bugs @ 12
|
| 469 |
|
|
.word _arm2_proc_init @ 16
|
| 470 |
|
|
.word _arm2_proc_fin @ 20
|
| 471 |
|
|
|
| 472 |
|
|
.word _arm2_remap_memc @ 24
|
| 473 |
|
|
.word _arm2_3_update_map @ 28
|
| 474 |
|
|
.word _arm2_3_update_cache @ 32
|
| 475 |
|
|
.word _arm3_xchg_1 @ 36
|
| 476 |
|
|
.word _abort @ 40
|
| 477 |
|
|
.word _arm3_xchg_4 @ 44
|
| 478 |
|
|
|
| 479 |
|
|
_arm3_name:
|
| 480 |
|
|
.ascii "arm3\0"
|
| 481 |
|
|
.align
|
| 482 |
|
|
|
| 483 |
|
|
.globl _arm3_processor_functions
|
| 484 |
|
|
_arm3_processor_functions:
|
| 485 |
|
|
.word _arm3_name @ 0
|
| 486 |
|
|
.word _arm3_switch_to @ 4
|
| 487 |
|
|
.word _arm2_3_data_abort @ 8
|
| 488 |
|
|
.word _arm2_3_check_bugs @ 12
|
| 489 |
|
|
.word _arm3_proc_init @ 16
|
| 490 |
|
|
.word _arm3_proc_fin @ 20
|
| 491 |
|
|
|
| 492 |
|
|
.word _arm3_remap_memc @ 24
|
| 493 |
|
|
.word _arm2_3_update_map @ 28
|
| 494 |
|
|
.word _arm2_3_update_cache @ 32
|
| 495 |
|
|
.word _arm3_xchg_1 @ 36
|
| 496 |
|
|
.word _abort @ 40
|
| 497 |
|
|
.word _arm3_xchg_4 @ 44
|
| 498 |
|
|
|
