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[/] [or1k_old/] [trunk/] [rc203soc/] [sw/] [uClinux/] [arch/] [armnommu/] [mm/] [proc-sa110.S] - Blame information for rev 1782

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1 1622 jcastillo
/*
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 * linux/arch/arm/mm/sa110.S: MMU functions for SA110
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 *
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 * (C) 1997 Russell King
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 *
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 * These are the low level assembler for performing cache and TLB
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 * functions on the sa110.
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 */
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#include 
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#include "../lib/constants.h"
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                .data
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Lclean_switch:  .long   0
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                .text
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17
/*
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 * Function: sa110_flush_cache_all (void)
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 *
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 * Purpose : Flush all cache lines
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 */
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                .align  5
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_sa110_flush_cache_all:                                 @ preserves r0
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                ldr     r3, =Lclean_switch
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                ldr     r2, [r3]
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                ands    r2, r2, #1
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                eor     r2, r2, #1
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                str     r2, [r3]
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                ldr     ip, =0xdf000000
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                addne   ip, ip, #32768
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                add     r1, ip, #16384                  @ only necessary for 16k
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1:              ldr     r2, [ip], #32
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                teq     r1, ip
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                bne     1b
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                mov     ip, #0
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                mcr     p15, 0, ip, c7, c5, 0           @ flush I cache
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                mcr     p15, 0, ip, c7, c10, 4          @ drain WB
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                mov     pc, lr
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40
/*
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 * Function: sa110_flush_cache_area (unsigned long address, int end, int flags)
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 *
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 * Params  : address    Area start address
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 *         : end        Area end address
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 *         : flags      b0 = I cache as well
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 *
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 * Purpose : clean & flush all cache lines associated with this area of memory
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 */
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                .align  5
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_sa110_flush_cache_area:
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                sub     r3, r1, r0
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                cmp     r3, #32768
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                bgt     _sa110_flush_cache_all
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1:              mcr     p15, 0, r0, c7, c10, 1          @ clean D entry
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                mcr     p15, 0, r0, c7, c6, 1           @ flush D entry
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                add     r0, r0, #32
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                mcr     p15, 0, r0, c7, c10, 1          @ clean D entry
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                mcr     p15, 0, r0, c7, c6, 1           @ flush D entry
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                add     r0, r0, #32
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                cmp     r0, r1
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                blt     1b
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                tst     r2, #1
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                movne   r0, #0
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                mcrne   p15, 0, r0, c7, c5, 0           @ flush I cache
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                mov     pc, lr
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67
/*
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 * Function: sa110_flush_cache_entry (unsigned long address)
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 *
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 * Params  : address    Address of cache line to flush
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 *
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 * Purpose : clean & flush an entry
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 */
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                .align  5
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_sa110_flush_cache_entry:
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                mov     r1, #0
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                mcr     p15, 0, r0, c7, c10, 1          @ clean D entry
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                mcr     p15, 0, r1, c7, c10, 4          @ drain WB
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                mcr     p15, 0, r1, c7, c5, 0           @ flush I cache
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                mov     pc, lr
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82
/*
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 * Function: sa110_flush_cache_pte (unsigned long address)
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 *
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 * Params  : address    Address of cache line to clean
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 *
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 * Purpose : Ensure that physical memory reflects cache at this location
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 *           for page table purposes.
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 */
90
_sa110_flush_cache_pte:
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                mcr     p15, 0, r0, c7, c10, 1          @ clean D entry  (drain is done by TLB fns)
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                mov     pc, lr
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94
/*
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 * Function: sa110_flush_ram_page (unsigned long page)
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 *
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 * Params  : address    Area start address
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 *         : size       size of area
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 *         : flags      b0 = I cache as well
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 *
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 * Purpose : clean & flush all cache lines associated with this area of memory
102
 */
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                .align  5
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_sa110_flush_ram_page:
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                mov     r1, #4096
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1:              mcr     p15, 0, r0, c7, c10, 1          @ clean D entry
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                mcr     p15, 0, r0, c7, c6, 1           @ flush D entry
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                add     r0, r0, #32
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                mcr     p15, 0, r0, c7, c10, 1          @ clean D entry
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                mcr     p15, 0, r0, c7, c6, 1           @ flush D entry
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                add     r0, r0, #32
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                subs    r1, r1, #64
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                bne     1b
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                mov     r0, #0
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                mcr     p15, 0, r0, c7, c10, 4          @ drain WB
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                mcr     p15, 0, r0, c7, c5, 0           @ flush I cache
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                mov     pc, lr
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119
/*
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 * Function: sa110_flush_tlb_all (void)
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 *
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 * Purpose : flush all TLB entries in all caches
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 */
124
                .align  5
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_sa110_flush_tlb_all:
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                mov     r0, #0
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                mcr     p15, 0, r0, c7, c10, 4          @ drain WB
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                mcr     p15, 0, r0, c8, c7, 0           @ flush I & D tlbs
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                mov     pc, lr
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131
/*
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 * Function: sa110_flush_tlb_area (unsigned long address, int end, int flags)
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 *
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 * Params  : address    Area start address
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 *         : end        Area end address
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 *         : flags      b0 = I cache as well
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 *
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 * Purpose : flush a TLB entry
139
 */
140
                .align  5
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_sa110_flush_tlb_area:
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                mov     r3, #0
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                mcr     p15, 0, r3, c7, c10, 4          @ drain WB
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1:              cmp     r0, r1
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                mcrlt   p15, 0, r0, c8, c6, 1           @ flush D TLB entry
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                addlt   r0, r0, #4096
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                cmp     r0, r1
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                mcrlt   p15, 0, r0, c8, c6, 1           @ flush D TLB entry
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                addlt   r0, r0, #4096
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                blt     1b
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                tst     r2, #1
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                mcrne   p15, 0, r3, c8, c5, 0           @ flush I TLB
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                mov     pc, lr
154
 
155
LC0:            .word   _current
156
/*
157
 * Function: sa110_switch_to (struct task_struct *prev, struct task_struct *next)
158
 *
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 * Params  : prev       Old task structure
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 *         : next       New task structure for process to run
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 *
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 * Purpose : Perform a task switch, saving the old processes state, and restoring
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 *           the new.
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 *
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 * Notes   : We don't fiddle with the FP registers here - we postpone this until
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 *           the new task actually uses FP.  This way, we don't swap FP for tasks
167
 *           that do not require it.
168
 */
169
                .align  5
170
_sa110_switch_to:
171
                stmfd   sp!, {r4 - r9, fp, lr}          @ Store most regs on stack
172
                mrs     ip, cpsr
173
                stmfd   sp!, {ip}                       @ Save cpsr_SVC
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                str     sp, [r0, #TSS_SAVE]             @ Save sp_SVC
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                ldr     r2, LC0
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                str     r1, [r2]
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                ldr     sp, [r1, #TSS_SAVE]             @ Get saved sp_SVC
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                ldr     r0, [r1, #TSS_MEMMAP]           @ Page table pointer
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                ldr     r3, =Lclean_switch
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                ldr     r2, [r3]
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                ands    r2, r2, #1
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                eor     r2, r2, #1
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                str     r2, [r3]
184
                ldr     r2, =0xdf000000
185
                addne   r2, r2, #32768
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                add     r1, r2, #16384                  @ only necessary for 16k
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1:              ldr     r3, [r2], #32
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                teq     r1, r2
189
                bne     1b
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                mov     r1, #0
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                mcr     p15, 0, r1, c7, c5, 0           @ flush I cache
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                mcr     p15, 0, r1, c7, c10, 4          @ drain WB
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                mcr     p15, 0, r0, c2, c0, 0           @ load page table pointer
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                mcr     p15, 0, r1, c8, c7, 0           @ flush TLBs
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                ldmfd   sp!, {ip}
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                msr     spsr, ip                        @ Save tasks CPSR into SPSR for this return
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                ldmfd   sp!, {r4 - r9, fp, pc}^         @ Load all regs saved previously
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/*
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 * Function: sa110_data_abort ()
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 *
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 * Params  : r0 = address of aborted instruction
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 *
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 * Purpose : obtain information about current aborted instruction
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 *
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 * Returns : r0 = address of abort
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 *         : r1 = FSR
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 *         : r2 != 0 if writing
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 */
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                .align  5
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_sa110_data_abort:
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                ldr     r2, [r0]                        @ read instruction causing problem
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                mrc     p15, 0, r0, c6, c0, 0           @ get FAR
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                mov     r2, r2, lsr #19                 @ b1 = L
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                and     r3, r2, #0x69 << 2
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                and     r2, r2, #2
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                teq     r3, #0x21 << 2
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                orreq   r2, r2, #1                      @ b1 = {LD,ST}RT
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                mrc     p15, 0, r1, c5, c0, 0           @ get FSR
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                and     r1, r1, #15
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                mov     pc, lr
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/*
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 * Function: sa110_set_pmd ()
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 *
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 * Params  : r0 = Address to set
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 *         : r1 = value to set
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 *
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 * Purpose : Set a PMD and flush it out of any WB cache
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 */
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                .align  5
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_sa110_set_pmd: str     r1, [r0]
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                mcr     p15, 0, r0, c7, c10, 1          @ clean D entry  (drain is done by TLB fns)
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                mov     pc, lr
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236
/*
237
 * Function: sa110_check_bugs (void)
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 *         : sa110_proc_init (void)
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 *         : sa110_proc_fin (void)
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 *
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 * Notes   : This processor does not require these
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 */
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_sa110_check_bugs:
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                mrs     ip, cpsr
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                bic     ip, ip, #F_BIT
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                msr     cpsr, ip
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_sa110_proc_init:
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_sa110_proc_fin:
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                mov     pc, lr
250
 
251
/*
252
 * Function: sa110_reset
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 *
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 * Notes   : This sets up everything for a reset
255
 */
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_sa110_reset:   mrs     r1, cpsr
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                orr     r1, r1, #F_BIT | I_BIT
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                msr     cpsr, r1
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                stmfd   sp!, {r1, lr}
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                bl      _sa110_flush_cache_all
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                bl      _sa110_flush_tlb_all
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                mcr     p15, 0, ip, c7, c7, 0           @ flush I,D caches
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                mrc     p15, 0, r0, c1, c0, 0           @ ctrl register
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                bic     r0, r0, #0x1800
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                bic     r0, r0, #0x000f
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                ldmfd   sp!, {r1, pc}
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/*
268
 * Purpose : Function pointers used to access above functions - all calls
269
 *           come through these
270
 */
271
_sa110_name:    .ascii  "sa110\0"
272
                .align
273
 
274
                .globl  _sa110_processor_functions
275
_sa110_processor_functions:
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                .word   _sa110_name                     @  0
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                .word   _sa110_switch_to                @  4
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                .word   _sa110_data_abort               @  8
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                .word   _sa110_check_bugs               @ 12
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                .word   _sa110_proc_init                @ 16
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                .word   _sa110_proc_fin                 @ 20
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                .word   _sa110_flush_cache_all          @ 24
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                .word   _sa110_flush_cache_area         @ 28
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                .word   _sa110_flush_cache_entry        @ 32
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                .word   _sa110_flush_cache_pte          @ 36
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                .word   _sa110_flush_ram_page           @ 40
288
                .word   _sa110_flush_tlb_all            @ 44
289
                .word   _sa110_flush_tlb_area           @ 48
290
 
291
                .word   _sa110_set_pmd                  @ 52
292
                .word   _sa110_reset                    @ 54

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