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[/] [or1k_old/] [trunk/] [rc203soc/] [sw/] [uClinux/] [arch/] [or32/] [board/] [reset.S] - Blame information for rev 1782

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Line No. Rev Author Line
1 1624 jcastillo 
#include
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#include
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#include
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#undef IC_ENABLE
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#define IC_ENABLE 1
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        .extern _reset_support
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        .extern _src_beg
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        .extern _dst_beg
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        .extern _dst_end
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        .extern _c_reset
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        .global start
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        .global _lolev_ie
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        .global _str
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        .section .stack
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        .space 0x30000
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_stack:
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        .section .reset, "a"
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        .org 0x100
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start:
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_reset:
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        l.addi  r3,r0,SPR_SR_SM
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        l.mtspr r0,r3,SPR_SR
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        l.movhi r3,hi(_start)
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        l.ori   r3,r3,lo(_start)
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        l.jr    r3
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        l.nop
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        .section .text
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_start:
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        l.jal   init_mc
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        l.nop
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.if IC_ENABLE
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        l.jal   _ic_enable
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        l.nop
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.endif
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        /* Copy form flash to sram */
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.if 1
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        l.movhi r3,hi(_src_beg)
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        l.ori   r3,r3,lo(_src_beg)
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        l.movhi r4,hi(_dst_beg)
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        l.ori   r4,r4,lo(_dst_beg)
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        l.movhi r5,hi(_dst_end)
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        l.ori   r5,r5,lo(_dst_end)
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        l.sub   r5,r5,r4
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        l.sfeqi r5,0
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        l.bf    2f
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        l.nop
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1:      l.lwz   r6,0(r3)
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        l.sw    0(r4),r6
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        l.addi  r3,r3,4
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        l.addi  r4,r4,4
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        l.addi  r5,r5,-4
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        l.sfgtsi r5,0
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        l.bf    1b
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        l.nop
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2:
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.endif
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        l.movhi r1,hi(_stack)
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        l.addi  r1,r1,lo(_stack)
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        l.addi  r1,r1,-4
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        l.movhi r3,hi(_linux_start)
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        l.ori   r3,r3,lo(_linux_start)
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        l.addi  r4,r0,0
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        l.jal   _decompress
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        l.nop
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        l.addi  r2,r0,0x100
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        l.jr    r2
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        l.addi  r2,r0,0
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init_mc:
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        l.movhi r3,hi(MC_BASE_ADD)
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        l.ori   r3,r3,lo(MC_BASE_ADD)
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        l.addi  r4,r3,MC_CSC(0)
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        l.movhi r5,hi(FLASH_BASE_ADD)
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        l.srai  r5,r5,5
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        l.ori   r5,r5,0x0025
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        l.sw    0(r4),r5
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        l.addi  r4,r3,MC_TMS(0)
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        l.movhi r5,hi(FLASH_TMS_VAL)
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        l.ori   r5,r5,lo(FLASH_TMS_VAL)
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        l.sw    0(r4),r5
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        l.addi  r4,r3,MC_BA_MASK
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        l.addi  r5,r0,MC_MASK_VAL
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        l.sw    0(r4),r5
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        l.addi  r4,r3,MC_CSR
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        l.movhi r5,hi(MC_CSR_VAL)
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        l.ori   r5,r5,lo(MC_CSR_VAL)
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        l.sw    0(r4),r5
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        l.addi  r4,r3,MC_TMS(1)
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        l.movhi r5,hi(SDRAM_TMS_VAL)
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        l.ori   r5,r5,lo(SDRAM_TMS_VAL)
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        l.sw    0(r4),r5
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        l.addi  r4,r3,MC_CSC(1)
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        l.movhi r5,hi(SDRAM_BASE_ADD)
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        l.srai  r5,r5,5
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        l.ori   r5,r5,0x0411
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        l.sw    0(r4),r5
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        l.jr    r9
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        l.nop
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_ic_enable:
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        /* Disable IC */
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        l.mfspr r13,r0,SPR_SR
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        l.addi  r11,r0,-1
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        l.xori  r11,r11,SPR_SR_ICE
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        l.and   r11,r13,r11
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        l.mtspr r0,r11,SPR_SR
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        /* Invalidate IC */
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        l.addi  r13,r0,0
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        l.addi  r11,r0,IC_SIZE
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1:
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        l.mtspr r0,r13,SPR_ICBIR
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        l.sfne  r13,r11
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        l.bf    1b
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        l.addi  r13,r13,IC_LINE
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        /* Enable IC */
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        l.mfspr r13,r0,SPR_SR
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        l.ori   r13,r13,SPR_SR_ICE
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        l.mtspr r0,r13,SPR_SR
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        l.nop
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        l.nop
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        l.nop
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        l.nop
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        l.nop
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        l.jr    r9
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        l.nop
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        .global __print
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__print:
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        l.lwz   r3,0(r1)
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        l.addi  r4,r1,4
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#       l.sys   202
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        l.nop 3
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        l.jr    r9
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        l.nop
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