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[/] [or1k_old/] [trunk/] [rc203soc/] [sw/] [uClinux/] [arch/] [or32/] [kernel/] [head.S] - Blame information for rev 1782

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Line No. Rev Author Line
1 1624 jcastillo 
#include
2 
#include
3 
#include
4 
#include
5 
#include
6 
 
7 
#define RAM 0
8 
#define TEMP_R_LOC 0x00000010
9 
 
10 
        .global __text_start
11 
        .global __main
12 
        .global ___bss_start
13 
        .global __bss_end
14 
        .global __ram_start
15 
        .global __ram_end
16 
        .global __rom_start
17 
        .global __rom_end
18 
        .global ___data_start
19 
        .global __data_end
20 
        .global ___data_rom_start
21 
 
22 
        .global splash_bits
23 
        .global __start
24 
        .global __stext
25 
 
26 
        .global __switch
27 
        .global _putc
28 
 
29 
#define SAVE_REGS(mark) \
30 
        l.addi  r1,r1,-(INT_FRAME_SIZE); \
31 
        l.mfspr r3,r0,SPR_EPCR_BASE; \
32 
        l.sw    PC(r1),r3; \
33 
        l.mfspr r3,r0,SPR_ESR_BASE; \
34 
        l.sw    SR(r1),r3; \
35 
        l.lwz   r3,(TEMP_R_LOC + 4)(r0); /* Read r1 (sp) from tmp location */ \
36 
        l.sw    SP(r1),r3; \
37 
        l.sw    GPR2(r1),r2; \
38 
        l.sw    GPR4(r1),r4; \
39 
        l.sw    GPR5(r1),r5; \
40 
        l.sw    GPR6(r1),r6; \
41 
        l.sw    GPR7(r1),r7; \
42 
        l.sw    GPR8(r1),r8; \
43 
        l.sw    GPR9(r1),r9; \
44 
        l.sw    GPR10(r1),r10; \
45 
        l.sw    GPR11(r1),r11; \
46 
        l.sw    GPR12(r1),r12; \
47 
        l.sw    GPR13(r1),r13; \
48 
        l.sw    GPR14(r1),r14; \
49 
        l.sw    GPR15(r1),r15; \
50 
        l.sw    GPR16(r1),r16; \
51 
        l.sw    GPR17(r1),r17; \
52 
        l.sw    GPR18(r1),r18; \
53 
        l.sw    GPR19(r1),r19; \
54 
        l.sw    GPR20(r1),r20; \
55 
        l.sw    GPR21(r1),r21; \
56 
        l.sw    GPR22(r1),r22; \
57 
        l.sw    GPR23(r1),r23; \
58 
        l.sw    GPR24(r1),r24; \
59 
        l.sw    GPR25(r1),r25; \
60 
        l.sw    GPR26(r1),r26; \
61 
        l.sw    GPR27(r1),r27; \
62 
        l.sw    GPR28(r1),r28; \
63 
        l.sw    GPR29(r1),r29; \
64 
        l.sw    GPR30(r1),r30; \
65 
        l.sw    GPR31(r1),r31; \
66 
        l.lwz   r3,(TEMP_R_LOC + 0)(r0);  /* Read r3 from tmp location */ \
67 
        l.sw    GPR3(r1),r3; \
68 
        l.sw    ORIG_GPR3(r1),r3; \
69 
        l.sw    RESULT(r1),r0
70 
 
71 
#define SAVE_INT_REGS(mark) \
72 
        l.sw    (TEMP_R_LOC + 4)(r0),r1;       /* Temporary store r1 to add 4!!! */ \
73 
        l.mfspr r3,r0,SPR_SR; \
74 
        l.addi  r1,r0,-1; \
75 
        l.xori  r1,r1,(SPR_SR_IEE | SPR_SR_TEE); \
76 
        l.and   r3,r3,r1; \
77 
        l.mtspr r0,r3,SPR_SR; \
78 
        l.lwz   r1,(TEMP_R_LOC + 4)(r0); \
79 
        l.mfspr r3,r0,SPR_ESR_BASE; /* Interrupt from user/system mode */ \
80 
        l.andi  r3,r3,SPR_SR_SM; \
81 
        l.sfeqi r3,SPR_SR_SM; \
82 
        l.bf    10f; /* SIMON */ /* Branch if SUPV */ \
83 
        l.nop; \
84 
        l.movhi r3,hi(_current_set); \
85 
        l.ori   r3,r3,lo(_current_set); \
86 
        l.lwz   r3,0(r3); \
87 
        l.sw    TSS+TSS_USP(r3),r1; \
88 
        l.mfspr r1,r0,SPR_EPCR_BASE; \
89 
        l.sw    TSS+TSS_PC(r3),r1; \
90 
        l.lwz   r1,TSS+TSS_KSP(r3); \
91 
        l.addi  r1,r1,-(INT_FRAME_SIZE); \
92 
        l.sw    TSS+TSS_REGS(r3),r1; \
93 
        l.lwz   r1,TSS+TSS_KSP(r3); \
94 
10:     SAVE_REGS(mark)
95 
 
96 
#define RETURN_FROM_INT(mark) \
97 
90:     l.addi  r4,r0,-1;       /* Disable interrupts */ \
98 
        l.xori  r4,r4,(SPR_SR_IEE | SPR_SR_TEE); \
99 
        l.mfspr r3,r0,SPR_SR; \
100 
        l.and   r3,r3,r4; \
101 
        l.mtspr r0,r3,SPR_SR; \
102 
        l.movhi r2,hi(_intr_count); \
103 
        l.ori   r2,r2,lo(_intr_count); \
104 
        l.lwz   r3,0(r2); \
105 
        l.sfeqi r3,0; \
106 
        l.bnf   00f; \
107 
        l.nop; \
108 
        l.movhi r4,hi(_bh_mask); \
109 
        l.ori   r4,r4,lo(_bh_mask); \
110 
        l.lwz   r4,0(r4); \
111 
        l.movhi r5,hi(_bh_active); \
112 
        l.ori   r5,r5,lo(_bh_active); \
113 
        l.lwz   r5,0(r5); \
114 
        l.and   r4,r4,r5; \
115 
        l.sfeqi r4,0; \
116 
        l.bf    00f; \
117 
        l.nop; \
118 
        l.addi  r3,r3,1; \
119 
        l.sw    0(r2),r3; \
120 
        l.jal   _do_bottom_half; \
121 
        l.nop; \
122 
        l.movhi r2,hi(_intr_count); \
123 
        l.ori   r2,r2,lo(_intr_count); \
124 
        l.lwz   r3,0(r2); \
125 
        l.addi  r3,r3,-1; \
126 
        l.sw    0(r2),r3; \
127 
00:     l.lwz   r2,SR(r1); \
128 
        l.andi  r3,r2,SPR_SR_SM; \
129 
        l.sfeqi r3,0; \
130 
        l.bnf   10f; /* SIMON */ /* Branch if SUPV */ \
131 
        l.nop; \
132 
        l.andi  r3,r2,SPR_SR_ICE; \
133 
        l.sfeqi r3,0; \
134 
        l.bf    05f; /* Branch if IC disabled */ \
135 
        l.nop; \
136 
        l.jal   _ic_invalidate; \
137 
        l.nop; \
138 
05:     l.movhi r3,hi(_current_set); /* need to save kernel stack pointer */ \
139 
        l.ori   r3,r3,lo(_current_set); \
140 
        l.lwz   r3,0(r3); \
141 
        l.addi  r4,r1,INT_FRAME_SIZE; \
142 
        l.sw    TSS+TSS_KSP(r3),r4; \
143 
        l.lwz   r4,STATE(r3); /* If state != 0, can't run */ \
144 
        l.sfeqi r4,0; \
145 
        l.bf    06f; \
146 
        l.nop; \
147 
        l.jal   _schedule; \
148 
        l.nop; \
149 
        l.j     90b; \
150 
        l.nop; \
151 
06:     l.lwz   r4,COUNTER(r3); \
152 
        l.sfeqi r4,0; \
153 
        l.bnf   07f; \
154 
        l.nop; \
155 
        l.jal   _schedule; \
156 
        l.nop; \
157 
        l.j     90b; \
158 
        l.nop; \
159 
07:     l.addi  r5,r0,-1; \
160 
        l.lwz   r4,BLOCKED(r3); /* Check for pending unblocked signals */ \
161 
        l.xor   r4,r4,r5; \
162 
        l.lwz   r5,SIGNAL(r3); \
163 
        l.and   r5,r5,r4; \
164 
        l.sfeqi r5,0; \
165 
        l.bf    10f; \
166 
        l.nop; \
167 
        l.addi  r3,r4,0; \
168 
        l.addi  r4,r1,0; \
169 
        l.jal   _do_signal; \
170 
        l.nop; \
171 
10:     l.lwz   r3,PC(r1); \
172 
        l.movhi r4,0x2; \
173 
        l.ori   r4,r4,0x6034;\
174 
        l.sfeq  r3,r4;\
175 
        l.bnf   20f; \
176 
        l.nop; \
177 
        l.lwz   r10,GPR10(r1); \
178 
        l.sfeqi r10,0; \
179 
        l.bnf   20f; \
180 
        l.nop; \
181 
        l.lwz   r4,SR(r1); \
182 
        l.andi  r4,r4,SPR_SR_F;\
183 
        l.sfeqi r4,0x00; \
184 
        l.bf    20f; \
185 
        l.nop; \
186 
        l.j     _fail; \
187 
        l.nop; \
188 
20:     l.mtspr r0,r3,SPR_EPCR_BASE; \
189 
        l.lwz   r3,SR(r1); \
190 
        l.mtspr r0,r3,SPR_ESR_BASE; \
191 
        l.lwz   r2,GPR2(r1); \
192 
        l.lwz   r3,GPR3(r1); \
193 
        l.lwz   r4,GPR4(r1); \
194 
        l.lwz   r5,GPR5(r1); \
195 
        l.lwz   r6,GPR6(r1); \
196 
        l.lwz   r7,GPR7(r1); \
197 
        l.lwz   r8,GPR8(r1); \
198 
        l.lwz   r9,GPR9(r1); \
199 
        l.lwz   r10,GPR10(r1); \
200 
        l.lwz   r11,GPR11(r1); \
201 
        l.lwz   r12,GPR12(r1); \
202 
        l.lwz   r13,GPR13(r1); \
203 
        l.lwz   r14,GPR14(r1); \
204 
        l.lwz   r15,GPR15(r1); \
205 
        l.lwz   r16,GPR16(r1); \
206 
        l.lwz   r17,GPR17(r1); \
207 
        l.lwz   r18,GPR18(r1); \
208 
        l.lwz   r19,GPR19(r1); \
209 
        l.lwz   r20,GPR20(r1); \
210 
        l.lwz   r21,GPR21(r1); \
211 
        l.lwz   r22,GPR22(r1); \
212 
        l.lwz   r23,GPR23(r1); \
213 
        l.lwz   r24,GPR24(r1); \
214 
        l.lwz   r25,GPR25(r1); \
215 
        l.lwz   r26,GPR26(r1); \
216 
        l.lwz   r27,GPR27(r1); \
217 
        l.lwz   r28,GPR28(r1); \
218 
        l.lwz   r29,GPR29(r1); \
219 
        l.lwz   r30,GPR30(r1); \
220 
        l.lwz   r31,GPR31(r1); \
221 
        l.addi  r1,r1,0; \
222 
        l.lwz   r1,SP(r1); \
223 
        l.rfe; \
224 
        l.nop
225 
 
226 
        .section .bss
227 
sys_stack:
228 
        .space  4*4096
229 
sys_stack_top:
230 
#if CONFIG_ROMKERNEL
231 
        .section .romvec, "ax",
232 
        .org    0x100
233 
 
234 
        l.movhi r3,hi(MC_BASE_ADD)
235 
        l.ori   r3,r3,MC_BA_MASK
236 
        l.addi  r5,r0,0x00
237 
        l.sw    0(r3),r5
238 
 
239 
        l.movhi r3,hi(__start)
240 
        l.ori   r3,r3,lo(__start)
241 
        l.jr    r3
242 
        l.nop
243 
 
244 
        .org    0x200
245 
 
246 
        l.nop
247 
        l.rfe
248 
        l.nop
249 
 
250 
        .org    0x300
251 
 
252 
        l.sw    (TEMP_R_LOC + 0)(r0),r3;       /* Temporary store r3 to add 0!!! */ \
253 
        l.movhi r3,hi(_dpfault)
254 
        l.ori   r3,r3,lo(_dpfault)
255 
        l.jr    r3
256 
        l.nop
257 
 
258 
        .org    0x400
259 
 
260 
        l.sw    (TEMP_R_LOC + 0)(r0),r3;       /* Temporary store r3 to add 0!!! */ \
261 
        l.movhi r3,hi(_ipfault)
262 
        l.ori   r3,r3,lo(_ipfault)
263 
        l.jr    r3
264 
        l.nop
265 
 
266 
        .org    0x500
267 
 
268 
        l.sw    (TEMP_R_LOC + 0)(r0),r3;       /* Temporary store r3 to add 0!!! */ \
269 
        l.movhi r3,hi(_tick)
270 
        l.ori   r3,r3,lo(_tick)
271 
        l.jr    r3
272 
        l.nop
273 
 
274 
        .org    0x600
275 
 
276 
        l.sw    (TEMP_R_LOC + 0)(r0),r3;       /* Temporary store r3 to add 0!!! */ \
277 
        l.movhi r3,hi(_align)
278 
        l.ori   r3,r3,lo(_align)
279 
        l.jr    r3
280 
        l.nop
281 
 
282 
        .org    0x800
283 
 
284 
        l.sw    (TEMP_R_LOC + 0)(r0),r3;       /* Temporary store r3 to add 0!!! */ \
285 
        l.movhi r3,hi(_ext_int)
286 
        l.ori   r3,r3,lo(_ext_int)
287 
        l.jr    r3
288 
        l.nop
289 
 
290 
        .org    0x900
291 
 
292 
        l.sw    (TEMP_R_LOC + 0)(r0),r3;       /* Temporary store r3 to add 0!!! */ \
293 
        l.movhi r3,hi(_dtlbmiss)
294 
        l.ori   r3,r3,lo(_dtlbmiss)
295 
        l.jr    r3
296 
        l.nop
297 
 
298 
        .org    0xa00
299 
 
300 
        l.sw    (TEMP_R_LOC + 0)(r0),r3;       /* Temporary store r3 to add 0!!! */ \
301 
        l.movhi r3,hi(_itlbmiss)
302 
        l.ori   r3,r3,lo(_itlbmiss)
303 
        l.jr    r3
304 
        l.nop
305 
 
306 
        .org    0xb00
307 
 
308 
        l.sw    (TEMP_R_LOC + 0)(r0),r3;       /* Temporary store r3 to add 0!!! */ \
309 
        l.movhi r3,hi(_sys_call)
310 
        l.ori   r3,r3,lo(_sys_call)
311 
        l.jr    r3
312 
        l.nop
313 
 
314 
        .org    0xc00
315 
 
316 
        l.sw    (TEMP_R_LOC + 0)(r0),r3;       /* Temporary store r3 to add 0!!! */ \
317 
        l.movhi r3,hi(_sys_call)
318 
        l.ori   r3,r3,lo(_sys_call)
319 
        l.jr    r3
320 
        l.nop
321 
#endif
322 
        .section .ramvec, "ax"
323 
        .org    0x100
324 
 
325 
        l.movhi r3,hi(__start)
326 
        l.ori   r3,r3,lo(__start)
327 
        l.jr    r3
328 
        l.nop
329 
 
330 
        .org    0x200
331 
 
332 
        l.sw    (TEMP_R_LOC + 0)(r0),r3;       /* Temporary store r3 to add 0!!! */ \
333 
        l.movhi r3,hi(_trap_200)
334 
        l.ori   r3,r3,lo(_trap_200)
335 
        l.jr    r3
336 
        l.nop
337 
 
338 
        .org    0x300
339 
 
340 
        l.sw    (TEMP_R_LOC + 0)(r0),r3;       /* Temporary store r3 to add 0!!! */ \
341 
        l.movhi r3,hi(_trap_300)
342 
        l.ori   r3,r3,lo(_trap_300)
343 
        l.jr    r3
344 
        l.nop
345 
 
346 
        .org    0x400
347 
 
348 
        l.sw    (TEMP_R_LOC + 0)(r0),r3;       /* Temporary store r3 to add 0!!! */ \
349 
        l.movhi r3,hi(_trap_400)
350 
        l.ori   r3,r3,lo(_trap_400)
351 
        l.jr    r3
352 
        l.nop
353 
 
354 
        .org    0x500
355 
 
356 
        l.sw    (TEMP_R_LOC + 0)(r0),r3;       /* Temporary store r3 to add 0!!! */ \
357 
        l.movhi r3,hi(_tick)
358 
        l.ori   r3,r3,lo(_tick)
359 
        l.jr    r3
360 
        l.nop
361 
 
362 
        .org    0x600
363 
 
364 
        l.sw    (TEMP_R_LOC + 0)(r0),r3;       /* Temporary store r3 to add 0!!! */ \
365 
        l.movhi r3,hi(_align)
366 
        l.ori   r3,r3,lo(_align)
367 
        l.jr    r3
368 
        l.nop
369 
 
370 
        .org    0x700
371 
 
372 
        l.sw    (TEMP_R_LOC + 0)(r0),r3;       /* Temporary store r3 to add 0!!! */ \
373 
        l.movhi r3,hi(_trap_700)
374 
        l.ori   r3,r3,lo(_trap_700)
375 
        l.jr    r3
376 
        l.nop
377 
 
378 
        .org    0x800
379 
 
380 
        l.sw    (TEMP_R_LOC + 0)(r0),r3;       /* Temporary store r3 to add 0!!! */ \
381 
        l.movhi r3,hi(_ext_int)
382 
        l.ori   r3,r3,lo(_ext_int)
383 
        l.jr    r3
384 
        l.nop
385 
 
386 
        .org    0x900
387 
 
388 
        l.sw    (TEMP_R_LOC + 0)(r0),r3;       /* Temporary store r3 to add 0!!! */ \
389 
        l.movhi r3,hi(_trap_900)
390 
        l.ori   r3,r3,lo(_trap_900)
391 
        l.jr    r3
392 
        l.nop
393 
 
394 
        .org    0xa00
395 
 
396 
        l.sw    (TEMP_R_LOC + 0)(r0),r3;       /* Temporary store r3 to add 0!!! */ \
397 
        l.movhi r3,hi(_trap_a00)
398 
        l.ori   r3,r3,lo(_trap_a00)
399 
        l.jr    r3
400 
        l.nop
401 
 
402 
        .org    0xb00
403 
 
404 
        l.sw    (TEMP_R_LOC + 0)(r0),r3;       /* Temporary store r3 to add 0!!! */ \
405 
        l.movhi r3,hi(_trap_b00)
406 
        l.ori   r3,r3,lo(_trap_b00)
407 
        l.jr    r3
408 
        l.nop
409 
 
410 
        .org    0xc00
411 
 
412 
        l.sw    (TEMP_R_LOC + 0)(r0),r3;       /* Temporary store r3 to add 0!!! */ \
413 
        l.movhi r3,hi(_sys_call)
414 
        l.ori   r3,r3,lo(_sys_call)
415 
        l.jr    r3
416 
        l.nop
417 
 
418 
 
419 
        .text
420 
__start:
421 
__stext:
422 
        l.addi  r3,r0,SPR_SR_SM
423 
        l.mtspr r0,r3,SPR_SR
424 
#if 1
425 
 
426 
        /* Init uart */
427 
        l.jal   _ua_init
428 
        l.nop
429 
 
430 
        /* Jump to flash original location */
431 
        l.movhi r3,hi(__flsh_start)
432 
        l.ori   r3,r3,lo(__flsh_start)
433 
        l.jr    r3
434 
        l.nop
435 
 
436 
__flsh_start:
437 
 
438 
#if CONFIG_ROMKERNEL
439 
#if MC_INIT
440 
        l.movhi r3,hi(MC_BASE_ADD)
441 
        l.ori   r3,r3,lo(MC_BASE_ADD)
442 
 
443 
        l.addi  r4,r3,MC_CSC(0)
444 
        l.movhi r5,hi(FLASH_BASE_ADD)
445 
        l.srai  r5,r5,6
446 
        l.ori   r5,r5,0x0025
447 
        l.sw    0(r4),r5
448 
 
449 
        l.addi  r4,r3,MC_TMS(0)
450 
        l.movhi r5,hi(FLASH_TMS_VAL)
451 
        l.ori   r5,r5,lo(FLASH_TMS_VAL)
452 
        l.sw    0(r4),r5
453 
 
454 
        l.addi  r4,r3,MC_BA_MASK
455 
        l.addi  r5,r0,MC_MASK_VAL
456 
        l.sw    0(r4),r5
457 
 
458 
        l.addi  r4,r3,MC_CSR
459 
        l.movhi r5,hi(MC_CSR_VAL)
460 
        l.ori   r5,r5,lo(MC_CSR_VAL)
461 
        l.sw    0(r4),r5
462 
 
463 
        l.addi  r4,r3,MC_TMS(1)
464 
        l.movhi r5,hi(SDRAM_TMS_VAL)
465 
        l.ori   r5,r5,lo(SDRAM_TMS_VAL)
466 
        l.sw    0(r4),r5
467 
 
468 
        l.addi  r4,r3,MC_CSC(1)
469 
        l.movhi r5,hi(SDRAM_BASE_ADD)
470 
        l.srai  r5,r5,6
471 
        l.ori   r5,r5,0x0411
472 
        l.sw    0(r4),r5
473 
 
474 
#ifdef FBMEM_BASE_ADD
475 
        l.addi  r4,r3,MC_CSC(2)
476 
        l.movhi r5,hi(FBMEM_BASE_ADD)
477 
        l.srai  r5,r5,6
478 
        l.ori   r5,r5,0x0005
479 
        l.sw    0(r4),r5
480 
 
481 
        l.addi  r4,r3,MC_TMS(2)
482 
        l.movhi r5,0xffff
483 
        l.ori   r5,r5,0xffff
484 
        l.sw    0(r4),r5
485 
#endif
486 
#endif
487 
#endif
488 
#endif
489 
 
490 
#if ICACHE
491 
        l.jal   _ic_enable
492 
        l.nop
493 
#endif
494 
 
495 
#if DCACHE
496 
        l.jal   _dc_enable
497 
        l.nop
498 
#endif
499 
 
500 
        l.movhi r1, hi(sys_stack_top)           /* stack setup */
501 
        l.ori   r1,r1,lo(sys_stack_top)
502 
 
503 
#if CONFIG_ROMKERNEL
504 
        /* Copy data segment from ROM to RAM */
505 
        l.movhi r3, hi(___data_rom_start)
506 
        l.ori   r3,r3,lo(___data_rom_start)
507 
 
508 
        l.movhi r4, hi(___data_start)
509 
        l.ori   r4,r4,lo(___data_start)
510 
 
511 
        l.movhi r5, hi(__data_end)
512 
        l.ori   r5,r5,lo(__data_end)
513 
 
514 
        /* Copy %r3 to %r4 until %r4 == %r5 */
515 
1:
516 
        l.sfeq  r3,r4
517 
        l.bf    3f
518 
        l.nop
519 
2:
520 
        l.sfgeu r4,r5
521 
        l.bf    1f
522 
        l.nop
523 
        l.lwz   r8,0(r3)
524 
        l.sw    0(r4),r8
525 
        l.addi  r3,r3,4
526 
        l.j     2b
527 
        l.addi  r4,r4,4
528 
 
529 
        /* Copy ramvec segment from ROM to RAM */
530 
1:
531 
        l.movhi r4, hi(__ramvec_start)
532 
        l.ori   r4,r4,lo(__ramvec_start)
533 
 
534 
        l.movhi r5, hi(__ramvec_end)
535 
        l.ori   r5,r5,lo(__ramvec_end)
536 
 
537 
        /* Copy %r3 to %r4 until %r4 == %r5 */
538 
2:
539 
        l.sfgeu r4,r5
540 
        l.bf    1f
541 
        l.nop
542 
        l.lwz   r8,0(r3)
543 
        l.sw    0(r4),r8
544 
        l.addi  r3,r3,4
545 
        l.j     2b
546 
        l.addi  r4,r4,4
547 
#if 0
548 
        /* Copy initrd segment from ROM to RAM */
549 
1:
550 
        l.movhi r4, hi(__initrd_start)
551 
        l.ori   r4,r4,lo(__initrd_start)
552 
 
553 
        l.movhi r5, hi(__initrd_end)
554 
        l.ori   r5,r5,lo(__initrd_end)
555 
 
556 
        /* Copy %r3 to %r4 until %r4 == %r5 */
557 
2:
558 
        l.sfgeu r4,r5
559 
        l.bf    1f
560 
        l.nop
561 
        l.lwz   r8,0(r3)
562 
        l.sw    0(r4),r8
563 
        l.addi  r3,r3,4
564 
        l.j     2b
565 
        l.addi  r4,r4,4
566 
#endif
567 
#endif
568 
1:
569 
3:
570 
        l.movhi r3, hi(___bss_start)
571 
        l.ori   r3,r3,lo(___bss_start)
572 
 
573 
        l.movhi r4, hi(end)
574 
        l.ori   r4,r4,lo(end)
575 
 
576 
        /* Copy 0 to %r3 until %r3 == %r4 */
577 
1:
578 
        l.sfgeu r3,r4
579 
        l.bf    1f
580 
        l.nop
581 
        l.sw    0(r3),r0
582 
        l.j     1b
583 
        l.addi  r3,r3,4
584 
1:
585 
 
586 
#if IMMU
587 
        l.jal   _immu_enable
588 
        l.nop
589 
#endif
590 
 
591 
#if DMMU
592 
        l.jal   _dmmu_enable
593 
        l.nop
594 
#endif
595 
 
596 
        l.j     _start_kernel
597 
        l.nop
598 
 
599 
_exit:
600 
        l.j     _exit
601 
        l.nop
602 
 
603 
_dpfault:
604 
 
605 
 
606 
_ipfault:
607 
 
608 
_tick:
609 
        SAVE_INT_REGS(0x0500)
610 
        l.lwz   r3,0(r1)
611 
        l.movhi r4,0x2
612 
        l.ori   r4,r4,0x6034
613 
        l.sfeq  r3,r4
614 
        l.bnf   1f
615 
        l.nop
616 
        l.sfeqi r10,0x00
617 
        l.bnf   1f
618 
        l.nop
619 
        l.lwz   r3,0xc(r0)
620 
        l.addi  r3,r3,1
621 
        l.sw    0xc(r0),r3
622 
        l.lwz   r3,4(r1)
623 
        l.andi  r3,r3,SPR_SR_F
624 
        l.sfeqi r3,0x00
625 
        l.bnf   _fail
626 
        l.nop
627 
1:
628 
        l.addi  r3,r1,0
629 
        l.jal   _timer_interrupt
630 
        l.nop
631 
 
632 
        RETURN_FROM_INT(0x500)
633 
 
634 
_fail:
635 
        l.j   _fail
636 
        l.nop
637 
 
638 
_align:
639 
        l.addi  r1,r1,-128
640 
        l.sw    0x08(r1),r2
641 
        l.lwz   r3,(TEMP_R_LOC + 0)(r0)
642 
        l.sw    0x0c(r1),r3
643 
        l.sw    0x10(r1),r4
644 
        l.sw    0x14(r1),r5
645 
        l.sw    0x18(r1),r6
646 
        l.sw    0x1c(r1),r7
647 
        l.sw    0x20(r1),r8
648 
        l.sw    0x24(r1),r9
649 
        l.sw    0x28(r1),r10
650 
        l.sw    0x2c(r1),r11
651 
        l.sw    0x30(r1),r12
652 
        l.sw    0x34(r1),r13
653 
        l.sw    0x38(r1),r14
654 
        l.sw    0x3c(r1),r15
655 
        l.sw    0x40(r1),r16
656 
        l.sw    0x44(r1),r17
657 
        l.sw    0x48(r1),r18
658 
        l.sw    0x4c(r1),r19
659 
        l.sw    0x50(r1),r20
660 
        l.sw    0x54(r1),r21
661 
        l.sw    0x58(r1),r22
662 
        l.sw    0x5c(r1),r23
663 
        l.sw    0x60(r1),r24
664 
        l.sw    0x64(r1),r25
665 
        l.sw    0x68(r1),r26
666 
        l.sw    0x6c(r1),r27
667 
        l.sw    0x70(r1),r28
668 
        l.sw    0x74(r1),r29
669 
        l.sw    0x78(r1),r30
670 
        l.sw    0x7c(r1),r31
671 
 
672 
        l.mfspr r2,r0,SPR_EEAR_BASE     /* Load the efective addres */
673 
        l.mfspr r5,r0,SPR_EPCR_BASE     /* Load the insn address */
674 
 
675 
        l.lwz   r3,0(r5)                /* Load insn */
676 
        l.srli  r4,r3,26                /* Shift left to get the insn opcode */
677 
 
678 
        l.sfeqi r4,0x00                 /* Check if the load/store insn is in delay slot */
679 
        l.bf    jmp
680 
        l.sfeqi r4,0x01
681 
        l.bf    jmp
682 
        l.sfeqi r4,0x03
683 
        l.bf    jmp
684 
        l.sfeqi r4,0x04
685 
        l.bf    jmp
686 
        l.sfeqi r4,0x11
687 
        l.bf    jr
688 
        l.sfeqi r4,0x12
689 
        l.bf    jr
690 
        l.nop
691 
        l.j     1f
692 
        l.addi  r5,r5,4                 /* Increment PC to get return insn address */
693 
 
694 
jmp:
695 
        l.slli  r4,r3,6                 /* Get the signed extended jump length */
696 
        l.srai  r4,r4,4
697 
 
698 
        l.lwz   r3,4(r5)                /* Load the real load/store insn */
699 
 
700 
        l.add   r5,r5,r4                /* Calculate jump target address */
701 
 
702 
        l.j     1f
703 
        l.srli  r4,r3,26                /* Shift left to get the insn opcode */
704 
 
705 
jr:
706 
        l.slli  r4,r3,9                 /* Shift to get the reg nb */
707 
        l.andi  r4,r4,0x7c
708 
 
709 
        l.lwz   r3,4(r5)                /* Load the real load/store insn */
710 
 
711 
        l.add   r4,r4,r1                /* Load the jump register value from the stack */
712 
        l.lwz   r5,0(r4)
713 
 
714 
        l.srli  r4,r3,26                /* Shift left to get the insn opcode */
715 
 
716 
 
717 
1:      l.mtspr r0,r5,SPR_EPCR_BASE
718 
 
719 
        l.sfeqi r4,0x26
720 
        l.bf    lhs
721 
        l.sfeqi r4,0x25
722 
        l.bf    lhz
723 
        l.sfeqi r4,0x22
724 
        l.bf    lws
725 
        l.sfeqi r4,0x21
726 
        l.bf    lwz
727 
        l.sfeqi r4,0x37
728 
        l.bf    sh
729 
        l.sfeqi r4,0x35
730 
        l.bf    sw
731 
        l.nop
732 
 
733 
1:      l.j     1b                      /* I don't know what to do */
734 
        l.nop
735 
 
736 
lhs:    l.lbs   r5,0(r2)
737 
        l.slli  r5,r5,8
738 
        l.lbz   r6,1(r2)
739 
        l.or    r5,r5,r6
740 
        l.srli  r4,r3,19
741 
        l.andi  r4,r4,0x7c
742 
        l.add   r4,r4,r1
743 
        l.j     align_end
744 
        l.sw    0(r4),r5
745 
 
746 
lhz:    l.lbz   r5,0(r2)
747 
        l.slli  r5,r5,8
748 
        l.lbz   r6,1(r2)
749 
        l.or    r5,r5,r6
750 
        l.srli  r4,r3,19
751 
        l.andi  r4,r4,0x7c
752 
        l.add   r4,r4,r1
753 
        l.j     align_end
754 
        l.sw    0(r4),r5
755 
 
756 
lws:    l.lbs   r5,0(r2)
757 
        l.slli  r5,r5,24
758 
        l.lbz   r6,1(r2)
759 
        l.slli  r6,r6,16
760 
        l.or    r5,r5,r6
761 
        l.lbz   r6,2(r2)
762 
        l.slli  r6,r6,8
763 
        l.or    r5,r5,r6
764 
        l.lbz   r6,3(r2)
765 
        l.or    r5,r5,r6
766 
        l.srli  r4,r3,19
767 
        l.andi  r4,r4,0x7c
768 
        l.add   r4,r4,r1
769 
        l.j     align_end
770 
        l.sw    0(r4),r5
771 
 
772 
lwz:    l.lbz   r5,0(r2)
773 
        l.slli  r5,r5,24
774 
        l.lbz   r6,1(r2)
775 
        l.slli  r6,r6,16
776 
        l.or    r5,r5,r6
777 
        l.lbz   r6,2(r2)
778 
        l.slli  r6,r6,8
779 
        l.or    r5,r5,r6
780 
        l.lbz   r6,3(r2)
781 
        l.or    r5,r5,r6
782 
        l.srli  r4,r3,19
783 
        l.andi  r4,r4,0x7c
784 
        l.add   r4,r4,r1
785 
        l.j     align_end
786 
        l.sw    0(r4),r5
787 
 
788 
sh:
789 
        l.srli  r4,r3,9
790 
        l.andi  r4,r4,0x7c
791 
        l.add   r4,r4,r1
792 
        l.lwz   r5,0(r4)
793 
        l.sb    1(r2),r5
794 
        l.srli  r5,r5,8
795 
        l.j     align_end
796 
        l.sb    0(r2),r5
797 
 
798 
sw:
799 
        l.srli  r4,r3,9
800 
        l.andi  r4,r4,0x7c
801 
        l.add   r4,r4,r1
802 
        l.lwz   r5,0(r4)
803 
        l.sb    3(r2),r5
804 
        l.srli  r5,r5,8
805 
        l.sb    2(r2),r5
806 
        l.srli  r5,r5,8
807 
        l.sb    1(r2),r5
808 
        l.srli  r5,r5,8
809 
        l.j     align_end
810 
        l.sb    0(r2),r5
811 
 
812 
align_end:
813 
        l.lwz   r2,0x08(r1)
814 
        l.lwz   r3,0x0c(r1)
815 
        l.lwz   r4,0x10(r1)
816 
        l.lwz   r5,0x14(r1)
817 
        l.lwz   r6,0x18(r1)
818 
        l.lwz   r7,0x1c(r1)
819 
        l.lwz   r8,0x20(r1)
820 
        l.lwz   r9,0x24(r1)
821 
        l.lwz   r10,0x28(r1)
822 
        l.lwz   r11,0x2c(r1)
823 
        l.lwz   r12,0x30(r1)
824 
        l.lwz   r13,0x34(r1)
825 
        l.lwz   r14,0x38(r1)
826 
        l.lwz   r15,0x3c(r1)
827 
        l.lwz   r16,0x40(r1)
828 
        l.lwz   r17,0x44(r1)
829 
        l.lwz   r18,0x48(r1)
830 
        l.lwz   r19,0x4c(r1)
831 
        l.lwz   r20,0x50(r1)
832 
        l.lwz   r21,0x54(r1)
833 
        l.lwz   r22,0x58(r1)
834 
        l.lwz   r23,0x5c(r1)
835 
        l.lwz   r24,0x60(r1)
836 
        l.lwz   r25,0x64(r1)
837 
        l.lwz   r26,0x68(r1)
838 
        l.lwz   r27,0x6c(r1)
839 
        l.lwz   r28,0x70(r1)
840 
        l.lwz   r29,0x74(r1)
841 
        l.lwz   r30,0x78(r1)
842 
        l.lwz   r31,0x7c(r1)
843 
        l.addi  r1,r1,128
844 
        l.rfe
845 
 
846 
 
847 
_ext_int:
848 
        SAVE_INT_REGS(0x0800)
849 
        l.lwz   r3,0(r1)
850 
        l.movhi r4,0x2
851 
        l.ori   r4,r4,0x6034
852 
        l.sfeq  r3,r4
853 
        l.bnf   1f
854 
        l.nop
855 
        l.lwz   r3,0xc(r0)
856 
        l.addi  r3,r3,1
857 
        l.sw    0xc(r0),r3
858 
        l.sfeqi r10,0x00
859 
        l.bf    _fail
860 
        l.nop
861 
1:
862 
        l.addi  r3,r1,0
863 
        l.jal   _handle_IRQ
864 
        l.nop
865 
        RETURN_FROM_INT(0x800)
866 
 
867 
_dtlbmiss:
868 
        l.sw    (TEMP_R_LOC + 4)(r0),r4
869 
        l.sw    (TEMP_R_LOC + 8)(r0),r5
870 
        l.mfspr r3,r0,SPR_EEAR_BASE
871 
        l.srli  r4,r3,DMMU_PAGE_ADD_BITS
872 
        l.andi  r4,r4,DMMU_SET_ADD_MASK
873 
        l.addi  r5,r0,-1
874 
        l.xori  r5,r5,DMMU_PAGE_ADD_MASK
875 
        l.and   r5,r3,r5
876 
        l.ori   r5,r5,SPR_DTLBMR_V
877 
        l.mtspr r4,r5,SPR_DTLBMR_BASE(0)
878 
        l.movhi r5,hi(SPR_DTLBTR_PPN)
879 
        l.ori   r5,r5,lo(SPR_DTLBTR_PPN)
880 
        l.and   r5,r3,r5
881 
        l.ori   r5,r5,DTLBTR_NO_LIMIT
882 
        l.movhi r3,0x8000
883 
        l.sfgeu r5,r3
884 
        l.bnf   1f
885 
        l.nop
886 
        l.ori   r5,r5,SPR_DTLBTR_CI
887 
1:      l.mtspr r4,r5,SPR_DTLBTR_BASE(0)
888 
        l.lwz   r3,(TEMP_R_LOC + 0)(r0)
889 
        l.lwz   r4,(TEMP_R_LOC + 4)(r0)
890 
        l.lwz   r5,(TEMP_R_LOC + 8)(r0)
891 
        l.rfe
892 
        l.nop
893 
 
894 
 
895 
_itlbmiss:
896 
        l.sw    (TEMP_R_LOC + 4)(r0),r4
897 
        l.sw    (TEMP_R_LOC + 8)(r0),r5
898 
        l.mfspr r3,r0,SPR_EEAR_BASE
899 
        l.srli  r4,r3,IMMU_PAGE_ADD_BITS
900 
        l.andi  r4,r4,IMMU_SET_ADD_MASK
901 
        l.addi  r5,r0,-1
902 
        l.xori  r5,r5,IMMU_PAGE_ADD_MASK
903 
        l.and   r5,r3,r5
904 
        l.ori   r5,r5,SPR_ITLBMR_V
905 
        l.mtspr r4,r5,SPR_ITLBMR_BASE(0)
906 
        l.movhi r5,hi(SPR_ITLBTR_PPN)
907 
        l.ori   r5,r5,lo(SPR_ITLBTR_PPN)
908 
        l.and   r5,r3,r5
909 
        l.ori   r5,r5,ITLBTR_NO_LIMIT
910 
        l.mtspr r4,r5,SPR_ITLBTR_BASE(0)
911 
        l.lwz   r3,(TEMP_R_LOC + 0)(r0)
912 
        l.lwz   r4,(TEMP_R_LOC + 4)(r0)
913 
        l.lwz   r5,(TEMP_R_LOC + 8)(r0)
914 
        l.rfe
915 
        l.nop
916 
 
917 
_sys_call:
918 
        SAVE_INT_REGS(0x0c00)
919 
        /* EPCR was pointing to l.sys instruction, we have to incremet it */
920 
/*      l.lwz   r2,PC(r1)
921 
        l.addi  r2,r2,4
922 
        l.sw    PC(r1),r2
923 
*/
924 
        l.sfeqi r11,0x7777              /* Special case for 'sys_sigreturn' */
925 
        l.bnf   10f
926 
        l.nop
927 
        l.jal   _sys_sigreturn
928 
        l.addi  r3,r1,0
929 
        l.sfgtsi r11,0                  /* Check for restarted system call */
930 
        l.bf    99f
931 
        l.nop
932 
        l.j     20f
933 
        l.nop
934 
10:
935 
        l.movhi r2,hi(_sys_call_table)
936 
        l.ori   r2,r2,lo(_sys_call_table)
937 
        l.slli  r11,r11,2
938 
        l.add   r2,r2,r11
939 
        l.lwz   r2,0(r2)
940 
        l.addi  r8,r1,0                 /* regs pointer */
941 
        l.jalr  r2
942 
        l.nop
943 
        l.sw    GPR11(r1),r11           /* save return value */
944 
20:
945 
        l.sw    RESULT(r1),r11          /* save result */
946 
        l.sfgesi r11,0
947 
        l.bf    99f
948 
        l.nop
949 
        l.sfeqi r11,-ERESTARTNOHAND
950 
        l.bnf   22f
951 
        l.nop
952 
        l.addi  r11,r0,EINTR
953 
22:
954 
        l.sw    RESULT(r1),r11
955 
99:
956 
        RETURN_FROM_INT(0xc00)
957 
 
958 
/*
959 
 * This routine switches between two different tasks.  The process
960 
 * state of one is saved on its kernel stack.  Then the state
961 
 * of the other is restored from its kernel stack.  The memory
962 
 * management hardware is updated to the second process's state.
963 
 * Finally, we can return to the second process, via the 'return'.
964 
 *
965 
 * Note: there are two ways to get to the "going out" portion
966 
 * of this code; either by coming in via the entry (_switch)
967 
 * or via "fork" which must set up an environment equivalent
968 
 * to the "_switch" path.  If you change this (or in particular, the
969 
 * SAVE_REGS macro), you'll have to change the fork code also.
970 
 */
971 
__switch:
972 
        l.sw    (TEMP_R_LOC + 0)(r0),r3 /* Temporary store r3 to add 0!!! */
973 
        l.sw    (TEMP_R_LOC + 4)(r0),r1 /* Temporary store r1 to add 4!!! */
974 
        l.mtspr r0,r9,SPR_EPCR_BASE     /* Link register to EPCR */
975 
        l.mfspr r3,r0,SPR_SR            /* From SR to ESR */
976 
        l.mtspr r0,r3,SPR_ESR_BASE
977 
        SAVE_REGS(0x0FF0)
978 
        l.sw    TSS_KSP(r3),r1          /* Set old stack pointer */
979 
        l.lwz   r1,TSS_KSP(r4)          /* Load new stack pointer */
980 
        RETURN_FROM_INT(0xFF0)
981 
 
982 
_ua_init:
983 
        l.movhi r3,hi(UART_BASE_ADD)
984 
 
985 
        l.addi  r4,r0,0x7
986 
        l.sb    0x2(r3),r4
987 
 
988 
        l.addi  r4,r0,0x0
989 
        l.sb    0x1(r3),r4
990 
 
991 
        l.addi  r4,r0,0x3
992 
        l.sb    0x3(r3),r4
993 
 
994 
        l.lbz   r5,3(r3)
995 
        l.ori   r4,r5,0x80
996 
        l.sb    0x3(r3),r4
997 
        l.addi  r4,r0,((UART_DEVISOR>>8) & 0x000000ff)
998 
        l.sb    UART_DLM(r3),r4
999 
        l.addi  r4,r0,((UART_DEVISOR) & 0x000000ff)
1000 
        l.sb    UART_DLL(r3),r4
1001 
        l.sb    0x3(r3),r5
1002 
 
1003 
        l.jr    r9
1004 
        l.nop
1005 
 
1006 
_putc:
1007 
        l.movhi r4,hi(UART_BASE_ADD)
1008 
 
1009 
        l.addi  r6,r0,0x20
1010 
1:      l.lbz   r5,5(r4)
1011 
        l.andi  r5,r5,0x20
1012 
        l.sfeq  r5,r6
1013 
        l.bnf   1b
1014 
        l.nop
1015 
 
1016 
        l.sb    0(r4),r3
1017 
 
1018 
        l.addi  r6,r0,0x60
1019 
1:      l.lbz   r5,5(r4)
1020 
        l.andi  r5,r5,0x60
1021 
        l.sfeq  r5,r6
1022 
        l.bnf   1b
1023 
        l.nop
1024 
 
1025 
        l.jr    r9
1026 
        l.nop
1027 
 
1028 
 
1029 
_trap_200:
1030 
        l.nop
1031 
        l.nop
1032 
.word   0x21000001
1033 
1:      l.j     1b
1034 
        l.nop
1035 
 
1036 
_trap_300:
1037 
        l.nop
1038 
        l.nop
1039 
.word   0x21000001
1040 
1:      l.j     1b
1041 
        l.nop
1042 
 
1043 
_trap_400:
1044 
        l.nop
1045 
        l.nop
1046 
.word   0x21000001
1047 
1:      l.j     1b
1048 
        l.nop
1049 
 
1050 
_trap_700:
1051 
        l.nop
1052 
        l.nop
1053 
.word   0x21000001
1054 
1:      l.j     1b
1055 
        l.nop
1056 
 
1057 
_trap_900:
1058 
        l.nop
1059 
        l.nop
1060 
.word   0x21000001
1061 
1:      l.j     1b
1062 
        l.nop
1063 
 
1064 
_trap_a00:
1065 
        l.nop
1066 
        l.nop
1067 
.word   0x21000001
1068 
1:      l.j     1b
1069 
        l.nop
1070 
 
1071 
_trap_b00:
1072 
        l.nop
1073 
        l.nop
1074 
.word   0x21000001
1075 
1:      l.j     1b
1076 
        l.nop
1077 
 
1078 
        .data
1079 
env:
1080 
        .long   0

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