URL https://opencores.org/ocsvn/or1k_old/or1k_old/trunk

Subversion Repositories or1k_old

[/] [or1k_old/] [trunk/] [rc203soc/] [sw/] [uClinux/] [include/] [asm-armnommu/] [arch-a5k/] [io.h] - Blame information for rev 1782

Details | Compare with Previous | View Log


/*
 * linux/include/asm-arm/arch-a5k/io.h
 *
 * Copyright (C) 1997 Russell King
 *
 * Modifications:
 *  06-Dec-1997 RMK     Created.
 */
#ifndef __ASM_ARM_ARCH_IO_H
#define __ASM_ARM_ARCH_IO_H
 
/*
 * This architecture does not require any delayed IO, and
 * has the constant-optimised IO
 */
#undef  ARCH_IO_DELAY
 
/*
 * We use two different types of addressing - PC style addresses, and ARM
 * addresses.  PC style accesses the PC hardware with the normal PC IO
 * addresses, eg 0x3f8 for serial#1.  ARM addresses are 0x80000000+
 * and are translated to the start of IO.  Note that all addresses are
 * shifted left!
 */
#define __PORT_PCIO(x)  (!((x) & 0x80000000))
 
/*
 * Dynamic IO functions - let the compiler
 * optimize the expressions
 */
extern __inline__ void __outb (unsigned int value, unsigned int port)
{
        unsigned long temp;
        __asm__ __volatile__(
        "tst    %2, #0x80000000\n\t"
        "mov    %0, %4\n\t"
        "addeq  %0, %0, %3\n\t"
        "strb   %1, [%0, %2, lsl #2]"
        : "=&r" (temp)
        : "r" (value), "r" (port), "Ir" (PCIO_BASE - IO_BASE), "Ir" (IO_BASE)
        : "cc");
}
 
extern __inline__ void __outw (unsigned int value, unsigned int port)
{
        unsigned long temp;
        __asm__ __volatile__(
        "tst    %2, #0x80000000\n\t"
        "mov    %0, %4\n\t"
        "addeq  %0, %0, %3\n\t"
        "str    %1, [%0, %2, lsl #2]"
        : "=&r" (temp)
        : "r" (value|value<<16), "r" (port), "Ir" (PCIO_BASE - IO_BASE), "Ir" (IO_BASE)
        : "cc");
}
 
extern __inline__ void __outl (unsigned int value, unsigned int port)
{
        unsigned long temp;
        __asm__ __volatile__(
        "tst    %2, #0x80000000\n\t"
        "mov    %0, %4\n\t"
        "addeq  %0, %0, %3\n\t"
        "str    %1, [%0, %2, lsl #2]"
        : "=&r" (temp)
        : "r" (value), "r" (port), "Ir" (PCIO_BASE - IO_BASE), "Ir" (IO_BASE)
        : "cc");
}
 
#define DECLARE_DYN_IN(sz,fnsuffix,instr)                                       \
extern __inline__ unsigned sz __in##fnsuffix (unsigned int port)                \
{                                                                               \
        unsigned long temp, value;                                              \
        __asm__ __volatile__(                                                   \
        "tst    %2, #0x80000000\n\t"                                            \
        "mov    %0, %4\n\t"                                                     \
        "addeq  %0, %0, %3\n\t"                                                 \
        "ldr" ##instr## "       %1, [%0, %2, lsl #2]"                           \
        : "=&r" (temp), "=r" (value)                                            \
        : "r" (port), "Ir" (PCIO_BASE - IO_BASE), "Ir" (IO_BASE)                \
        : "cc");                                                                \
        return (unsigned sz)value;                                              \
}
 
extern __inline__ unsigned int __ioaddr (unsigned int port)                     \
{                                                                               \
        if (__PORT_PCIO(port))                                                  \
                return (unsigned int)(PCIO_BASE + (port << 2));                 \
        else                                                                    \
                return (unsigned int)(IO_BASE + (port << 2));                   \
}
 
DECLARE_DYN_IN(char,b,"b")
DECLARE_DYN_IN(short,w,"")
DECLARE_DYN_IN(long,l,"")
 
#undef DECLARE_DYN_IN
 
/*
 * Constant address IO functions
 *
 * These have to be macros for the 'J' constraint to work -
 * +/-4096 immediate operand.
 */
#define __outbc(value,port)                                                     \
({                                                                              \
        if (__PORT_PCIO((port)))                                                \
                __asm__ __volatile__(                                           \
                "strb   %0, [%1, %2]"                                           \
                : : "r" (value), "r" (PCIO_BASE), "Jr" ((port) << 2));          \
        else                                                                    \
                __asm__ __volatile__(                                           \
                "strb   %0, [%1, %2]"                                           \
                : : "r" (value), "r" (IO_BASE), "r" ((port) << 2));             \
})
 
#define __inbc(port)                                                            \
({                                                                              \
        unsigned char result;                                                   \
        if (__PORT_PCIO((port)))                                                \
                __asm__ __volatile__(                                           \
                "ldrb   %0, [%1, %2]"                                           \
                : "=r" (result) : "r" (PCIO_BASE), "Jr" ((port) << 2));         \
        else                                                                    \
                __asm__ __volatile__(                                           \
                "ldrb   %0, [%1, %2]"                                           \
                : "=r" (result) : "r" (IO_BASE), "r" ((port) << 2));            \
        result;                                                                 \
})
 
#define __outwc(value,port)                                                     \
({                                                                              \
        unsigned long v = value;                                                \
        if (__PORT_PCIO((port)))                                                \
                __asm__ __volatile__(                                           \
                "str    %0, [%1, %2]"                                           \
                : : "r" (v|v<<16), "r" (PCIO_BASE), "Jr" ((port) << 2));        \
        else                                                                    \
                __asm__ __volatile__(                                           \
                "str    %0, [%1, %2]"                                           \
                : : "r" (v|v<<16), "r" (IO_BASE), "r" ((port) << 2));           \
})
 
#define __inwc(port)                                                            \
({                                                                              \
        unsigned short result;                                                  \
        if (__PORT_PCIO((port)))                                                \
                __asm__ __volatile__(                                           \
                "ldr    %0, [%1, %2]"                                           \
                : "=r" (result) : "r" (PCIO_BASE), "Jr" ((port) << 2));         \
        else                                                                    \
                __asm__ __volatile__(                                           \
                "ldr    %0, [%1, %2]"                                           \
                : "=r" (result) : "r" (IO_BASE), "r" ((port) << 2));            \
        result & 0xffff;                                                        \
})
 
#define __outlc(v,p) __outwc((v),(p))
 
#define __inlc(port)                                                            \
({                                                                              \
        unsigned long result;                                                   \
        if (__PORT_PCIO((port)))                                                \
                __asm__ __volatile__(                                           \
                "ldr    %0, [%1, %2]"                                           \
                : "=r" (result) : "r" (PCIO_BASE), "Jr" ((port) << 2));         \
        else                                                                    \
                __asm__ __volatile__(                                           \
                "ldr    %0, [%1, %2]"                                           \
                : "=r" (result) : "r" (IO_BASE), "r" ((port) << 2));            \
        result;                                                                 \
})
 
#define __ioaddrc(port)                                                         \
({                                                                              \
        unsigned long addr;                                                     \
        if (__PORT_PCIO((port)))                                                \
                addr = PCIO_BASE + ((port) << 2);                               \
        else                                                                    \
                addr = IO_BASE + ((port) << 2);                                 \
        addr;                                                                   \
})
 
/*
 * Translated address IO functions
 *
 * IO address has already been translated to a virtual address
 */
#define outb_t(v,p)                                                             \
        (*(volatile unsigned char *)(p) = (v))
 
#define inb_t(p)                                                                \
        (*(volatile unsigned char *)(p))
 
#define outl_t(v,p)                                                             \
        (*(volatile unsigned long *)(p) = (v))
 
#define inl_t(p)                                                                \
        (*(volatile unsigned long *)(p))
 
#endif

Browse

Tools

Subversion Repositories or1k_old

[/] [or1k_old/] [trunk/] [rc203soc/] [sw/] [uClinux/] [include/] [asm-armnommu/] [arch-a5k/] [io.h] - Blame information for rev 1782

Line No.	Rev	Author	Line
1	1633	jcastillo	`/*`
2			`* linux/include/asm-arm/arch-a5k/io.h`
3			`*`
4			`* Copyright (C) 1997 Russell King`
5			`*`
6			`* Modifications:`
7			`* 06-Dec-1997 RMK Created.`
8			`*/`
9			`#ifndef __ASM_ARM_ARCH_IO_H`
10			`#define __ASM_ARM_ARCH_IO_H`
11
12			`/*`
13			`* This architecture does not require any delayed IO, and`
14			`* has the constant-optimised IO`
15			`*/`
16			`#undef ARCH_IO_DELAY`
17
18			`/*`
19			`* We use two different types of addressing - PC style addresses, and ARM`
20			`* addresses. PC style accesses the PC hardware with the normal PC IO`
21			`* addresses, eg 0x3f8 for serial#1. ARM addresses are 0x80000000+`
22			`* and are translated to the start of IO. Note that all addresses are`
23			`* shifted left!`
24			`*/`
25			`#define __PORT_PCIO(x) (!((x) & 0x80000000))`
26
27			`/*`
28			`* Dynamic IO functions - let the compiler`
29			`* optimize the expressions`
30			`*/`
31			`extern __inline__ void __outb (unsigned int value, unsigned int port)`
32			`{`
33			`unsigned long temp;`
34			`__asm__ __volatile__(`
35			`"tst %2, #0x80000000\n\t"`
36			`"mov %0, %4\n\t"`
37			`"addeq %0, %0, %3\n\t"`
38			`"strb %1, [%0, %2, lsl #2]"`
39			`: "=&r" (temp)`
40			`: "r" (value), "r" (port), "Ir" (PCIO_BASE - IO_BASE), "Ir" (IO_BASE)`
41			`: "cc");`
42			`}`
43
44			`extern __inline__ void __outw (unsigned int value, unsigned int port)`
45			`{`
46			`unsigned long temp;`
47			`__asm__ __volatile__(`
48			`"tst %2, #0x80000000\n\t"`
49			`"mov %0, %4\n\t"`
50			`"addeq %0, %0, %3\n\t"`
51			`"str %1, [%0, %2, lsl #2]"`
52			`: "=&r" (temp)`
53			`: "r" (value\|value<<16), "r" (port), "Ir" (PCIO_BASE - IO_BASE), "Ir" (IO_BASE)`
54			`: "cc");`
55			`}`
56
57			`extern __inline__ void __outl (unsigned int value, unsigned int port)`
58			`{`
59			`unsigned long temp;`
60			`__asm__ __volatile__(`
61			`"tst %2, #0x80000000\n\t"`
62			`"mov %0, %4\n\t"`
63			`"addeq %0, %0, %3\n\t"`
64			`"str %1, [%0, %2, lsl #2]"`
65			`: "=&r" (temp)`
66			`: "r" (value), "r" (port), "Ir" (PCIO_BASE - IO_BASE), "Ir" (IO_BASE)`
67			`: "cc");`
68			`}`
69
70			`#define DECLARE_DYN_IN(sz,fnsuffix,instr) \`
71			`extern __inline__ unsigned sz __in##fnsuffix (unsigned int port) \`
72			`{ \`
73			`unsigned long temp, value; \`
74			`__asm__ __volatile__( \`
75			`"tst %2, #0x80000000\n\t" \`
76			`"mov %0, %4\n\t" \`
77			`"addeq %0, %0, %3\n\t" \`
78			`"ldr" ##instr## " %1, [%0, %2, lsl #2]" \`
79			`: "=&r" (temp), "=r" (value) \`
80			`: "r" (port), "Ir" (PCIO_BASE - IO_BASE), "Ir" (IO_BASE) \`
81			`: "cc"); \`
82			`return (unsigned sz)value; \`
83			`}`
84
85			`extern __inline__ unsigned int __ioaddr (unsigned int port) \`
86			`{ \`
87			`if (__PORT_PCIO(port)) \`
88			`return (unsigned int)(PCIO_BASE + (port << 2)); \`
89			`else \`
90			`return (unsigned int)(IO_BASE + (port << 2)); \`
91			`}`
92
93			`DECLARE_DYN_IN(char,b,"b")`
94			`DECLARE_DYN_IN(short,w,"")`
95			`DECLARE_DYN_IN(long,l,"")`
96
97			`#undef DECLARE_DYN_IN`
98
99			`/*`
100			`* Constant address IO functions`
101			`*`
102			`* These have to be macros for the 'J' constraint to work -`
103			`* +/-4096 immediate operand.`
104			`*/`
105			`#define __outbc(value,port) \`
106			`({ \`
107			`if (__PORT_PCIO((port))) \`
108			`__asm__ __volatile__( \`
109			`"strb %0, [%1, %2]" \`
110			`: : "r" (value), "r" (PCIO_BASE), "Jr" ((port) << 2)); \`
111			`else \`
112			`__asm__ __volatile__( \`
113			`"strb %0, [%1, %2]" \`
114			`: : "r" (value), "r" (IO_BASE), "r" ((port) << 2)); \`
115			`})`
116
117			`#define __inbc(port) \`
118			`({ \`
119			`unsigned char result; \`
120			`if (__PORT_PCIO((port))) \`
121			`__asm__ __volatile__( \`
122			`"ldrb %0, [%1, %2]" \`
123			`: "=r" (result) : "r" (PCIO_BASE), "Jr" ((port) << 2)); \`
124			`else \`
125			`__asm__ __volatile__( \`
126			`"ldrb %0, [%1, %2]" \`
127			`: "=r" (result) : "r" (IO_BASE), "r" ((port) << 2)); \`
128			`result; \`
129			`})`
130
131			`#define __outwc(value,port) \`
132			`({ \`
133			`unsigned long v = value; \`
134			`if (__PORT_PCIO((port))) \`
135			`__asm__ __volatile__( \`
136			`"str %0, [%1, %2]" \`
137			`: : "r" (v\|v<<16), "r" (PCIO_BASE), "Jr" ((port) << 2)); \`
138			`else \`
139			`__asm__ __volatile__( \`
140			`"str %0, [%1, %2]" \`
141			`: : "r" (v\|v<<16), "r" (IO_BASE), "r" ((port) << 2)); \`
142			`})`
143
144			`#define __inwc(port) \`
145			`({ \`
146			`unsigned short result; \`
147			`if (__PORT_PCIO((port))) \`
148			`__asm__ __volatile__( \`
149			`"ldr %0, [%1, %2]" \`
150			`: "=r" (result) : "r" (PCIO_BASE), "Jr" ((port) << 2)); \`
151			`else \`
152			`__asm__ __volatile__( \`
153			`"ldr %0, [%1, %2]" \`
154			`: "=r" (result) : "r" (IO_BASE), "r" ((port) << 2)); \`
155			`result & 0xffff; \`
156			`})`
157
158			`#define __outlc(v,p) __outwc((v),(p))`
159
160			`#define __inlc(port) \`
161			`({ \`
162			`unsigned long result; \`
163			`if (__PORT_PCIO((port))) \`
164			`__asm__ __volatile__( \`
165			`"ldr %0, [%1, %2]" \`
166			`: "=r" (result) : "r" (PCIO_BASE), "Jr" ((port) << 2)); \`
167			`else \`
168			`__asm__ __volatile__( \`
169			`"ldr %0, [%1, %2]" \`
170			`: "=r" (result) : "r" (IO_BASE), "r" ((port) << 2)); \`
171			`result; \`
172			`})`
173
174			`#define __ioaddrc(port) \`
175			`({ \`
176			`unsigned long addr; \`
177			`if (__PORT_PCIO((port))) \`
178			`addr = PCIO_BASE + ((port) << 2); \`
179			`else \`
180			`addr = IO_BASE + ((port) << 2); \`
181			`addr; \`
182			`})`
183
184			`/*`
185			`* Translated address IO functions`
186			`*`
187			`* IO address has already been translated to a virtual address`
188			`*/`
189			`#define outb_t(v,p) \`
190			`((volatile unsigned char )(p) = (v))`
191
192			`#define inb_t(p) \`
193			`((volatile unsigned char )(p))`
194
195			`#define outl_t(v,p) \`
196			`((volatile unsigned long )(p) = (v))`
197
198			`#define inl_t(p) \`
199			`((volatile unsigned long )(p))`
200
201			`#endif`