OpenCores
URL https://opencores.org/ocsvn/or1k_old/or1k_old/trunk

Subversion Repositories or1k_old

[/] [or1k_old/] [trunk/] [rc203soc/] [sw/] [uClinux/] [include/] [asm-armnommu/] [hardware.h] - Blame information for rev 1765

Go to most recent revision | Details | Compare with Previous | View Log

Line No. Rev Author Line
1 1633 jcastillo
/*
2
 * linux/include/asm-arm/hardware.h
3
 *
4
 * Copyright (C) 1996 Russell King
5
 *
6
 * Common hardware definitions
7
 */
8
 
9
#ifndef __ASM_HARDWARE_H
10
#define __ASM_HARDWARE_H
11
 
12
#include <asm/arch/hardware.h>
13
 
14
/*
15
 * Use these macros to read/write the IOC.  All it does is perform the actual
16
 * read/write.
17
 */
18
#ifdef HAS_IOC
19
#ifndef __ASSEMBLER__
20
#define __IOC(offset)   (IO_IOC_BASE + (offset >> 2))
21
#else
22
#define __IOC(offset)   offset
23
#endif
24
 
25
#define IOC_CONTROL     __IOC(0x00)
26
#define IOC_KARTTX      __IOC(0x04)
27
#define IOC_KARTRX      __IOC(0x04)
28
 
29
#define IOC_IRQSTATA    __IOC(0x10)
30
#define IOC_IRQREQA     __IOC(0x14)
31
#define IOC_IRQCLRA     __IOC(0x14)
32
#define IOC_IRQMASKA    __IOC(0x18)
33
 
34
#define IOC_IRQSTATB    __IOC(0x20)
35
#define IOC_IRQREQB     __IOC(0x24)
36
#define IOC_IRQMASKB    __IOC(0x28)
37
 
38
#define IOC_FIQSTAT     __IOC(0x30)
39
#define IOC_FIQREQ      __IOC(0x34)
40
#define IOC_FIQMASK     __IOC(0x38)
41
 
42
#define IOC_T0CNTL      __IOC(0x40)
43
#define IOC_T0LTCHL     __IOC(0x40)
44
#define IOC_T0CNTH      __IOC(0x44)
45
#define IOC_T0LTCHH     __IOC(0x44)
46
#define IOC_T0GO        __IOC(0x48)
47
#define IOC_T0LATCH     __IOC(0x4c)
48
 
49
#define IOC_T1CNTL      __IOC(0x50)
50
#define IOC_T1LTCHL     __IOC(0x50)
51
#define IOC_T1CNTH      __IOC(0x54)
52
#define IOC_T1LTCHH     __IOC(0x54)
53
#define IOC_T1GO        __IOC(0x58)
54
#define IOC_T1LATCH     __IOC(0x5c)
55
 
56
#define IOC_T2CNTL      __IOC(0x60)
57
#define IOC_T2LTCHL     __IOC(0x60)
58
#define IOC_T2CNTH      __IOC(0x64)
59
#define IOC_T2LTCHH     __IOC(0x64)
60
#define IOC_T2GO        __IOC(0x68)
61
#define IOC_T2LATCH     __IOC(0x6c)
62
 
63
#define IOC_T3CNTL      __IOC(0x70)
64
#define IOC_T3LTCHL     __IOC(0x70)
65
#define IOC_T3CNTH      __IOC(0x74)
66
#define IOC_T3LTCHH     __IOC(0x74)
67
#define IOC_T3GO        __IOC(0x78)
68
#define IOC_T3LATCH     __IOC(0x7c)
69
#endif
70
 
71
#ifdef HAS_MEMC
72
#define VDMA_ALIGNMENT  PAGE_SIZE
73
#define VDMA_XFERSIZE   16
74
#define VDMA_INIT       0
75
#define VDMA_START      1
76
#define VDMA_END        2
77
 
78
#define video_set_dma(start,end,offset)                         \
79
do {                                                            \
80
        memc_write (VDMA_START, (start >> 2));                  \
81
        memc_write (VDMA_END, (end - VDMA_XFERSIZE) >> 2);      \
82
        memc_write (VDMA_INIT, (offset >> 2));                  \
83
} while (0)
84
#endif
85
 
86
#ifdef HAS_IOMD
87
#ifndef __ASSEMBLER__
88
#define __IOMD(offset)  (IO_IOMD_BASE + (offset >> 2))
89
#else
90
#define __IOMD(offset)  offset
91
#endif
92
 
93
#define IOMD_CONTROL    __IOMD(0x000)
94
#define IOMD_KARTTX     __IOMD(0x004)
95
#define IOMD_KARTRX     __IOMD(0x004)
96
#define IOMD_KCTRL      __IOMD(0x008)
97
 
98
#define IOMD_IRQSTATA   __IOMD(0x010)
99
#define IOMD_IRQREQA    __IOMD(0x014)
100
#define IOMD_IRQCLRA    __IOMD(0x014)
101
#define IOMD_IRQMASKA   __IOMD(0x018)
102
 
103
#define IOMD_IRQSTATB   __IOMD(0x020)
104
#define IOMD_IRQREQB    __IOMD(0x024)
105
#define IOMD_IRQMASKB   __IOMD(0x028)
106
 
107
#define IOMD_FIQSTAT    __IOMD(0x030)
108
#define IOMD_FIQREQ     __IOMD(0x034)
109
#define IOMD_FIQMASK    __IOMD(0x038)
110
 
111
#define IOMD_T0CNTL     __IOMD(0x040)
112
#define IOMD_T0LTCHL    __IOMD(0x040)
113
#define IOMD_T0CNTH     __IOMD(0x044)
114
#define IOMD_T0LTCHH    __IOMD(0x044)
115
#define IOMD_T0GO       __IOMD(0x048)
116
#define IOMD_T0LATCH    __IOMD(0x04c)
117
 
118
#define IOMD_T1CNTL     __IOMD(0x050)
119
#define IOMD_T1LTCHL    __IOMD(0x050)
120
#define IOMD_T1CNTH     __IOMD(0x054)
121
#define IOMD_T1LTCHH    __IOMD(0x054)
122
#define IOMD_T1GO       __IOMD(0x058)
123
#define IOMD_T1LATCH    __IOMD(0x05c)
124
 
125
#define IOMD_ROMCR0     __IOMD(0x080)
126
#define IOMD_ROMCR1     __IOMD(0x084)
127
#define IOMD_DRAMCR     __IOMD(0x088)
128
#define IOMD_VREFCR     __IOMD(0x08C)
129
 
130
#define IOMD_FSIZE      __IOMD(0x090)
131
#define IOMD_ID0        __IOMD(0x094)
132
#define IOMD_ID1        __IOMD(0x098)
133
#define IOMD_VERSION    __IOMD(0x09C)
134
 
135
#define IOMD_MOUSEX     __IOMD(0x0A0)
136
#define IOMD_MOUSEY     __IOMD(0x0A4)
137
 
138
#define IOMD_DMATCR     __IOMD(0x0C0)
139
#define IOMD_IOTCR      __IOMD(0x0C4)
140
#define IOMD_ECTCR      __IOMD(0x0C8)
141
#define IOMD_DMAEXT     __IOMD(0x0CC)
142
 
143
#define DMA_EXT_IO0     1
144
#define DMA_EXT_IO1     2
145
#define DMA_EXT_IO2     4
146
#define DMA_EXT_IO3     8
147
 
148
#define IOMD_IO0CURA    __IOMD(0x100)
149
#define IOMD_IO0ENDA    __IOMD(0x104)
150
#define IOMD_IO0CURB    __IOMD(0x108)
151
#define IOMD_IO0ENDB    __IOMD(0x10C)
152
#define IOMD_IO0CR      __IOMD(0x110)
153
#define IOMD_IO0ST      __IOMD(0x114)
154
 
155
#define IOMD_IO1CURA    __IOMD(0x120)
156
#define IOMD_IO1ENDA    __IOMD(0x124)
157
#define IOMD_IO1CURB    __IOMD(0x128)
158
#define IOMD_IO1ENDB    __IOMD(0x12C)
159
#define IOMD_IO1CR      __IOMD(0x130)
160
#define IOMD_IO1ST      __IOMD(0x134)
161
 
162
#define IOMD_IO2CURA    __IOMD(0x140)
163
#define IOMD_IO2ENDA    __IOMD(0x144)
164
#define IOMD_IO2CURB    __IOMD(0x148)
165
#define IOMD_IO2ENDB    __IOMD(0x14C)
166
#define IOMD_IO2CR      __IOMD(0x150)
167
#define IOMD_IO2ST      __IOMD(0x154)
168
 
169
#define IOMD_IO3CURA    __IOMD(0x160)
170
#define IOMD_IO3ENDA    __IOMD(0x164)
171
#define IOMD_IO3CURB    __IOMD(0x168)
172
#define IOMD_IO3ENDB    __IOMD(0x16C)
173
#define IOMD_IO3CR      __IOMD(0x170)
174
#define IOMD_IO3ST      __IOMD(0x174)
175
 
176
#define IOMD_SD0CURA    __IOMD(0x180)
177
#define IOMD_SD0ENDA    __IOMD(0x184)
178
#define IOMD_SD0CURB    __IOMD(0x188)
179
#define IOMD_SD0ENDB    __IOMD(0x18C)
180
#define IOMD_SD0CR      __IOMD(0x190)
181
#define IOMD_SD0ST      __IOMD(0x194)
182
 
183
#define IOMD_SD1CURA    __IOMD(0x1A0)
184
#define IOMD_SD1ENDA    __IOMD(0x1A4)
185
#define IOMD_SD1CURB    __IOMD(0x1A8)
186
#define IOMD_SD1ENDB    __IOMD(0x1AC)
187
#define IOMD_SD1CR      __IOMD(0x1B0)
188
#define IOMD_SD1ST      __IOMD(0x1B4)
189
 
190
#define IOMD_CURSCUR    __IOMD(0x1C0)
191
#define IOMD_CURSINIT   __IOMD(0x1C4)
192
 
193
#define IOMD_VIDCUR     __IOMD(0x1D0)
194
#define IOMD_VIDEND     __IOMD(0x1D4)
195
#define IOMD_VIDSTART   __IOMD(0x1D8)
196
#define IOMD_VIDINIT    __IOMD(0x1DC)
197
#define IOMD_VIDCR      __IOMD(0x1E0)
198
 
199
#define IOMD_DMASTAT    __IOMD(0x1F0)
200
#define IOMD_DMAREQ     __IOMD(0x1F4)
201
#define IOMD_DMAMASK    __IOMD(0x1F8)
202
 
203
#define DMA_END_S       (1 << 31)
204
#define DMA_END_L       (1 << 30)
205
 
206
#define DMA_CR_C        0x80
207
#define DMA_CR_D        0x40
208
#define DMA_CR_E        0x20
209
 
210
#define DMA_ST_OFL      4
211
#define DMA_ST_INT      2
212
#define DMA_ST_AB       1
213
/*
214
 * IOC compatibility
215
 */
216
#define IOC_CONTROL     IOMD_CONTROL
217
#define IOC_IRQSTATA    IOMD_IRQSTATA
218
#define IOC_IRQREQA     IOMD_IRQREQA
219
#define IOC_IRQCLRA     IOMD_IRQCLRA
220
#define IOC_IRQMASKA    IOMD_IRQMASKA
221
 
222
#define IOC_IRQSTATB    IOMD_IRQSTATB
223
#define IOC_IRQREQB     IOMD_IRQREQB
224
#define IOC_IRQMASKB    IOMD_IRQMASKB
225
 
226
#define IOC_FIQSTAT     IOMD_FIQSTAT
227
#define IOC_FIQREQ      IOMD_FIQREQ
228
#define IOC_FIQMASK     IOMD_FIQMASK
229
 
230
#define IOC_T0CNTL      IOMD_T0CNTL
231
#define IOC_T0LTCHL     IOMD_T0LTCHL
232
#define IOC_T0CNTH      IOMD_T0CNTH
233
#define IOC_T0LTCHH     IOMD_T0LTCHH
234
#define IOC_T0GO        IOMD_T0GO
235
#define IOC_T0LATCH     IOMD_T0LATCH
236
 
237
#define IOC_T1CNTL      IOMD_T1CNTL
238
#define IOC_T1LTCHL     IOMD_T1LTCHL
239
#define IOC_T1CNTH      IOMD_T1CNTH
240
#define IOC_T1LTCHH     IOMD_T1LTCHH
241
#define IOC_T1GO        IOMD_T1GO
242
#define IOC_T1LATCH     IOMD_T1LATCH
243
 
244
/*
245
 * DMA (MEMC) compatibility
246
 */
247
#define HALF_SAM        vram_half_sam
248
#define VDMA_ALIGNMENT  (HALF_SAM * 2)
249
#define VDMA_XFERSIZE   (HALF_SAM)
250
#define VDMA_INIT       IOMD_VIDINIT
251
#define VDMA_START      IOMD_VIDSTART
252
#define VDMA_END        IOMD_VIDEND
253
 
254
#ifndef __ASSEMBLER__
255
extern unsigned int vram_half_sam;
256
#define video_set_dma(start,end,offset)                         \
257
do {                                                            \
258
        outl (SCREEN_START + start, VDMA_START);                \
259
        outl (SCREEN_START + end - VDMA_XFERSIZE, VDMA_END);    \
260
        if (offset >= end - VDMA_XFERSIZE)                      \
261
                offset |= 0x40000000;                           \
262
        outl (SCREEN_START + offset, VDMA_INIT);                \
263
} while (0)
264
#endif
265
#endif
266
 
267
#ifdef HAS_EXPMASK
268
#ifndef __ASSEMBLER__
269
#define __EXPMASK(offset)       (((volatile unsigned char *)EXPMASK_BASE)[offset])
270
#else
271
#define __EXPMASK(offset)       offset
272
#endif
273
 
274
#define EXPMASK_STATUS  __EXPMASK(0x00)
275
#define EXPMASK_ENABLE  __EXPMASK(0x04)
276
 
277
#endif
278
 
279
#endif

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.