OpenCores
URL https://opencores.org/ocsvn/or1k_old/or1k_old/trunk

Subversion Repositories or1k_old

[/] [or1k_old/] [trunk/] [rc203soc/] [sw/] [uClinux/] [include/] [asm-ppc/] [processor.h] - Blame information for rev 1782

Details | Compare with Previous | View Log

Line No. Rev Author Line
1 1633 jcastillo
#ifndef __ASM_PPC_PROCESSOR_H
2
#define __ASM_PPC_PROCESSOR_H
3
 
4
/*
5
 * PowerPC machine specifics
6
 */
7
 
8
#ifndef _PPC_MACHINE_H_
9
#define _PPC_MACHINE_H_ 
10
 
11
/* Bit encodings for Machine State Register (MSR) */
12
#define MSR_POW         (1<<18)         /* Enable Power Management */
13
#define MSR_TGPR        (1<<17)         /* TLB Update registers in use */
14
#define MSR_ILE         (1<<16)         /* Interrupt Little-Endian enable */
15
#define MSR_EE          (1<<15)         /* External Interrupt enable */
16
#define MSR_PR          (1<<14)         /* Supervisor/User privilege */
17
#define MSR_FP          (1<<13)         /* Floating Point enable */
18
#define MSR_ME          (1<<12)         /* Machine Check enable */
19
#define MSR_FE0         (1<<11)         /* Floating Exception mode 0 */
20
#define MSR_SE          (1<<10)         /* Single Step */
21
#define MSR_BE          (1<<9)          /* Branch Trace */
22
#define MSR_FE1         (1<<8)          /* Floating Exception mode 1 */
23
#define MSR_IP          (1<<6)          /* Exception prefix 0x000/0xFFF */
24
#define MSR_IR          (1<<5)          /* Instruction MMU enable */
25
#define MSR_DR          (1<<4)          /* Data MMU enable */
26
#define MSR_RI          (1<<1)          /* Recoverable Exception */
27
#define MSR_LE          (1<<0)          /* Little-Endian enable */
28
 
29
#define MSR_            MSR_FP|MSR_FE0|MSR_FE1|MSR_ME
30
#define MSR_USER        MSR_|MSR_PR|MSR_EE|MSR_IR|MSR_DR
31
 
32
/* Bit encodings for Hardware Implementation Register (HID0) */
33
#define HID0_EMCP       (1<<31)         /* Enable Machine Check pin */
34
#define HID0_EBA        (1<<29)         /* Enable Bus Address Parity */
35
#define HID0_EBD        (1<<28)         /* Enable Bus Data Parity */
36
#define HID0_SBCLK      (1<<27)
37
#define HID0_EICE       (1<<26)
38
#define HID0_ECLK       (1<<25)
39
#define HID0_PAR        (1<<24)
40
#define HID0_DOZE       (1<<23)
41
#define HID0_NAP        (1<<22)
42
#define HID0_SLEEP      (1<<21)
43
#define HID0_DPM        (1<<20)
44
#define HID0_ICE        (1<<15)         /* Instruction Cache Enable */
45
#define HID0_DCE        (1<<14)         /* Data Cache Enable */
46
#define HID0_ILOCK      (1<<13)         /* Instruction Cache Lock */
47
#define HID0_DLOCK      (1<<12)         /* Data Cache Lock */
48
#define HID0_ICFI       (1<<11)         /* Instruction Cache Flash Invalidate */
49
#define HID0_DCI        (1<<10)         /* Data Cache Invalidate */
50
 
51
#endif
52
 
53
static inline void start_thread(struct pt_regs * regs, unsigned long eip, unsigned long esp)
54
{
55
  regs->nip = eip;
56
  regs->gpr[1] = esp;
57
  regs->msr = MSR_USER;
58
}
59
 
60
 
61
/*
62
 * Bus types
63
 */
64
#define EISA_bus 0
65
#define EISA_bus__is_a_macro /* for versions in ksyms.c */
66
#define MCA_bus 0
67
#define MCA_bus__is_a_macro /* for versions in ksyms.c */
68
 
69
/*
70
 * Write Protection works right in supervisor mode on the PowerPC
71
 */
72
 
73
#define wp_works_ok 1
74
#define wp_works_ok__is_a_macro /* for versions in ksyms.c */
75
 
76
/*
77
 * User space process size: 2GB. This is hardcoded into a few places,
78
 * so don't change it unless you know what you are doing.
79
 *
80
 * "this is gonna have to change to 1gig for the sparc" - David S. Miller
81
 */
82
#define TASK_SIZE       (0x80000000UL)
83
#define MAX_USER_ADDR   TASK_SIZE
84
#define MMAP_SEARCH_START (TASK_SIZE/3)
85
 
86
struct thread_struct
87
   {
88
        unsigned long   ksp;            /* Kernel stack pointer */
89
        unsigned long   *pg_tables;     /* MMU information */
90
        unsigned long   segs[16];       /* MMU Segment registers */
91
        unsigned long   last_pc;        /* PC when last entered system */
92
        unsigned long   user_stack;     /* [User] Stack when entered kernel */
93
        double          fpr[32];        /* Complete floating point set */
94
        unsigned long   wchan;          /* Event task is sleeping on */
95
        unsigned long   *regs;          /* Pointer to saved register state */
96
   };
97
 
98
#define INIT_TSS  { \
99
        0, 0, {0}, \
100
        0, 0, {0}, \
101
}
102
 
103
#define INIT_MMAP { &init_mm, 0, 0x40000000, \
104
                      PAGE_SHARED, VM_READ | VM_WRITE | VM_EXEC }
105
 
106
#define alloc_kernel_stack()    get_free_page(GFP_KERNEL)
107
#define free_kernel_stack(page) free_page((page))
108
 
109
/*
110
 * Return saved PC of a blocked thread. For now, this is the "user" PC
111
 */
112
static inline unsigned long thread_saved_pc(struct thread_struct *t)
113
{
114
        return (t->last_pc);
115
}
116
 
117
#endif
118
 

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.