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jcastillo |
/* $Id: timer.h,v 1.1 2005-12-20 11:32:12 jcastillo Exp $
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* timer.h: Definitions for the timer chips on the Sparc.
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*
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* Copyright (C) 1995 David S. Miller (davem@caip.rutgers.edu)
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*/
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#ifndef _SPARC_TIMER_H
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#define _SPARC_TIMER_H
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#include <asm/system.h> /* For NCPUS */
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/* Timer structures. The interrupt timer has two properties which
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* are the counter (which is handled in do_timer in sched.c) and the limit.
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* This limit is where the timer's counter 'wraps' around. Oddly enough,
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* the sun4c timer when it hits the limit wraps back to 1 and not zero
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* thus when calculating the value at which it will fire a microsecond you
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* must adjust by one. Thanks SUN for designing such great hardware ;(
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*/
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/* Note that I am only going to use the timer that interrupts at
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* Sparc IRQ 10. There is another one available that can fire at
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* IRQ 14. Currently it is left untouched, we keep the PROM's limit
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* register value and let the prom take these interrupts. This allows
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* L1-A to work.
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*/
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struct sun4c_timer_info {
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volatile unsigned int cur_count10;
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volatile unsigned int timer_limit10;
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volatile unsigned int cur_count14;
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volatile unsigned int timer_limit14;
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};
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#define SUN4C_TIMER_PHYSADDR 0xf3000000
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/* A sun4m has two blocks of registers which are probably of the same
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* structure. LSI Logic's L64851 is told to _decrement_ from the limit
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* value. Aurora behaves similarly but its limit value is compacted in
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* other fashion (it's wider). Documented fields are defined here.
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*/
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/* As with the interrupt register, we have two classes of timer registers
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* which are per-cpu and master. Per-cpu timers only hit that cpu and are
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* only level 14 ticks, master timer hits all cpus and is level 10.
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*/
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#define SUN4M_PRM_CNT_L 0x80000000
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#define SUN4M_PRM_CNT_LVALUE 0x7FFFFC00
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struct sun4m_timer_percpu_info {
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volatile unsigned int l14_timer_limit; /* Initial value is 0x009c4000 */
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volatile unsigned int l14_cur_count;
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/* This register appears to be write only and/or inaccessible
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* on Uni-Processor sun4m machines.
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*/
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volatile unsigned int l14_limit_noclear; /* Data access error is here */
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volatile unsigned int cntrl; /* =1 after POST on Aurora */
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volatile unsigned char space[PAGE_SIZE - 16];
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};
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struct sun4m_timer_regs {
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struct sun4m_timer_percpu_info cpu_timers[NCPUS];
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volatile unsigned int l10_timer_limit;
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volatile unsigned int l10_cur_count;
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/* Again, this appears to be write only and/or inaccessible
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* on uni-processor sun4m machines.
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*/
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volatile unsigned int l10_limit_noclear;
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/* This register too, it must be magic. */
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volatile unsigned int foobar;
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volatile unsigned int cfg; /* equals zero at boot time... */
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};
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extern struct sun4m_timer_regs *sun4m_timers;
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extern volatile unsigned int *master_l10_counter;
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extern volatile unsigned int *master_l10_limit;
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#endif /* !(_SPARC_TIMER_H) */
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