| 1 |
1633 |
jcastillo |
/* $Id: ultra.h,v 1.1 2005-12-20 11:32:12 jcastillo Exp $
|
| 2 |
|
|
* ultra.h: Definitions and defines for the TI V9 UltraSparc.
|
| 3 |
|
|
*
|
| 4 |
|
|
* Copyright (C) 1995 David S. Miller (davem@caip.rutgers.edu)
|
| 5 |
|
|
*/
|
| 6 |
|
|
|
| 7 |
|
|
#ifndef _SPARC_ULTRA_H
|
| 8 |
|
|
#define _SPARC_ULTRA_H
|
| 9 |
|
|
|
| 10 |
|
|
/* Spitfire MMU control register:
|
| 11 |
|
|
*
|
| 12 |
|
|
* ----------------------------------------------------------
|
| 13 |
|
|
* | | IMPL | VERS | | MID | |
|
| 14 |
|
|
* ----------------------------------------------------------
|
| 15 |
|
|
* 64 31-28 27-24 23-22 21-17 16 0
|
| 16 |
|
|
*
|
| 17 |
|
|
* IMPL: Implementation of this Spitfire.
|
| 18 |
|
|
* VERS: Version of this Spitfire.
|
| 19 |
|
|
* MID: Module ID of this processor.
|
| 20 |
|
|
*/
|
| 21 |
|
|
|
| 22 |
|
|
#define SPITFIRE_MIDMASK 0x00000000003e0000
|
| 23 |
|
|
|
| 24 |
|
|
/* Spitfire Load Store Unit control register:
|
| 25 |
|
|
*
|
| 26 |
|
|
* ---------------------------------------------------------------------
|
| 27 |
|
|
* | RSV | PWR | PWW | VWR | VWW | RSV | PMASK | DME | IME | DCE | ICE |
|
| 28 |
|
|
* ---------------------------------------------------------------------
|
| 29 |
|
|
* 63-25 24 23 22 21 20 19-4 3 2 1 0
|
| 30 |
|
|
*
|
| 31 |
|
|
* PWR: Physical Watchpoint Read enable: 0=off 1=on
|
| 32 |
|
|
* PWW: Physical Watchpoint Write enable: 0=off 1=on
|
| 33 |
|
|
* VWR: Virtual Watchpoint Read enable: 0=off 1=on
|
| 34 |
|
|
* VWW: Virtual Watchpoint Write enable: 0=off 1=on
|
| 35 |
|
|
* PMASK: Parity MASK ???
|
| 36 |
|
|
* DME: Data MMU Enable: 0=off 1=on
|
| 37 |
|
|
* IME: Instruction MMU Enable: 0=off 1=on
|
| 38 |
|
|
* DCE: Data Cache Enable: 0=off 1=on
|
| 39 |
|
|
* ICE: Instruction Cache Enable: 0=off 1=on
|
| 40 |
|
|
*/
|
| 41 |
|
|
|
| 42 |
|
|
#define SPITFIRE_LSU_PWR 0x01000000
|
| 43 |
|
|
#define SPITFIRE_LSU_PWW 0x00800000
|
| 44 |
|
|
#define SPITFIRE_LSU_VWR 0x00400000
|
| 45 |
|
|
#define SPITFIRE_LSU_VWW 0x00200000
|
| 46 |
|
|
#define SPITFIRE_LSU_PMASK 0x000ffff0
|
| 47 |
|
|
#define SPITFIRE_LSU_DME 0x00000008
|
| 48 |
|
|
#define SPITFIRE_LSU_IME 0x00000004
|
| 49 |
|
|
#define SPITFIRE_LSU_DCE 0x00000002
|
| 50 |
|
|
#define SPITFIRE_LSU_ICE 0x00000001
|
| 51 |
|
|
|
| 52 |
|
|
#endif /* !(_SPARC_ULTRA_H) */
|
