OpenCores
URL https://opencores.org/ocsvn/or1k_old/or1k_old/trunk

Subversion Repositories or1k_old

[/] [or1k_old/] [trunk/] [uclinux/] [uClinux-2.0.x/] [arch/] [i960/] [lib/] [bzero.c] - Blame information for rev 1782

Details | Compare with Previous | View Log

Line No. Rev Author Line
1 199 simons
 
2
#include <linux/types.h>
3
#include <linux/string.h>
4
 
5
/* Optimization used unaligned access, so it had to go. */
6
 
7
void bzero(void * s, size_t count) {
8
        memset(s, '\0', count);
9
}
10
 
11
#if 0
12
void * memset(void * s, int c, size_t count)
13
{
14
  void *xs = s;
15
  size_t temp, temp1;
16
 
17
  if (!count)
18
    return xs;
19
  c &= 0xff;
20
  c |= c << 8;
21
  c |= c << 16;
22
  if ((long) s & 1)
23
    {
24
      char *cs = s;
25
      *cs++ = c;
26
      s = cs;
27
      count--;
28
    }
29
  if (count > 2 && (long) s & 2)
30
    {
31
      short *ss = s;
32
      *ss++ = c;
33
      s = ss;
34
      count -= 2;
35
    }
36
  temp = count >> 2;
37
  if (temp)
38
    {
39
      long *ls = s;
40
 
41
      __asm__ __volatile__("movel %1,%2\n\t"
42
                           "andw  #7,%2\n\t"
43
                           "lsrl  #3,%1\n\t"
44
                           "negw  %2\n\t"
45
                           "jmp   %%pc@(2f,%2:w:2)\n\t"
46
                           "1:\t"
47
                           "movel %3,%0@+\n\t"
48
                           "movel %3,%0@+\n\t"
49
                           "movel %3,%0@+\n\t"
50
                           "movel %3,%0@+\n\t"
51
                           "movel %3,%0@+\n\t"
52
                           "movel %3,%0@+\n\t"
53
                           "movel %3,%0@+\n\t"
54
                           "movel %3,%0@+\n\t"
55
                           "2:\t"
56
                           "dbra  %1,1b\n\t"
57
                           "clrw  %1\n\t"
58
                           "subql #1,%1\n\t"
59
                           "jpl   1b\n\t"
60
                           : "=a" (ls), "=d" (temp), "=&d" (temp1)
61
                           : "d" (c), "0" (ls), "1" (temp)
62
                           );
63
      s = ls;
64
    }
65
  if (count & 2)
66
    {
67
      short *ss = s;
68
      *ss++ = c;
69
      s = ss;
70
    }
71
  if (count & 1)
72
    {
73
      char *cs = s;
74
      *cs = c;
75
    }
76
  return xs;
77
}
78
#endif

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.