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simons |
/* AM53/79C974 (PCscsi) driver release 0.5
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*
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* The architecture and much of the code of this device
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* driver was originally developed by Drew Eckhardt for
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* the NCR5380. The following copyrights apply:
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* For the architecture and all parts similar to the NCR5380:
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* Copyright 1993, Drew Eckhardt
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* Visionary Computing
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* (Unix and Linux consulting and custom programming)
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* drew@colorado.edu
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* +1 (303) 666-5836
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*
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* The AM53C974_nobios_detect code was originally developed by
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* Robin Cutshaw (robin@xfree86.org) and is used here in a
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* modified form.
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*
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* For the other parts:
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* Copyright 1994, D. Frieauff
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* EMail: fri@rsx42sun0.dofn.de
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* Phone: x49-7545-8-2256 , x49-7541-42305
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*/
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/*
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* $Log: not supported by cvs2svn $
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* Revision 1.1.1.1 2001/07/02 17:58:29 simons
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* Initial revision
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*
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*/
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#ifndef AM53C974_H
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#define AM53C974_H
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#include <scsi/scsicam.h>
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/***************************************************************************************
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* Default setting of the controller's SCSI id. Edit and uncomment this only if your *
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* BIOS does not correctly initialize the controller's SCSI id. *
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* If you don't get a warning during boot, it is correctly initialized. *
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****************************************************************************************/
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/* #define AM53C974_SCSI_ID 7 */
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/***************************************************************************************
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* Default settings for sync. negotiation enable, transfer rate and sync. offset. *
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* These settings can be replaced by LILO overrides (append) with the following syntax: *
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* AM53C974=host-scsi-id, target-scsi-id, max-rate, max-offset *
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* Sync. negotiation is disabled by default and will be enabled for those targets which *
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* are specified in the LILO override *
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****************************************************************************************/
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#define DEFAULT_SYNC_NEGOTIATION_ENABLED 0 /* 0 or 1 */
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#define DEFAULT_RATE 5 /* MHz, min: 3; max: 10 */
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#define DEFAULT_SYNC_OFFSET 0 /* bytes, min: 0; max: 15; use 0 for async. mode */
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/* --------------------- don't edit below here --------------------- */
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#define AM53C974_DRIVER_REVISION_MAJOR 0
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#define AM53C974_DRIVER_REVISION_MINOR 5
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#define SEPARATOR_LINE \
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"--------------------------------------------------------------------------\n"
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/* debug control */
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/* #define AM53C974_DEBUG */
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/* #define AM53C974_DEBUG_MSG */
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/* #define AM53C974_DEBUG_KEYWAIT */
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/* #define AM53C974_DEBUG_INIT */
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/* #define AM53C974_DEBUG_QUEUE */
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/* #define AM53C974_DEBUG_INFO */
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/* #define AM53C974_DEBUG_LINKED */
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/* #define VERBOSE_AM53C974_DEBUG */
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/* #define AM53C974_DEBUG_INTR */
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/* #define AM53C974_DEB_RESEL */
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#define AM53C974_DEBUG_ABORT
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/* #define AM53C974_OPTION_DEBUG_PROBE_ONLY */
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/* special options/constants */
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#define DEF_CLK 40 /* chip clock freq. in MHz */
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#define MIN_PERIOD 4 /* for negotiation: min. number of clocks per cycle */
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#define MAX_PERIOD 13 /* for negotiation: max. number of clocks per cycle */
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#define MAX_OFFSET 15 /* for negotiation: max. offset (0=async) */
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#define DEF_SCSI_TIMEOUT 245 /* STIMREG value, 40 Mhz */
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#define DEF_STP 8 /* STPREG value assuming 5.0 MB/sec, FASTCLK, FASTSCSI */
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#define DEF_SOF_RAD 0 /* REQ/ACK deassertion delay */
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#define DEF_SOF_RAA 0 /* REQ/ACK assertion delay */
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#define DEF_ETM 0 /* CNTLREG1, ext. timing mode */
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#define DEF_PERE 1 /* CNTLREG1, parity error reporting */
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#define DEF_CLKF 0 /* CLKFREG, 0=40 Mhz */
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#define DEF_ENF 1 /* CNTLREG2, enable features */
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#define DEF_ADIDCHK 0 /* CNTLREG3, additional ID check */
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#define DEF_FASTSCSI 1 /* CNTLREG3, fast SCSI */
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#define DEF_FASTCLK 1 /* CNTLREG3, fast clocking, 5 MB/sec at 40MHz chip clk */
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#define DEF_GLITCH 1 /* CNTLREG4, glitch eater, 0=12ns, 1=35ns, 2=25ns, 3=off */
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#define DEF_PWD 0 /* CNTLREG4, reduced power feature */
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#define DEF_RAE 0 /* CNTLREG4, RAE active negation on REQ, ACK only */
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#define DEF_RADE 1 /* 1CNTLREG4, active negation on REQ, ACK and data */
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/*** PCI block ***/
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/* standard registers are defined in <linux/pci.h> */
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#ifndef PCI_VENDOR_ID_AMD
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#define PCI_VENDOR_ID_AMD 0x1022
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#define PCI_DEVICE_ID_AMD_SCSI 0x2020
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#endif
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#define PCI_BASE_MASK 0xFFFFFFE0
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#define PCI_COMMAND_PERREN 0x40
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#define PCI_SCRATCH_REG_0 0x40 /* 16 bits */
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#define PCI_SCRATCH_REG_1 0x42 /* 16 bits */
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#define PCI_SCRATCH_REG_2 0x44 /* 16 bits */
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#define PCI_SCRATCH_REG_3 0x46 /* 16 bits */
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#define PCI_SCRATCH_REG_4 0x48 /* 16 bits */
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#define PCI_SCRATCH_REG_5 0x4A /* 16 bits */
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#define PCI_SCRATCH_REG_6 0x4C /* 16 bits */
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#define PCI_SCRATCH_REG_7 0x4E /* 16 bits */
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/*** SCSI block ***/
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#define CTCLREG 0x00 /* r current transf. count, low byte */
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#define CTCMREG 0x04 /* r current transf. count, middle byte */
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#define CTCHREG 0x38 /* r current transf. count, high byte */
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#define STCLREG 0x00 /* w start transf. count, low byte */
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#define STCMREG 0x04 /* w start transf. count, middle byte */
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#define STCHREG 0x38 /* w start transf. count, high byte */
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#define FFREG 0x08 /* rw SCSI FIFO reg. */
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#define STIMREG 0x14 /* w SCSI timeout reg. */
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#define SDIDREG 0x10 /* w SCSI destination ID reg. */
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#define SDIREG_MASK 0x07 /* mask */
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#define STPREG 0x18 /* w synchronous transf. period reg. */
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#define STPREG_STP 0x1F /* synchr. transfer period */
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#define CLKFREG 0x24 /* w clock factor reg. */
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#define CLKFREG_MASK 0x07 /* mask */
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#define CMDREG 0x0C /* rw SCSI command reg. */
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#define CMDREG_DMA 0x80 /* set DMA mode (set together with opcodes below) */
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#define CMDREG_IT 0x10 /* information transfer */
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#define CMDREG_ICCS 0x11 /* initiator command complete steps */
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#define CMDREG_MA 0x12 /* message accepted */
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#define CMDREG_TPB 0x98 /* transfer pad bytes, DMA mode only */
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#define CMDREG_SATN 0x1A /* set ATN */
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#define CMDREG_RATN 0x1B /* reset ATN */
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#define CMDREG_SOAS 0x41 /* select without ATN steps */
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#define CMDREG_SAS 0x42 /* select with ATN steps (1 msg byte) */
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#define CMDREG_SASS 0x43 /* select with ATN and stop steps */
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#define CMDREG_ESR 0x44 /* enable selection/reselection */
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#define CMDREG_DSR 0x45 /* disable selection/reselection */
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#define CMDREG_SA3S 0x46 /* select with ATN 3 steps (3 msg bytes) */
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#define CMDREG_NOP 0x00 /* no operation */
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#define CMDREG_CFIFO 0x01 /* clear FIFO */
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#define CMDREG_RDEV 0x02 /* reset device */
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#define CMDREG_RBUS 0x03 /* reset SCSI bus */
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#define STATREG 0x10 /* r SCSI status reg. */
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#define STATREG_INT 0x80 /* SCSI interrupt condition detected */
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#define STATREG_IOE 0x40 /* SCSI illegal operation error detected */
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#define STATREG_PE 0x20 /* SCSI parity error detected */
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#define STATREG_CTZ 0x10 /* CTC reg decremented to zero */
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#define STATREG_MSG 0x04 /* SCSI MSG phase (latched?) */
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#define STATREG_CD 0x02 /* SCSI C/D phase (latched?) */
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#define STATREG_IO 0x01 /* SCSI I/O phase (latched?) */
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#define STATREG_PHASE 0x07 /* SCSI phase mask */
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#define INSTREG 0x14 /* r interrupt status reg. */
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#define INSTREG_SRST 0x80 /* SCSI reset detected */
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#define INSTREG_ICMD 0x40 /* SCSI invalid command detected */
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#define INSTREG_DIS 0x20 /* target disconnected or sel/resel timeout*/
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#define INSTREG_SR 0x10 /* device on bus has service request */
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#define INSTREG_SO 0x08 /* successful operation */
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#define INSTREG_RESEL 0x04 /* device reselected as initiator */
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#define ISREG 0x18 /* r internal state reg. */
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#define ISREG_SOF 0x08 /* synchronous offset flag (act. low) */
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#define ISREG_IS 0x07 /* status of intermediate op. */
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#define ISREG_OK_NO_STOP 0x04 /* selection successful */
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#define ISREG_OK_STOP 0x01 /* selection successful */
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#define CFIREG 0x1C /* r current FIFO/internal state reg. */
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#define CFIREG_IS 0xE0 /* status of intermediate op. */
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#define CFIREG_CF 0x1F /* number of bytes in SCSI FIFO */
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#define SOFREG 0x1C /* w synchr. offset reg. */
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#define SOFREG_RAD 0xC0 /* REQ/ACK deassertion delay (sync.) */
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#define SOFREG_RAA 0x30 /* REQ/ACK assertion delay (sync.) */
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#define SOFREG_SO 0x0F /* synch. offset (sync.) */
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#define CNTLREG1 0x20 /* rw control register one */
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#define CNTLREG1_ETM 0x80 /* set extended timing mode */
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#define CNTLREG1_DISR 0x40 /* disable interrupt on SCSI reset */
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#define CNTLREG1_PERE 0x10 /* enable parity error reporting */
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#define CNTLREG1_SID 0x07 /* host adapter SCSI ID */
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#define CNTLREG2 0x2C /* rw control register two */
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#define CNTLREG2_ENF 0x40 /* enable features */
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#define CNTLREG3 0x30 /* rw control register three */
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#define CNTLREG3_ADIDCHK 0x80 /* additional ID check */
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#define CNTLREG3_FASTSCSI 0x10 /* fast SCSI */
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#define CNTLREG3_FASTCLK 0x08 /* fast SCSI clocking */
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#define CNTLREG4 0x34 /* rw control register four */
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#define CNTLREG4_GLITCH 0xC0 /* glitch eater */
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#define CNTLREG4_PWD 0x20 /* reduced power feature */
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#define CNTLREG4_RAE 0x08 /* write only, active negot. ctrl. */
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#define CNTLREG4_RADE 0x04 /* active negot. ctrl. */
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#define CNTLREG4_RES 0x10 /* reserved bit, must be 1 */
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/*** DMA block ***/
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#define DMACMD 0x40 /* rw command */
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#define DMACMD_DIR 0x80 /* transfer direction (1=read from device) */
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#define DMACMD_INTE_D 0x40 /* DMA transfer interrupt enable */
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#define DMACMD_INTE_P 0x20 /* page transfer interrupt enable */
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#define DMACMD_MDL 0x10 /* map to memory descriptor list */
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#define DMACMD_DIAG 0x04 /* diagnostics, set to 0 */
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#define DMACMD_IDLE 0x00 /* idle cmd */
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#define DMACMD_BLAST 0x01 /* flush FIFO to memory */
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#define DMACMD_ABORT 0x02 /* terminate DMA */
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#define DMACMD_START 0x03 /* start DMA */
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| 218 |
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#define DMASTATUS 0x54 /* r status register */
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#define DMASTATUS_BCMPLT 0x20 /* BLAST complete */
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#define DMASTATUS_SCSIINT 0x10 /* SCSI interrupt pending */
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#define DMASTATUS_DONE 0x08 /* DMA transfer terminated */
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#define DMASTATUS_ABORT 0x04 /* DMA transfer aborted */
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#define DMASTATUS_ERROR 0x02 /* DMA transfer error */
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#define DMASTATUS_PWDN 0x02 /* power down indicator */
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#define DMASTC 0x44 /* rw starting transfer count */
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#define DMASPA 0x48 /* rw starting physical address */
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#define DMAWBC 0x4C /* r working byte counter */
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#define DMAWAC 0x50 /* r working address counter */
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#define DMASMDLA 0x58 /* rw starting MDL address */
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#define DMAWMAC 0x5C /* r working MDL counter */
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| 233 |
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/*** SCSI phases ***/
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#define PHASE_MSGIN 0x07
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#define PHASE_MSGOUT 0x06
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#define PHASE_RES_1 0x05
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#define PHASE_RES_0 0x04
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| 238 |
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#define PHASE_STATIN 0x03
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#define PHASE_CMDOUT 0x02
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| 240 |
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#define PHASE_DATAIN 0x01
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#define PHASE_DATAOUT 0x00
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| 243 |
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struct AM53C974_hostdata {
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| 244 |
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volatile unsigned in_reset:1; /* flag, says bus reset pending */
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volatile unsigned aborted:1; /* flag, says aborted */
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| 246 |
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volatile unsigned selecting:1; /* selection started, but not yet finished */
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| 247 |
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volatile unsigned disconnecting: 1; /* disconnection started, but not yet finished */
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| 248 |
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volatile unsigned dma_busy:1; /* dma busy when service request for info transfer received */
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| 249 |
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volatile unsigned char msgout[10]; /* message to output in MSGOUT_PHASE */
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| 250 |
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volatile unsigned char last_message[10]; /* last message OUT */
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| 251 |
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volatile Scsi_Cmnd *issue_queue; /* waiting to be issued */
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| 252 |
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volatile Scsi_Cmnd *disconnected_queue; /* waiting for reconnect */
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| 253 |
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volatile Scsi_Cmnd *sel_cmd; /* command for selection */
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| 254 |
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volatile Scsi_Cmnd *connected; /* currently connected command */
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volatile unsigned char busy[8]; /* index = target, bit = lun */
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| 256 |
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unsigned char sync_per[8]; /* synchronous transfer period (in effect) */
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| 257 |
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unsigned char sync_off[8]; /* synchronous offset (in effect) */
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| 258 |
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unsigned char sync_neg[8]; /* sync. negotiation performed (in effect) */
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| 259 |
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unsigned char sync_en[8]; /* sync. negotiation performed (in effect) */
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| 260 |
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unsigned char max_rate[8]; /* max. transfer rate (setup) */
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unsigned char max_offset[8]; /* max. sync. offset (setup), only valid if corresponding sync_en is nonzero */
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| 262 |
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};
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| 263 |
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| 264 |
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#define AM53C974 { \
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| 265 |
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NULL, /* pointer to next in list */ \
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| 266 |
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NULL, /* long * usage_count */ \
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| 267 |
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NULL, /* struct proc_dir_entry *proc_dir */ \
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| 268 |
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NULL, /* int (*proc_info)(char *, char **, off_t, int, int, int); */ \
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| 269 |
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"AM53C974", /* name */ \
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| 270 |
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AM53C974_detect, /* int (* detect)(struct SHT *) */ \
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| 271 |
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NULL, /* int (*release)(struct Scsi_Host *) */ \
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| 272 |
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AM53C974_info, /* const char *(* info)(struct Scsi_Host *) */ \
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| 273 |
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AM53C974_command, /* int (* command)(Scsi_Cmnd *) */ \
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| 274 |
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AM53C974_queue_command, /* int (* queuecommand)(Scsi_Cmnd *, \
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| 275 |
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void (*done)(Scsi_Cmnd *)) */ \
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| 276 |
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AM53C974_abort, /* int (* abort)(Scsi_Cmnd *) */ \
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| 277 |
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AM53C974_reset, /* int (* reset)(Scsi_Cmnd *) */ \
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| 278 |
|
|
NULL, /* int (* slave_attach)(int, int) */ \
|
| 279 |
|
|
scsicam_bios_param, /* int (* bios_param)(Disk *, int, int[]) */ \
|
| 280 |
|
|
12, /* can_queue */ \
|
| 281 |
|
|
-1, /* this_id */ \
|
| 282 |
|
|
SG_ALL, /* sg_tablesize */ \
|
| 283 |
|
|
1, /* cmd_per_lun */ \
|
| 284 |
|
|
0, /* present, i.e. how many adapters of this kind */ \
|
| 285 |
|
|
0, /* unchecked_isa_dma */ \
|
| 286 |
|
|
DISABLE_CLUSTERING /* use_clustering */ \
|
| 287 |
|
|
}
|
| 288 |
|
|
|
| 289 |
|
|
void AM53C974_setup(char *str, int *ints);
|
| 290 |
|
|
int AM53C974_detect(Scsi_Host_Template *tpnt);
|
| 291 |
|
|
int AM53C974_biosparm(Disk *disk, int dev, int *info_array);
|
| 292 |
|
|
const char *AM53C974_info(struct Scsi_Host *);
|
| 293 |
|
|
int AM53C974_command(Scsi_Cmnd *SCpnt);
|
| 294 |
|
|
int AM53C974_queue_command(Scsi_Cmnd *cmd, void (*done)(Scsi_Cmnd *));
|
| 295 |
|
|
int AM53C974_abort(Scsi_Cmnd *cmd);
|
| 296 |
|
|
int AM53C974_reset (Scsi_Cmnd *cmd, unsigned int flags);
|
| 297 |
|
|
|
| 298 |
|
|
#define AM53C974_local_declare() unsigned long io_port
|
| 299 |
|
|
#define AM53C974_setio(instance) io_port = instance->io_port
|
| 300 |
|
|
#define AM53C974_read_8(addr) inb(io_port + (addr))
|
| 301 |
|
|
#define AM53C974_write_8(addr,x) outb((x), io_port + (addr))
|
| 302 |
|
|
#define AM53C974_read_16(addr) inw(io_port + (addr))
|
| 303 |
|
|
#define AM53C974_write_16(addr,x) outw((x), io_port + (addr))
|
| 304 |
|
|
#define AM53C974_read_32(addr) inl(io_port + (addr))
|
| 305 |
|
|
#define AM53C974_write_32(addr,x) outl((x), io_port + (addr))
|
| 306 |
|
|
|
| 307 |
|
|
#define AM53C974_poll_int() { do { statreg = AM53C974_read_8(STATREG); } \
|
| 308 |
|
|
while (!(statreg & STATREG_INT)) ; \
|
| 309 |
|
|
AM53C974_read_8(INSTREG) ; } /* clear int */
|
| 310 |
|
|
#define AM53C974_cfifo() (AM53C974_read_8(CFIREG) & CFIREG_CF)
|
| 311 |
|
|
|
| 312 |
|
|
/* These are "special" values for the tag parameter passed to AM53C974_select. */
|
| 313 |
|
|
#define TAG_NEXT -1 /* Use next free tag */
|
| 314 |
|
|
#define TAG_NONE -2 /* Establish I_T_L nexus instead of I_T_L_Q
|
| 315 |
|
|
* even on SCSI-II devices */
|
| 316 |
|
|
|
| 317 |
|
|
/************ LILO overrides *************/
|
| 318 |
|
|
typedef struct _override_t {
|
| 319 |
|
|
int host_scsi_id; /* SCSI id of the bus controller */
|
| 320 |
|
|
int target_scsi_id; /* SCSI id of target */
|
| 321 |
|
|
int max_rate; /* max. transfer rate */
|
| 322 |
|
|
int max_offset; /* max. sync. offset, 0 = asynchronous */
|
| 323 |
|
|
} override_t;
|
| 324 |
|
|
|
| 325 |
|
|
/************ PCI stuff *************/
|
| 326 |
|
|
#define AM53C974_PCIREG_OPEN() outb(0xF1, 0xCF8); outb(0, 0xCFA)
|
| 327 |
|
|
#define AM53C974_PCIREG_CLOSE() outb(0, 0xCF8)
|
| 328 |
|
|
#define AM53C974_PCIREG_READ_BYTE(instance,a) ( inb((a) + (instance)->io_port) )
|
| 329 |
|
|
#define AM53C974_PCIREG_READ_WORD(instance,a) ( inw((a) + (instance)->io_port) )
|
| 330 |
|
|
#define AM53C974_PCIREG_READ_DWORD(instance,a) ( inl((a) + (instance)->io_port) )
|
| 331 |
|
|
#define AM53C974_PCIREG_WRITE_BYTE(instance,x,a) ( outb((x), (a) + (instance)->io_port) )
|
| 332 |
|
|
#define AM53C974_PCIREG_WRITE_WORD(instance,x,a) ( outw((x), (a) + (instance)->io_port) )
|
| 333 |
|
|
#define AM53C974_PCIREG_WRITE_DWORD(instance,x,a) ( outl((x), (a) + (instance)->io_port) )
|
| 334 |
|
|
|
| 335 |
|
|
typedef struct _pci_config_t {
|
| 336 |
|
|
/* start of official PCI config space header */
|
| 337 |
|
|
union {
|
| 338 |
|
|
unsigned int device_vendor;
|
| 339 |
|
|
struct {
|
| 340 |
|
|
unsigned short vendor;
|
| 341 |
|
|
unsigned short device;
|
| 342 |
|
|
} dv;
|
| 343 |
|
|
} dv_id;
|
| 344 |
|
|
#define _device_vendor dv_id.device_vendor
|
| 345 |
|
|
#define _vendor dv_id.dv.vendor
|
| 346 |
|
|
#define _device dv_id.dv.device
|
| 347 |
|
|
union {
|
| 348 |
|
|
unsigned int status_command;
|
| 349 |
|
|
struct {
|
| 350 |
|
|
unsigned short command;
|
| 351 |
|
|
unsigned short status;
|
| 352 |
|
|
} sc;
|
| 353 |
|
|
} stat_cmd;
|
| 354 |
|
|
#define _status_command stat_cmd.status_command
|
| 355 |
|
|
#define _command stat_cmd.sc.command
|
| 356 |
|
|
#define _status stat_cmd.sc.status
|
| 357 |
|
|
union {
|
| 358 |
|
|
unsigned int class_revision;
|
| 359 |
|
|
struct {
|
| 360 |
|
|
unsigned char rev_id;
|
| 361 |
|
|
unsigned char prog_if;
|
| 362 |
|
|
unsigned char sub_class;
|
| 363 |
|
|
unsigned char base_class;
|
| 364 |
|
|
} cr;
|
| 365 |
|
|
} class_rev;
|
| 366 |
|
|
#define _class_revision class_rev.class_revision
|
| 367 |
|
|
#define _rev_id class_rev.cr.rev_id
|
| 368 |
|
|
#define _prog_if class_rev.cr.prog_if
|
| 369 |
|
|
#define _sub_class class_rev.cr.sub_class
|
| 370 |
|
|
#define _base_class class_rev.cr.base_class
|
| 371 |
|
|
union {
|
| 372 |
|
|
unsigned int bist_header_latency_cache;
|
| 373 |
|
|
struct {
|
| 374 |
|
|
unsigned char cache_line_size;
|
| 375 |
|
|
unsigned char latency_timer;
|
| 376 |
|
|
unsigned char header_type;
|
| 377 |
|
|
unsigned char bist;
|
| 378 |
|
|
} bhlc;
|
| 379 |
|
|
} bhlc;
|
| 380 |
|
|
#define _bist_header_latency_cache bhlc.bist_header_latency_cache
|
| 381 |
|
|
#define _cache_line_size bhlc.bhlc.cache_line_size
|
| 382 |
|
|
#define _latency_timer bhlc.bhlc.latency_timer
|
| 383 |
|
|
#define _header_type bhlc.bhlc.header_type
|
| 384 |
|
|
#define _bist bhlc.bhlc.bist
|
| 385 |
|
|
unsigned int _base0;
|
| 386 |
|
|
unsigned int _base1;
|
| 387 |
|
|
unsigned int _base2;
|
| 388 |
|
|
unsigned int _base3;
|
| 389 |
|
|
unsigned int _base4;
|
| 390 |
|
|
unsigned int _base5;
|
| 391 |
|
|
unsigned int rsvd1;
|
| 392 |
|
|
unsigned int rsvd2;
|
| 393 |
|
|
unsigned int _baserom;
|
| 394 |
|
|
unsigned int rsvd3;
|
| 395 |
|
|
unsigned int rsvd4;
|
| 396 |
|
|
union {
|
| 397 |
|
|
unsigned int max_min_ipin_iline;
|
| 398 |
|
|
struct {
|
| 399 |
|
|
unsigned char int_line;
|
| 400 |
|
|
unsigned char int_pin;
|
| 401 |
|
|
unsigned char min_gnt;
|
| 402 |
|
|
unsigned char max_lat;
|
| 403 |
|
|
} mmii;
|
| 404 |
|
|
} mmii;
|
| 405 |
|
|
#define _max_min_ipin_iline mmii.max_min_ipin_iline
|
| 406 |
|
|
#define _int_line mmii.mmii.int_line
|
| 407 |
|
|
#define _int_pin mmii.mmii.int_pin
|
| 408 |
|
|
#define _min_gnt mmii.mmii.min_gnt
|
| 409 |
|
|
#define _max_lat mmii.mmii.max_lat
|
| 410 |
|
|
/* end of official PCI config space header */
|
| 411 |
|
|
unsigned short _ioaddr; /* config type 1 - private I/O addr */
|
| 412 |
|
|
unsigned int _pcibus; /* config type 2 - private bus id */
|
| 413 |
|
|
unsigned int _cardnum; /* config type 2 - private card number */
|
| 414 |
|
|
} pci_config_t;
|
| 415 |
|
|
|
| 416 |
|
|
#endif /* AM53C974_H */
|
