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[/] [or1k_old/] [trunk/] [uclinux/] [uClinux-2.0.x/] [sim.cfg] - Blame information for rev 1782

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1 315 simons
/* sim.cfg -- Simulator configuration script file
2
   Copyright (C) 2001, Marko Mlinar, markom@opencores.org
3
 
4 528 simons
This file includes a lot of help about configurations and default one
5
 
6 315 simons
This file is part of OpenRISC 1000 Architectural Simulator.
7
 
8
This program is free software; you can redistribute it and/or modify
9
it under the terms of the GNU General Public License as published by
10
the Free Software Foundation; either version 2 of the License, or
11
(at your option) any later version.
12
 
13
This program is distributed in the hope that it will be useful,
14
but WITHOUT ANY WARRANTY; without even the implied warranty of
15
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
16
GNU General Public License for more details.
17
 
18
You should have received a copy of the GNU General Public License
19
along with this program; if not, write to the Free Software
20
Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. */
21
 
22 528 simons
 
23
/* INTRODUCTION
24
 
25
   The or1ksim have various parameters, which can be set in configuration
26
   files.  Multiple configurations may be used and switched between at
27
   or1ksim startup.
28
   By default, or1ksim loads condfiguration file from './sim.cfg' and if not
29
   found it checks '~/.or1k/sim.cfg'. If even this file is not found or
30
   all parameters are not defined, default configuration is used.
31
   Users should not rely on default configuration, but rather redefine all
32
   critical settings, since default configuration may differ in newer
33
   versions of the or1ksim.
34
   If multiple configurations are used, user can switch between them by
35
   supplying -f  option when starting simulator.
36
 
37
   This file may contain (standard C) only comments - no // support.
38
 
39
   Like normal configuration file, this file is divided in sections,
40
   where each section is described in detail also.
41
 
42
   Some section also have subsections. One example of such subsection is
43
   block:
44
 
45
   device 
46
     instance specific parameters...
47
   enddevice
48
 
49
   which creates a device instance.
50
*/
51
 
52
 
53
/* MEMORY SECTION
54
 
55
   This section specifies how is initial memory generated and which blocks
56
   it consist of.
57
 
58
   type = random/unknown/pattern
59
      specifies the initial memory values. 'random' parameter generate
60
      random memory using seed 'random_seed' parameter. 'pattern' parameter
61
      fills memory with 'pattern' parameter and 'unknown' does not specify
62
      how memory should be generated - the fastest option.
63
 
64
   random_seed = 
65
      random seed for randomizer, used if type = random
66
 
67
   pattern = 
68
      pattern to fill memory, used if type = pattern
69
 
70
   nmemories = 
71
      number of memory instances connected
72
 
73
   instance specific:
74
     baseaddr = 
75
        memory start address
76
 
77
     size = 
78
        memory size
79
 
80
     name = ""
81
        memory block name
82
 
83
     ce = 
84
        chip enable index of the memory instance
85
 
86
     delayr = 
87
        cycles, required for read access, -1 if instance does not support reading
88
 
89
     delayw = 
90
        cycles, required for write access, -1 if instance does not support writing
91
 
92
     16550 = 0/1
93
        0, if this device is uart 16450 and 1, if it is 16550
94
 
95
     log = ""
96
        filename, where to log memory accesses to, no log, if log command is not specified
97
*/
98
 
99 315 simons
section memory
100
  /*random_seed = 12345
101
  type = random*/
102
  pattern = 0x00
103
  type = unknown /* Fastest */
104 528 simons
 
105 753 simons
  nmemories = 3
106 528 simons
  device 0
107 582 simons
    name = "FLASH"
108 528 simons
    ce = 0
109 988 simons
    baseaddr = 0xf0000000
110 753 simons
    size = 0x00800000
111 582 simons
    delayr = 10
112
    delayw = -1
113
/*    log = "flash.log"*/
114 528 simons
  enddevice
115
 
116
  device 1
117 582 simons
    name = "RAM"
118 528 simons
    ce = 1
119 582 simons
    baseaddr = 0x00000000
120 1313 jurem
    size = 0x01000000
121 582 simons
    delayr = 1
122
    delayw = 2
123
/*    log = "ram.log"*/
124 528 simons
  enddevice
125 753 simons
  device 2
126
    name = "SRAM"
127
    ce = 2
128
    baseaddr = 0x08000000
129
    size = 0x00400000
130
    delayr = 1
131
    delayw = 2
132
/*    log = "ram.log"*/
133
  enddevice
134 315 simons
end
135
 
136 528 simons
/* IMMU SECTION
137
 
138
    This section configures Instruction Memory Menangement Unit
139
 
140
    enabled = 0/1
141
       whether IMMU is enabled
142
       (NOTE: UPR bit is set)
143
 
144
    nsets = 
145
       number of ITLB sets; must be power of two
146
 
147
    nways = 
148
       number of ITLB ways
149
 
150
    pagesize = 
151
       instruction page size; must be power of two
152
 
153
    entrysize = 
154
       instruction entry size in bytes
155
 
156
    ustates = 
157
       number of ITLB usage states (2, 3, 4 etc., max is 4)
158
*/
159
 
160
section immu
161 653 simons
  enabled = 1
162
  nsets = 64
163 528 simons
  nways = 1
164
  pagesize = 8192
165
end
166
 
167
/* DMMU SECTION
168
 
169
    This section configures Data Memory Menangement Unit
170
 
171
    enabled = 0/1
172
       whether DMMU is enabled
173
       (NOTE: UPR bit is set)
174
 
175
    nsets = 
176
       number of DTLB sets; must be power of two
177
 
178
    nways = 
179
       number of DTLB ways
180
 
181
    pagesize = 
182
       data page size; must be power of two
183
 
184
    entrysize = 
185
       data entry size in bytes
186
 
187
    ustates = 
188
       number of DTLB usage states (2, 3, 4 etc., max is 4)
189
*/
190
 
191
section dmmu
192 653 simons
  enabled = 1
193
  nsets = 64
194 528 simons
  nways = 1
195
  pagesize = 8192
196
end
197
 
198
 
199
/* IC SECTION
200
 
201
    This section configures Instruction Cache
202
 
203
    enabled = 0/1
204
       whether IC is enabled
205
       (NOTE: UPR bit is set)
206
 
207
    nsets = 
208
       number of IC sets; must be power of two
209
 
210
    nways = 
211
       number of IC ways
212
 
213
    blocksize = 
214
       IC block size in bytes; must be power of two
215
 
216
    ustates = 
217
       number of IC usage states (2, 3, 4 etc., max is 4)
218
*/
219
 
220
section ic
221 653 simons
  enabled = 1
222
  nsets = 256
223 528 simons
  nways = 1
224
  blocksize = 16
225
end
226
 
227
/* DC SECTION
228
 
229
    This section configures Data Cache
230
 
231
    enabled = 0/1
232
       whether DC is enabled
233
       (NOTE: UPR bit is set)
234
 
235
    nsets = 
236
       number of DC sets; must be power of two
237
 
238
    nways = 
239
       number of DC ways
240
 
241
    blocksize = 
242
       DC block size in bytes; must be power of two
243
 
244
    ustates = 
245
       number of DC usage states (2, 3, 4 etc., max is 4)
246
*/
247
 
248
section dc
249 653 simons
  enabled = 1
250
  nsets = 256
251 528 simons
  nways = 1
252
  blocksize = 16
253
end
254
 
255
/* SIM SECTION
256
 
257
  This section specifies how should sim behave.
258
 
259
  verbose = 0/1
260
      whether to print out extra messages
261
 
262
  debug = 0-9
263
      = 0 disabled debug messages
264
      1-9 level of sim debug information, greater the number more verbose is
265
          the output
266
 
267
  profile = 0/1
268
      whether to generate profiling file 'sim.profile'
269
 
270
  prof_fn = ""
271
      filename, where to generate profiling info, used
272
      only if 'profile' is set
273
 
274
  history = 0/1
275
      whether instruction execution flow is tracked for
276
      display by simulator hist command. Useful for
277
      back-trace debugging.
278
 
279
  iprompt = 0/1
280
      whether we strart in interactive prompt
281
 
282
  exe_log = 0/1
283
      whether execution log should be generated
284
 
285
  exe_log_fn = ""
286
      where to put execution log in, used only if 'exe_log'
287
      is set
288
 
289
  clkcycle = [ps|ns|us|ms]
290
      specifies time measurement for one cycle
291
*/
292
 
293
section sim
294 727 simons
  verbose = 0
295 528 simons
  debug = 0
296
  profile = 0
297
  prof_fn = "sim.profile"
298
 
299 711 simons
  history = 0
300 528 simons
  /* iprompt = 0 */
301
  exe_log = 0
302 682 simons
  exe_log_type = software
303 1313 jurem
  exe_log_start = 3800000
304 743 simons
/*  exe_log_end = 20000000*/
305 1313 jurem
  exe_log_marker = 1000
306 528 simons
  exe_log_fn = "executed.log"
307
end
308
 
309
 
310
/* SECTION VAPI
311
 
312
    This section configures Verification API, used for Advanced
313
    Core Verification.
314
 
315
    enabled = 0/1
316
        whether to start VAPI server
317
 
318
    server_port = 
319
        TCP/IP port to start VAPI server on
320
 
321
    log_enabled = 0/1
322
       whether logging of VAPI requests is enabled
323
 
324
    vapi_fn = 
325
       specifies filename where to log into, if log_enabled is selected
326
*/
327
 
328
section VAPI
329
  enabled = 0
330
  server_port = 9998
331
  log_enabled = 0
332
  vapi_log_fn = "vapi.log"
333
end
334
 
335
 
336
/* CPU SECTION
337
 
338
   This section specifies various CPU parameters.
339
 
340
   ver = 
341
   rev = 
342
      specifies version and revision of the CPU used
343
 
344
   upr = 
345
      changes the upr register
346
 
347
   superscalar = 0/1
348
      whether CPU is scalar or superscalar
349
      (modify cpu/or32/execute.c to tune superscalar model)
350
 
351
   hazards = 0/1
352
      whether data hazards are tracked in superscalar CPU
353
      and displayed by the simulator r command
354
 
355
   dependstats = 0/1
356
      whether inter-instruction dependencies are calculated
357
      and displayed by simulator stats command.
358
 
359
   slp = 0/1
360
      calculation of subroutine level parallelism. Displayed
361
      by simulator stats command.
362
 
363
   btic = 0/1
364
      enable branch target instruction cache model
365
 
366
   bpb = 0/1
367
      enable branch prediction buffer model
368
 
369
      parameters for CPU analysis
370
*/
371
 
372 315 simons
section cpu
373
  ver = 0x1200
374
  rev = 0x0001
375
  /* upr = */
376
  superscalar = 0
377
  hazards = 0
378
  dependstats = 0
379
  slp = 0
380 528 simons
  btic = 0
381 315 simons
  bpb = 0
382
end
383
 
384 528 simons
 
385
/* DEBUG SECTION
386
 
387
   This sections specifies how debug unit should behave.
388
 
389
   enabled = 0/1
390
      whether debug unit is enabled
391
 
392
   gdb_enabled = 0/1
393
      whether to start gdb server at 'server_port' port
394
 
395
   server_port = 
396
      TCP/IP port to start gdb server on, used only if gdb_enabled
397
      is set
398
 
399 315 simons
section debug
400 528 simons
  enabled = 0
401
  gdb_enabled = 0
402 315 simons
  server_port = 9999
403
end
404
 
405
 
406 528 simons
/* MC SECTION
407
 
408
   This section configures the memory controller
409
 
410
   enabled = 0/1
411
      whether memory controller is enabled
412
 
413
   baseaddr = 
414
      address of first MC register
415
 
416
   POC = 
417
      Power On Configuration register
418
*/
419
 
420 315 simons
section mc
421 582 simons
  enabled = 1
422 988 simons
  baseaddr = 0x93000000
423 315 simons
  POC = 0x00000008                 /* Power on configuration register */
424
end
425
 
426 528 simons
 
427
/* UART SECTION
428
 
429
   This section configures UARTs
430
 
431
   enabled = 0/1
432
      whether uarts are enabled
433
 
434
   nuarts = 
435
      make specified number of instances, configure each
436
      instance within device - enddevice construct.
437
 
438
   instance specific:
439
     baseaddr = 
440
        address of first UART register for this device
441
 
442
     rx_file = ""
443
        filename, where to read data from
444
 
445
     tx_file = ""
446
        filename, where to write data to
447
 
448
     irq = 
449
        irq number for this device
450
 
451
     16550 = 0/1
452
        0, if this device is uart 16450 and 1, if it is 16550
453
 
454
     jitter = 
455
        in msecs... time to block, -1 to disable it
456
 
457
     vapi_id = 
458
        VAPI id of this instance
459
*/
460
 
461 315 simons
section uart
462
  enabled = 1
463
  nuarts = 1
464 528 simons
 
465 315 simons
  device 0
466 753 simons
    baseaddr = 0x90000000
467 988 simons
    irq = 2
468 1313 jurem
    rxfile = "uart0.rx"
469
    txfile = "uart0.tx"
470 315 simons
    jitter = -1                     /* async behaviour */
471 531 simons
    16550 = 1
472 315 simons
  enddevice
473
end
474
 
475 528 simons
 
476
/* DMA SECTION
477
 
478
   This section configures DMAs
479
 
480
   enabled = 0/1
481
      whether DMAs are enabled
482
 
483
   ndmas = 
484
      make specified number of instances, configure each
485
      instance within device - enddevice construct.
486
 
487
   instance specific:
488
     baseaddr = 
489
        address of first DMA register for this device
490
 
491
     irq = 
492
        irq number for this device
493
 
494
     vapi_id = 
495
        VAPI id of this instance
496
*/
497
 
498 315 simons
section dma
499
  enabled = 0
500
  ndmas = 1
501 528 simons
 
502 315 simons
  device 0
503 988 simons
    baseaddr = 0x9a000000
504
    irq = 11
505 315 simons
  enddevice
506
end
507
 
508 528 simons
 
509
/* ETHERNET SECTION
510
 
511
   This section configures ethernets
512
 
513
   enabled = 0/1
514
      whether ethernets are enabled
515
 
516
   nethernets = 
517
      make specified number of instances, configure each
518
      instance within device - enddevice construct.
519
 
520
   instance specific:
521
     baseaddr = 
522
        address of first ethernet register for this device
523
 
524
     dma = 
525
        which controller is this ethernet "connected" to
526
 
527
     rx_channel = 
528
        DMA channel used for RX
529
 
530
     tx_channel = 
531
        DMA channel used for TX
532
 
533
     rx_file = ""
534
        filename, where to read data from
535
 
536
     tx_file = ""
537
        filename, where to write data to
538
 
539
     vapi_id = 
540
        VAPI id of this instance
541
*/
542
 
543
section ethernet
544
  nethernets = 1
545
 
546
  device 0
547 988 simons
    baseaddr = 0x92000000
548 528 simons
    dma = 0
549 988 simons
    irq = 4
550 764 simons
    rtx_type = 1
551 528 simons
    tx_channel = 0
552
    rx_channel = 1
553 753 simons
    rxfile = "eth0.rx"
554
    txfile = "eth0.tx"
555 743 simons
    sockif = "eth0"
556 528 simons
  enddevice
557 315 simons
end
558 528 simons
 
559
/* TICK TIMER SECTION
560
 
561
    This section configures tick timer
562
 
563
    enabled = 0/1
564
      whether tick timer is enabled
565
 
566
    irq = 
567
      irq number
568
*/
569
 
570
section tick
571
  enabled = 1
572 582 simons
  irq = 0
573 528 simons
end
574 656 simons
 
575
section fb
576
  enabled = 1
577 988 simons
  baseaddr = 0x97000000
578 852 simons
  refresh_rate = 10000000
579 656 simons
  filename = "primary"
580
end
581 727 simons
 
582
/* KBD SECTION
583
 
584
    This section configures PS/2 compatible keyboard
585
 
586
    enabled = 0/1
587
      whether keyboard is enabled
588
 
589
    baseaddr = 
590
      base address of the keyboard device
591
 
592
    rxfile = ""
593
      filename, where to read data from
594
*/
595
 
596
section kbd
597
  enabled = 1
598 988 simons
  irq = 5
599
  baseaddr = 0x94000000
600 727 simons
  rxfile = "kbd.rx"
601
end
602
 

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