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[/] [or1k_soc_on_altera_embedded_dev_kit/] [tags/] [linux-2.6/] [linux-2.6.24_or32_unified_v2.3/] [arch/] [arm/] [plat-omap/] [gpio.c] - Blame information for rev 3

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1 3 xianfeng 
/*
2 
 *  linux/arch/arm/plat-omap/gpio.c
3 
 *
4 
 * Support functions for OMAP GPIO
5 
 *
6 
 * Copyright (C) 2003-2005 Nokia Corporation
7 
 * Written by Juha Yrjölä <juha.yrjola@nokia.com>
8 
 *
9 
 * This program is free software; you can redistribute it and/or modify
10 
 * it under the terms of the GNU General Public License version 2 as
11 
 * published by the Free Software Foundation.
12 
 */
13 
 
14 
#include <linux/init.h>
15 
#include <linux/module.h>
16 
#include <linux/interrupt.h>
17 
#include <linux/sysdev.h>
18 
#include <linux/err.h>
19 
#include <linux/clk.h>
20 
 
21 
#include <asm/hardware.h>
22 
#include <asm/irq.h>
23 
#include <asm/arch/irqs.h>
24 
#include <asm/arch/gpio.h>
25 
#include <asm/mach/irq.h>
26 
 
27 
#include <asm/io.h>
28 
 
29 
/*
30 
 * OMAP1510 GPIO registers
31 
 */
32 
#define OMAP1510_GPIO_BASE              (void __iomem *)0xfffce000
33 
#define OMAP1510_GPIO_DATA_INPUT        0x00
34 
#define OMAP1510_GPIO_DATA_OUTPUT       0x04
35 
#define OMAP1510_GPIO_DIR_CONTROL       0x08
36 
#define OMAP1510_GPIO_INT_CONTROL       0x0c
37 
#define OMAP1510_GPIO_INT_MASK          0x10
38 
#define OMAP1510_GPIO_INT_STATUS        0x14
39 
#define OMAP1510_GPIO_PIN_CONTROL       0x18
40 
 
41 
#define OMAP1510_IH_GPIO_BASE           64
42 
 
43 
/*
44 
 * OMAP1610 specific GPIO registers
45 
 */
46 
#define OMAP1610_GPIO1_BASE             (void __iomem *)0xfffbe400
47 
#define OMAP1610_GPIO2_BASE             (void __iomem *)0xfffbec00
48 
#define OMAP1610_GPIO3_BASE             (void __iomem *)0xfffbb400
49 
#define OMAP1610_GPIO4_BASE             (void __iomem *)0xfffbbc00
50 
#define OMAP1610_GPIO_REVISION          0x0000
51 
#define OMAP1610_GPIO_SYSCONFIG         0x0010
52 
#define OMAP1610_GPIO_SYSSTATUS         0x0014
53 
#define OMAP1610_GPIO_IRQSTATUS1        0x0018
54 
#define OMAP1610_GPIO_IRQENABLE1        0x001c
55 
#define OMAP1610_GPIO_WAKEUPENABLE      0x0028
56 
#define OMAP1610_GPIO_DATAIN            0x002c
57 
#define OMAP1610_GPIO_DATAOUT           0x0030
58 
#define OMAP1610_GPIO_DIRECTION         0x0034
59 
#define OMAP1610_GPIO_EDGE_CTRL1        0x0038
60 
#define OMAP1610_GPIO_EDGE_CTRL2        0x003c
61 
#define OMAP1610_GPIO_CLEAR_IRQENABLE1  0x009c
62 
#define OMAP1610_GPIO_CLEAR_WAKEUPENA   0x00a8
63 
#define OMAP1610_GPIO_CLEAR_DATAOUT     0x00b0
64 
#define OMAP1610_GPIO_SET_IRQENABLE1    0x00dc
65 
#define OMAP1610_GPIO_SET_WAKEUPENA     0x00e8
66 
#define OMAP1610_GPIO_SET_DATAOUT       0x00f0
67 
 
68 
/*
69 
 * OMAP730 specific GPIO registers
70 
 */
71 
#define OMAP730_GPIO1_BASE              (void __iomem *)0xfffbc000
72 
#define OMAP730_GPIO2_BASE              (void __iomem *)0xfffbc800
73 
#define OMAP730_GPIO3_BASE              (void __iomem *)0xfffbd000
74 
#define OMAP730_GPIO4_BASE              (void __iomem *)0xfffbd800
75 
#define OMAP730_GPIO5_BASE              (void __iomem *)0xfffbe000
76 
#define OMAP730_GPIO6_BASE              (void __iomem *)0xfffbe800
77 
#define OMAP730_GPIO_DATA_INPUT         0x00
78 
#define OMAP730_GPIO_DATA_OUTPUT        0x04
79 
#define OMAP730_GPIO_DIR_CONTROL        0x08
80 
#define OMAP730_GPIO_INT_CONTROL        0x0c
81 
#define OMAP730_GPIO_INT_MASK           0x10
82 
#define OMAP730_GPIO_INT_STATUS         0x14
83 
 
84 
/*
85 
 * omap24xx specific GPIO registers
86 
 */
87 
#define OMAP242X_GPIO1_BASE             (void __iomem *)0x48018000
88 
#define OMAP242X_GPIO2_BASE             (void __iomem *)0x4801a000
89 
#define OMAP242X_GPIO3_BASE             (void __iomem *)0x4801c000
90 
#define OMAP242X_GPIO4_BASE             (void __iomem *)0x4801e000
91 
 
92 
#define OMAP243X_GPIO1_BASE             (void __iomem *)0x4900C000
93 
#define OMAP243X_GPIO2_BASE             (void __iomem *)0x4900E000
94 
#define OMAP243X_GPIO3_BASE             (void __iomem *)0x49010000
95 
#define OMAP243X_GPIO4_BASE             (void __iomem *)0x49012000
96 
#define OMAP243X_GPIO5_BASE             (void __iomem *)0x480B6000
97 
 
98 
#define OMAP24XX_GPIO_REVISION          0x0000
99 
#define OMAP24XX_GPIO_SYSCONFIG         0x0010
100 
#define OMAP24XX_GPIO_SYSSTATUS         0x0014
101 
#define OMAP24XX_GPIO_IRQSTATUS1        0x0018
102 
#define OMAP24XX_GPIO_IRQSTATUS2        0x0028
103 
#define OMAP24XX_GPIO_IRQENABLE2        0x002c
104 
#define OMAP24XX_GPIO_IRQENABLE1        0x001c
105 
#define OMAP24XX_GPIO_CTRL              0x0030
106 
#define OMAP24XX_GPIO_OE                0x0034
107 
#define OMAP24XX_GPIO_DATAIN            0x0038
108 
#define OMAP24XX_GPIO_DATAOUT           0x003c
109 
#define OMAP24XX_GPIO_LEVELDETECT0      0x0040
110 
#define OMAP24XX_GPIO_LEVELDETECT1      0x0044
111 
#define OMAP24XX_GPIO_RISINGDETECT      0x0048
112 
#define OMAP24XX_GPIO_FALLINGDETECT     0x004c
113 
#define OMAP24XX_GPIO_CLEARIRQENABLE1   0x0060
114 
#define OMAP24XX_GPIO_SETIRQENABLE1     0x0064
115 
#define OMAP24XX_GPIO_CLEARWKUENA       0x0080
116 
#define OMAP24XX_GPIO_SETWKUENA         0x0084
117 
#define OMAP24XX_GPIO_CLEARDATAOUT      0x0090
118 
#define OMAP24XX_GPIO_SETDATAOUT        0x0094
119 
 
120 
struct gpio_bank {
121 
        void __iomem *base;
122 
        u16 irq;
123 
        u16 virtual_irq_start;
124 
        int method;
125 
        u32 reserved_map;
126 
#if defined (CONFIG_ARCH_OMAP16XX) || defined (CONFIG_ARCH_OMAP24XX)
127 
        u32 suspend_wakeup;
128 
        u32 saved_wakeup;
129 
#endif
130 
#ifdef CONFIG_ARCH_OMAP24XX
131 
        u32 non_wakeup_gpios;
132 
        u32 enabled_non_wakeup_gpios;
133 
 
134 
        u32 saved_datain;
135 
        u32 saved_fallingdetect;
136 
        u32 saved_risingdetect;
137 
#endif
138 
        spinlock_t lock;
139 
};
140 
 
141 
#define METHOD_MPUIO            0
142 
#define METHOD_GPIO_1510        1
143 
#define METHOD_GPIO_1610        2
144 
#define METHOD_GPIO_730         3
145 
#define METHOD_GPIO_24XX        4
146 
 
147 
#ifdef CONFIG_ARCH_OMAP16XX
148 
static struct gpio_bank gpio_bank_1610[5] = {
149 
        { OMAP_MPUIO_BASE,     INT_MPUIO,           IH_MPUIO_BASE,     METHOD_MPUIO},
150 
        { OMAP1610_GPIO1_BASE, INT_GPIO_BANK1,      IH_GPIO_BASE,      METHOD_GPIO_1610 },
151 
        { OMAP1610_GPIO2_BASE, INT_1610_GPIO_BANK2, IH_GPIO_BASE + 16, METHOD_GPIO_1610 },
152 
        { OMAP1610_GPIO3_BASE, INT_1610_GPIO_BANK3, IH_GPIO_BASE + 32, METHOD_GPIO_1610 },
153 
        { OMAP1610_GPIO4_BASE, INT_1610_GPIO_BANK4, IH_GPIO_BASE + 48, METHOD_GPIO_1610 },
154 
};
155 
#endif
156 
 
157 
#ifdef CONFIG_ARCH_OMAP15XX
158 
static struct gpio_bank gpio_bank_1510[2] = {
159 
        { OMAP_MPUIO_BASE,    INT_MPUIO,      IH_MPUIO_BASE, METHOD_MPUIO },
160 
        { OMAP1510_GPIO_BASE, INT_GPIO_BANK1, IH_GPIO_BASE,  METHOD_GPIO_1510 }
161 
};
162 
#endif
163 
 
164 
#ifdef CONFIG_ARCH_OMAP730
165 
static struct gpio_bank gpio_bank_730[7] = {
166 
        { OMAP_MPUIO_BASE,     INT_730_MPUIO,       IH_MPUIO_BASE,      METHOD_MPUIO },
167 
        { OMAP730_GPIO1_BASE,  INT_730_GPIO_BANK1,  IH_GPIO_BASE,       METHOD_GPIO_730 },
168 
        { OMAP730_GPIO2_BASE,  INT_730_GPIO_BANK2,  IH_GPIO_BASE + 32,  METHOD_GPIO_730 },
169 
        { OMAP730_GPIO3_BASE,  INT_730_GPIO_BANK3,  IH_GPIO_BASE + 64,  METHOD_GPIO_730 },
170 
        { OMAP730_GPIO4_BASE,  INT_730_GPIO_BANK4,  IH_GPIO_BASE + 96,  METHOD_GPIO_730 },
171 
        { OMAP730_GPIO5_BASE,  INT_730_GPIO_BANK5,  IH_GPIO_BASE + 128, METHOD_GPIO_730 },
172 
        { OMAP730_GPIO6_BASE,  INT_730_GPIO_BANK6,  IH_GPIO_BASE + 160, METHOD_GPIO_730 },
173 
};
174 
#endif
175 
 
176 
#ifdef CONFIG_ARCH_OMAP24XX
177 
 
178 
static struct gpio_bank gpio_bank_242x[4] = {
179 
        { OMAP242X_GPIO1_BASE, INT_24XX_GPIO_BANK1, IH_GPIO_BASE,       METHOD_GPIO_24XX },
180 
        { OMAP242X_GPIO2_BASE, INT_24XX_GPIO_BANK2, IH_GPIO_BASE + 32,  METHOD_GPIO_24XX },
181 
        { OMAP242X_GPIO3_BASE, INT_24XX_GPIO_BANK3, IH_GPIO_BASE + 64,  METHOD_GPIO_24XX },
182 
        { OMAP242X_GPIO4_BASE, INT_24XX_GPIO_BANK4, IH_GPIO_BASE + 96,  METHOD_GPIO_24XX },
183 
};
184 
 
185 
static struct gpio_bank gpio_bank_243x[5] = {
186 
        { OMAP243X_GPIO1_BASE, INT_24XX_GPIO_BANK1, IH_GPIO_BASE,       METHOD_GPIO_24XX },
187 
        { OMAP243X_GPIO2_BASE, INT_24XX_GPIO_BANK2, IH_GPIO_BASE + 32,  METHOD_GPIO_24XX },
188 
        { OMAP243X_GPIO3_BASE, INT_24XX_GPIO_BANK3, IH_GPIO_BASE + 64,  METHOD_GPIO_24XX },
189 
        { OMAP243X_GPIO4_BASE, INT_24XX_GPIO_BANK4, IH_GPIO_BASE + 96,  METHOD_GPIO_24XX },
190 
        { OMAP243X_GPIO5_BASE, INT_24XX_GPIO_BANK5, IH_GPIO_BASE + 128, METHOD_GPIO_24XX },
191 
};
192 
 
193 
#endif
194 
 
195 
static struct gpio_bank *gpio_bank;
196 
static int gpio_bank_count;
197 
 
198 
static inline struct gpio_bank *get_gpio_bank(int gpio)
199 
{
200 
#ifdef CONFIG_ARCH_OMAP15XX
201 
        if (cpu_is_omap15xx()) {
202 
                if (OMAP_GPIO_IS_MPUIO(gpio))
203 
                        return &gpio_bank[0];
204 
                return &gpio_bank[1];
205 
        }
206 
#endif
207 
#if defined(CONFIG_ARCH_OMAP16XX)
208 
        if (cpu_is_omap16xx()) {
209 
                if (OMAP_GPIO_IS_MPUIO(gpio))
210 
                        return &gpio_bank[0];
211 
                return &gpio_bank[1 + (gpio >> 4)];
212 
        }
213 
#endif
214 
#ifdef CONFIG_ARCH_OMAP730
215 
        if (cpu_is_omap730()) {
216 
                if (OMAP_GPIO_IS_MPUIO(gpio))
217 
                        return &gpio_bank[0];
218 
                return &gpio_bank[1 + (gpio >> 5)];
219 
        }
220 
#endif
221 
#ifdef CONFIG_ARCH_OMAP24XX
222 
        if (cpu_is_omap24xx())
223 
                return &gpio_bank[gpio >> 5];
224 
#endif
225 
}
226 
 
227 
static inline int get_gpio_index(int gpio)
228 
{
229 
#ifdef CONFIG_ARCH_OMAP730
230 
        if (cpu_is_omap730())
231 
                return gpio & 0x1f;
232 
#endif
233 
#ifdef CONFIG_ARCH_OMAP24XX
234 
        if (cpu_is_omap24xx())
235 
                return gpio & 0x1f;
236 
#endif
237 
        return gpio & 0x0f;
238 
}
239 
 
240 
static inline int gpio_valid(int gpio)
241 
{
242 
        if (gpio < 0)
243 
                return -1;
244 
#ifndef CONFIG_ARCH_OMAP24XX
245 
        if (OMAP_GPIO_IS_MPUIO(gpio)) {
246 
                if (gpio >= OMAP_MAX_GPIO_LINES + 16)
247 
                        return -1;
248 
                return 0;
249 
        }
250 
#endif
251 
#ifdef CONFIG_ARCH_OMAP15XX
252 
        if (cpu_is_omap15xx() && gpio < 16)
253 
                return 0;
254 
#endif
255 
#if defined(CONFIG_ARCH_OMAP16XX)
256 
        if ((cpu_is_omap16xx()) && gpio < 64)
257 
                return 0;
258 
#endif
259 
#ifdef CONFIG_ARCH_OMAP730
260 
        if (cpu_is_omap730() && gpio < 192)
261 
                return 0;
262 
#endif
263 
#ifdef CONFIG_ARCH_OMAP24XX
264 
        if (cpu_is_omap24xx() && gpio < 128)
265 
                return 0;
266 
#endif
267 
        return -1;
268 
}
269 
 
270 
static int check_gpio(int gpio)
271 
{
272 
        if (unlikely(gpio_valid(gpio)) < 0) {
273 
                printk(KERN_ERR "omap-gpio: invalid GPIO %d\n", gpio);
274 
                dump_stack();
275 
                return -1;
276 
        }
277 
        return 0;
278 
}
279 
 
280 
static void _set_gpio_direction(struct gpio_bank *bank, int gpio, int is_input)
281 
{
282 
        void __iomem *reg = bank->base;
283 
        u32 l;
284 
 
285 
        switch (bank->method) {
286 
#ifdef CONFIG_ARCH_OMAP1
287 
        case METHOD_MPUIO:
288 
                reg += OMAP_MPUIO_IO_CNTL;
289 
                break;
290 
#endif
291 
#ifdef CONFIG_ARCH_OMAP15XX
292 
        case METHOD_GPIO_1510:
293 
                reg += OMAP1510_GPIO_DIR_CONTROL;
294 
                break;
295 
#endif
296 
#ifdef CONFIG_ARCH_OMAP16XX
297 
        case METHOD_GPIO_1610:
298 
                reg += OMAP1610_GPIO_DIRECTION;
299 
                break;
300 
#endif
301 
#ifdef CONFIG_ARCH_OMAP730
302 
        case METHOD_GPIO_730:
303 
                reg += OMAP730_GPIO_DIR_CONTROL;
304 
                break;
305 
#endif
306 
#ifdef CONFIG_ARCH_OMAP24XX
307 
        case METHOD_GPIO_24XX:
308 
                reg += OMAP24XX_GPIO_OE;
309 
                break;
310 
#endif
311 
        default:
312 
                WARN_ON(1);
313 
                return;
314 
        }
315 
        l = __raw_readl(reg);
316 
        if (is_input)
317 
                l |= 1 << gpio;
318 
        else
319 
                l &= ~(1 << gpio);
320 
        __raw_writel(l, reg);
321 
}
322 
 
323 
void omap_set_gpio_direction(int gpio, int is_input)
324 
{
325 
        struct gpio_bank *bank;
326 
 
327 
        if (check_gpio(gpio) < 0)
328 
                return;
329 
        bank = get_gpio_bank(gpio);
330 
        spin_lock(&bank->lock);
331 
        _set_gpio_direction(bank, get_gpio_index(gpio), is_input);
332 
        spin_unlock(&bank->lock);
333 
}
334 
 
335 
static void _set_gpio_dataout(struct gpio_bank *bank, int gpio, int enable)
336 
{
337 
        void __iomem *reg = bank->base;
338 
        u32 l = 0;
339 
 
340 
        switch (bank->method) {
341 
#ifdef CONFIG_ARCH_OMAP1
342 
        case METHOD_MPUIO:
343 
                reg += OMAP_MPUIO_OUTPUT;
344 
                l = __raw_readl(reg);
345 
                if (enable)
346 
                        l |= 1 << gpio;
347 
                else
348 
                        l &= ~(1 << gpio);
349 
                break;
350 
#endif
351 
#ifdef CONFIG_ARCH_OMAP15XX
352 
        case METHOD_GPIO_1510:
353 
                reg += OMAP1510_GPIO_DATA_OUTPUT;
354 
                l = __raw_readl(reg);
355 
                if (enable)
356 
                        l |= 1 << gpio;
357 
                else
358 
                        l &= ~(1 << gpio);
359 
                break;
360 
#endif
361 
#ifdef CONFIG_ARCH_OMAP16XX
362 
        case METHOD_GPIO_1610:
363 
                if (enable)
364 
                        reg += OMAP1610_GPIO_SET_DATAOUT;
365 
                else
366 
                        reg += OMAP1610_GPIO_CLEAR_DATAOUT;
367 
                l = 1 << gpio;
368 
                break;
369 
#endif
370 
#ifdef CONFIG_ARCH_OMAP730
371 
        case METHOD_GPIO_730:
372 
                reg += OMAP730_GPIO_DATA_OUTPUT;
373 
                l = __raw_readl(reg);
374 
                if (enable)
375 
                        l |= 1 << gpio;
376 
                else
377 
                        l &= ~(1 << gpio);
378 
                break;
379 
#endif
380 
#ifdef CONFIG_ARCH_OMAP24XX
381 
        case METHOD_GPIO_24XX:
382 
                if (enable)
383 
                        reg += OMAP24XX_GPIO_SETDATAOUT;
384 
                else
385 
                        reg += OMAP24XX_GPIO_CLEARDATAOUT;
386 
                l = 1 << gpio;
387 
                break;
388 
#endif
389 
        default:
390 
                WARN_ON(1);
391 
                return;
392 
        }
393 
        __raw_writel(l, reg);
394 
}
395 
 
396 
void omap_set_gpio_dataout(int gpio, int enable)
397 
{
398 
        struct gpio_bank *bank;
399 
 
400 
        if (check_gpio(gpio) < 0)
401 
                return;
402 
        bank = get_gpio_bank(gpio);
403 
        spin_lock(&bank->lock);
404 
        _set_gpio_dataout(bank, get_gpio_index(gpio), enable);
405 
        spin_unlock(&bank->lock);
406 
}
407 
 
408 
int omap_get_gpio_datain(int gpio)
409 
{
410 
        struct gpio_bank *bank;
411 
        void __iomem *reg;
412 
 
413 
        if (check_gpio(gpio) < 0)
414 
                return -EINVAL;
415 
        bank = get_gpio_bank(gpio);
416 
        reg = bank->base;
417 
        switch (bank->method) {
418 
#ifdef CONFIG_ARCH_OMAP1
419 
        case METHOD_MPUIO:
420 
                reg += OMAP_MPUIO_INPUT_LATCH;
421 
                break;
422 
#endif
423 
#ifdef CONFIG_ARCH_OMAP15XX
424 
        case METHOD_GPIO_1510:
425 
                reg += OMAP1510_GPIO_DATA_INPUT;
426 
                break;
427 
#endif
428 
#ifdef CONFIG_ARCH_OMAP16XX
429 
        case METHOD_GPIO_1610:
430 
                reg += OMAP1610_GPIO_DATAIN;
431 
                break;
432 
#endif
433 
#ifdef CONFIG_ARCH_OMAP730
434 
        case METHOD_GPIO_730:
435 
                reg += OMAP730_GPIO_DATA_INPUT;
436 
                break;
437 
#endif
438 
#ifdef CONFIG_ARCH_OMAP24XX
439 
        case METHOD_GPIO_24XX:
440 
                reg += OMAP24XX_GPIO_DATAIN;
441 
                break;
442 
#endif
443 
        default:
444 
                return -EINVAL;
445 
        }
446 
        return (__raw_readl(reg)
447 
                        & (1 << get_gpio_index(gpio))) != 0;
448 
}
449 
 
450 
#define MOD_REG_BIT(reg, bit_mask, set) \
451 
do {    \
452 
        int l = __raw_readl(base + reg); \
453 
        if (set) l |= bit_mask; \
454 
        else l &= ~bit_mask; \
455 
        __raw_writel(l, base + reg); \
456 
} while(0)
457 
 
458 
#ifdef CONFIG_ARCH_OMAP24XX
459 
static inline void set_24xx_gpio_triggering(struct gpio_bank *bank, int gpio, int trigger)
460 
{
461 
        void __iomem *base = bank->base;
462 
        u32 gpio_bit = 1 << gpio;
463 
 
464 
        MOD_REG_BIT(OMAP24XX_GPIO_LEVELDETECT0, gpio_bit,
465 
                trigger & __IRQT_LOWLVL);
466 
        MOD_REG_BIT(OMAP24XX_GPIO_LEVELDETECT1, gpio_bit,
467 
                trigger & __IRQT_HIGHLVL);
468 
        MOD_REG_BIT(OMAP24XX_GPIO_RISINGDETECT, gpio_bit,
469 
                trigger & __IRQT_RISEDGE);
470 
        MOD_REG_BIT(OMAP24XX_GPIO_FALLINGDETECT, gpio_bit,
471 
                trigger & __IRQT_FALEDGE);
472 
        if (likely(!(bank->non_wakeup_gpios & gpio_bit))) {
473 
                if (trigger != 0)
474 
                        __raw_writel(1 << gpio, bank->base + OMAP24XX_GPIO_SETWKUENA);
475 
                else
476 
                        __raw_writel(1 << gpio, bank->base + OMAP24XX_GPIO_CLEARWKUENA);
477 
        } else {
478 
                if (trigger != 0)
479 
                        bank->enabled_non_wakeup_gpios |= gpio_bit;
480 
                else
481 
                        bank->enabled_non_wakeup_gpios &= ~gpio_bit;
482 
        }
483 
        /* FIXME: Possibly do 'set_irq_handler(j, handle_level_irq)' if only level
484 
         * triggering requested. */
485 
}
486 
#endif
487 
 
488 
static int _set_gpio_triggering(struct gpio_bank *bank, int gpio, int trigger)
489 
{
490 
        void __iomem *reg = bank->base;
491 
        u32 l = 0;
492 
 
493 
        switch (bank->method) {
494 
#ifdef CONFIG_ARCH_OMAP1
495 
        case METHOD_MPUIO:
496 
                reg += OMAP_MPUIO_GPIO_INT_EDGE;
497 
                l = __raw_readl(reg);
498 
                if (trigger & __IRQT_RISEDGE)
499 
                        l |= 1 << gpio;
500 
                else if (trigger & __IRQT_FALEDGE)
501 
                        l &= ~(1 << gpio);
502 
                else
503 
                        goto bad;
504 
                break;
505 
#endif
506 
#ifdef CONFIG_ARCH_OMAP15XX
507 
        case METHOD_GPIO_1510:
508 
                reg += OMAP1510_GPIO_INT_CONTROL;
509 
                l = __raw_readl(reg);
510 
                if (trigger & __IRQT_RISEDGE)
511 
                        l |= 1 << gpio;
512 
                else if (trigger & __IRQT_FALEDGE)
513 
                        l &= ~(1 << gpio);
514 
                else
515 
                        goto bad;
516 
                break;
517 
#endif
518 
#ifdef CONFIG_ARCH_OMAP16XX
519 
        case METHOD_GPIO_1610:
520 
                if (gpio & 0x08)
521 
                        reg += OMAP1610_GPIO_EDGE_CTRL2;
522 
                else
523 
                        reg += OMAP1610_GPIO_EDGE_CTRL1;
524 
                gpio &= 0x07;
525 
                l = __raw_readl(reg);
526 
                l &= ~(3 << (gpio << 1));
527 
                if (trigger & __IRQT_RISEDGE)
528 
                        l |= 2 << (gpio << 1);
529 
                if (trigger & __IRQT_FALEDGE)
530 
                        l |= 1 << (gpio << 1);
531 
                if (trigger)
532 
                        /* Enable wake-up during idle for dynamic tick */
533 
                        __raw_writel(1 << gpio, bank->base + OMAP1610_GPIO_SET_WAKEUPENA);
534 
                else
535 
                        __raw_writel(1 << gpio, bank->base + OMAP1610_GPIO_CLEAR_WAKEUPENA);
536 
                break;
537 
#endif
538 
#ifdef CONFIG_ARCH_OMAP730
539 
        case METHOD_GPIO_730:
540 
                reg += OMAP730_GPIO_INT_CONTROL;
541 
                l = __raw_readl(reg);
542 
                if (trigger & __IRQT_RISEDGE)
543 
                        l |= 1 << gpio;
544 
                else if (trigger & __IRQT_FALEDGE)
545 
                        l &= ~(1 << gpio);
546 
                else
547 
                        goto bad;
548 
                break;
549 
#endif
550 
#ifdef CONFIG_ARCH_OMAP24XX
551 
        case METHOD_GPIO_24XX:
552 
                set_24xx_gpio_triggering(bank, gpio, trigger);
553 
                break;
554 
#endif
555 
        default:
556 
                goto bad;
557 
        }
558 
        __raw_writel(l, reg);
559 
        return 0;
560 
bad:
561 
        return -EINVAL;
562 
}
563 
 
564 
static int gpio_irq_type(unsigned irq, unsigned type)
565 
{
566 
        struct gpio_bank *bank;
567 
        unsigned gpio;
568 
        int retval;
569 
 
570 
        if (!cpu_is_omap24xx() && irq > IH_MPUIO_BASE)
571 
                gpio = OMAP_MPUIO(irq - IH_MPUIO_BASE);
572 
        else
573 
                gpio = irq - IH_GPIO_BASE;
574 
 
575 
        if (check_gpio(gpio) < 0)
576 
                return -EINVAL;
577 
 
578 
        if (type & ~IRQ_TYPE_SENSE_MASK)
579 
                return -EINVAL;
580 
 
581 
        /* OMAP1 allows only only edge triggering */
582 
        if (!cpu_is_omap24xx()
583 
                        && (type & (IRQ_TYPE_LEVEL_LOW|IRQ_TYPE_LEVEL_HIGH)))
584 
                return -EINVAL;
585 
 
586 
        bank = get_irq_chip_data(irq);
587 
        spin_lock(&bank->lock);
588 
        retval = _set_gpio_triggering(bank, get_gpio_index(gpio), type);
589 
        if (retval == 0) {
590 
                irq_desc[irq].status &= ~IRQ_TYPE_SENSE_MASK;
591 
                irq_desc[irq].status |= type;
592 
        }
593 
        spin_unlock(&bank->lock);
594 
        return retval;
595 
}
596 
 
597 
static void _clear_gpio_irqbank(struct gpio_bank *bank, int gpio_mask)
598 
{
599 
        void __iomem *reg = bank->base;
600 
 
601 
        switch (bank->method) {
602 
#ifdef CONFIG_ARCH_OMAP1
603 
        case METHOD_MPUIO:
604 
                /* MPUIO irqstatus is reset by reading the status register,
605 
                 * so do nothing here */
606 
                return;
607 
#endif
608 
#ifdef CONFIG_ARCH_OMAP15XX
609 
        case METHOD_GPIO_1510:
610 
                reg += OMAP1510_GPIO_INT_STATUS;
611 
                break;
612 
#endif
613 
#ifdef CONFIG_ARCH_OMAP16XX
614 
        case METHOD_GPIO_1610:
615 
                reg += OMAP1610_GPIO_IRQSTATUS1;
616 
                break;
617 
#endif
618 
#ifdef CONFIG_ARCH_OMAP730
619 
        case METHOD_GPIO_730:
620 
                reg += OMAP730_GPIO_INT_STATUS;
621 
                break;
622 
#endif
623 
#ifdef CONFIG_ARCH_OMAP24XX
624 
        case METHOD_GPIO_24XX:
625 
                reg += OMAP24XX_GPIO_IRQSTATUS1;
626 
                break;
627 
#endif
628 
        default:
629 
                WARN_ON(1);
630 
                return;
631 
        }
632 
        __raw_writel(gpio_mask, reg);
633 
 
634 
        /* Workaround for clearing DSP GPIO interrupts to allow retention */
635 
        if (cpu_is_omap2420())
636 
                __raw_writel(gpio_mask, bank->base + OMAP24XX_GPIO_IRQSTATUS2);
637 
}
638 
 
639 
static inline void _clear_gpio_irqstatus(struct gpio_bank *bank, int gpio)
640 
{
641 
        _clear_gpio_irqbank(bank, 1 << get_gpio_index(gpio));
642 
}
643 
 
644 
static u32 _get_gpio_irqbank_mask(struct gpio_bank *bank)
645 
{
646 
        void __iomem *reg = bank->base;
647 
        int inv = 0;
648 
        u32 l;
649 
        u32 mask;
650 
 
651 
        switch (bank->method) {
652 
#ifdef CONFIG_ARCH_OMAP1
653 
        case METHOD_MPUIO:
654 
                reg += OMAP_MPUIO_GPIO_MASKIT;
655 
                mask = 0xffff;
656 
                inv = 1;
657 
                break;
658 
#endif
659 
#ifdef CONFIG_ARCH_OMAP15XX
660 
        case METHOD_GPIO_1510:
661 
                reg += OMAP1510_GPIO_INT_MASK;
662 
                mask = 0xffff;
663 
                inv = 1;
664 
                break;
665 
#endif
666 
#ifdef CONFIG_ARCH_OMAP16XX
667 
        case METHOD_GPIO_1610:
668 
                reg += OMAP1610_GPIO_IRQENABLE1;
669 
                mask = 0xffff;
670 
                break;
671 
#endif
672 
#ifdef CONFIG_ARCH_OMAP730
673 
        case METHOD_GPIO_730:
674 
                reg += OMAP730_GPIO_INT_MASK;
675 
                mask = 0xffffffff;
676 
                inv = 1;
677 
                break;
678 
#endif
679 
#ifdef CONFIG_ARCH_OMAP24XX
680 
        case METHOD_GPIO_24XX:
681 
                reg += OMAP24XX_GPIO_IRQENABLE1;
682 
                mask = 0xffffffff;
683 
                break;
684 
#endif
685 
        default:
686 
                WARN_ON(1);
687 
                return 0;
688 
        }
689 
 
690 
        l = __raw_readl(reg);
691 
        if (inv)
692 
                l = ~l;
693 
        l &= mask;
694 
        return l;
695 
}
696 
 
697 
static void _enable_gpio_irqbank(struct gpio_bank *bank, int gpio_mask, int enable)
698 
{
699 
        void __iomem *reg = bank->base;
700 
        u32 l;
701 
 
702 
        switch (bank->method) {
703 
#ifdef CONFIG_ARCH_OMAP1
704 
        case METHOD_MPUIO:
705 
                reg += OMAP_MPUIO_GPIO_MASKIT;
706 
                l = __raw_readl(reg);
707 
                if (enable)
708 
                        l &= ~(gpio_mask);
709 
                else
710 
                        l |= gpio_mask;
711 
                break;
712 
#endif
713 
#ifdef CONFIG_ARCH_OMAP15XX
714 
        case METHOD_GPIO_1510:
715 
                reg += OMAP1510_GPIO_INT_MASK;
716 
                l = __raw_readl(reg);
717 
                if (enable)
718 
                        l &= ~(gpio_mask);
719 
                else
720 
                        l |= gpio_mask;
721 
                break;
722 
#endif
723 
#ifdef CONFIG_ARCH_OMAP16XX
724 
        case METHOD_GPIO_1610:
725 
                if (enable)
726 
                        reg += OMAP1610_GPIO_SET_IRQENABLE1;
727 
                else
728 
                        reg += OMAP1610_GPIO_CLEAR_IRQENABLE1;
729 
                l = gpio_mask;
730 
                break;
731 
#endif
732 
#ifdef CONFIG_ARCH_OMAP730
733 
        case METHOD_GPIO_730:
734 
                reg += OMAP730_GPIO_INT_MASK;
735 
                l = __raw_readl(reg);
736 
                if (enable)
737 
                        l &= ~(gpio_mask);
738 
                else
739 
                        l |= gpio_mask;
740 
                break;
741 
#endif
742 
#ifdef CONFIG_ARCH_OMAP24XX
743 
        case METHOD_GPIO_24XX:
744 
                if (enable)
745 
                        reg += OMAP24XX_GPIO_SETIRQENABLE1;
746 
                else
747 
                        reg += OMAP24XX_GPIO_CLEARIRQENABLE1;
748 
                l = gpio_mask;
749 
                break;
750 
#endif
751 
        default:
752 
                WARN_ON(1);
753 
                return;
754 
        }
755 
        __raw_writel(l, reg);
756 
}
757 
 
758 
static inline void _set_gpio_irqenable(struct gpio_bank *bank, int gpio, int enable)
759 
{
760 
        _enable_gpio_irqbank(bank, 1 << get_gpio_index(gpio), enable);
761 
}
762 
 
763 
/*
764 
 * Note that ENAWAKEUP needs to be enabled in GPIO_SYSCONFIG register.
765 
 * 1510 does not seem to have a wake-up register. If JTAG is connected
766 
 * to the target, system will wake up always on GPIO events. While
767 
 * system is running all registered GPIO interrupts need to have wake-up
768 
 * enabled. When system is suspended, only selected GPIO interrupts need
769 
 * to have wake-up enabled.
770 
 */
771 
static int _set_gpio_wakeup(struct gpio_bank *bank, int gpio, int enable)
772 
{
773 
        switch (bank->method) {
774 
#ifdef CONFIG_ARCH_OMAP16XX
775 
        case METHOD_MPUIO:
776 
        case METHOD_GPIO_1610:
777 
                spin_lock(&bank->lock);
778 
                if (enable) {
779 
                        bank->suspend_wakeup |= (1 << gpio);
780 
                        enable_irq_wake(bank->irq);
781 
                } else {
782 
                        disable_irq_wake(bank->irq);
783 
                        bank->suspend_wakeup &= ~(1 << gpio);
784 
                }
785 
                spin_unlock(&bank->lock);
786 
                return 0;
787 
#endif
788 
#ifdef CONFIG_ARCH_OMAP24XX
789 
        case METHOD_GPIO_24XX:
790 
                if (bank->non_wakeup_gpios & (1 << gpio)) {
791 
                        printk(KERN_ERR "Unable to modify wakeup on "
792 
                                        "non-wakeup GPIO%d\n",
793 
                                        (bank - gpio_bank) * 32 + gpio);
794 
                        return -EINVAL;
795 
                }
796 
                spin_lock(&bank->lock);
797 
                if (enable) {
798 
                        bank->suspend_wakeup |= (1 << gpio);
799 
                        enable_irq_wake(bank->irq);
800 
                } else {
801 
                        disable_irq_wake(bank->irq);
802 
                        bank->suspend_wakeup &= ~(1 << gpio);
803 
                }
804 
                spin_unlock(&bank->lock);
805 
                return 0;
806 
#endif
807 
        default:
808 
                printk(KERN_ERR "Can't enable GPIO wakeup for method %i\n",
809 
                       bank->method);
810 
                return -EINVAL;
811 
        }
812 
}
813 
 
814 
static void _reset_gpio(struct gpio_bank *bank, int gpio)
815 
{
816 
        _set_gpio_direction(bank, get_gpio_index(gpio), 1);
817 
        _set_gpio_irqenable(bank, gpio, 0);
818 
        _clear_gpio_irqstatus(bank, gpio);
819 
        _set_gpio_triggering(bank, get_gpio_index(gpio), IRQT_NOEDGE);
820 
}
821 
 
822 
/* Use disable_irq_wake() and enable_irq_wake() functions from drivers */
823 
static int gpio_wake_enable(unsigned int irq, unsigned int enable)
824 
{
825 
        unsigned int gpio = irq - IH_GPIO_BASE;
826 
        struct gpio_bank *bank;
827 
        int retval;
828 
 
829 
        if (check_gpio(gpio) < 0)
830 
                return -ENODEV;
831 
        bank = get_irq_chip_data(irq);
832 
        retval = _set_gpio_wakeup(bank, get_gpio_index(gpio), enable);
833 
 
834 
        return retval;
835 
}
836 
 
837 
int omap_request_gpio(int gpio)
838 
{
839 
        struct gpio_bank *bank;
840 
 
841 
        if (check_gpio(gpio) < 0)
842 
                return -EINVAL;
843 
 
844 
        bank = get_gpio_bank(gpio);
845 
        spin_lock(&bank->lock);
846 
        if (unlikely(bank->reserved_map & (1 << get_gpio_index(gpio)))) {
847 
                printk(KERN_ERR "omap-gpio: GPIO %d is already reserved!\n", gpio);
848 
                dump_stack();
849 
                spin_unlock(&bank->lock);
850 
                return -1;
851 
        }
852 
        bank->reserved_map |= (1 << get_gpio_index(gpio));
853 
 
854 
        /* Set trigger to none. You need to enable the desired trigger with
855 
         * request_irq() or set_irq_type().
856 
         */
857 
        _set_gpio_triggering(bank, get_gpio_index(gpio), IRQT_NOEDGE);
858 
 
859 
#ifdef CONFIG_ARCH_OMAP15XX
860 
        if (bank->method == METHOD_GPIO_1510) {
861 
                void __iomem *reg;
862 
 
863 
                /* Claim the pin for MPU */
864 
                reg = bank->base + OMAP1510_GPIO_PIN_CONTROL;
865 
                __raw_writel(__raw_readl(reg) | (1 << get_gpio_index(gpio)), reg);
866 
        }
867 
#endif
868 
        spin_unlock(&bank->lock);
869 
 
870 
        return 0;
871 
}
872 
 
873 
void omap_free_gpio(int gpio)
874 
{
875 
        struct gpio_bank *bank;
876 
 
877 
        if (check_gpio(gpio) < 0)
878 
                return;
879 
        bank = get_gpio_bank(gpio);
880 
        spin_lock(&bank->lock);
881 
        if (unlikely(!(bank->reserved_map & (1 << get_gpio_index(gpio))))) {
882 
                printk(KERN_ERR "omap-gpio: GPIO %d wasn't reserved!\n", gpio);
883 
                dump_stack();
884 
                spin_unlock(&bank->lock);
885 
                return;
886 
        }
887 
#ifdef CONFIG_ARCH_OMAP16XX
888 
        if (bank->method == METHOD_GPIO_1610) {
889 
                /* Disable wake-up during idle for dynamic tick */
890 
                void __iomem *reg = bank->base + OMAP1610_GPIO_CLEAR_WAKEUPENA;
891 
                __raw_writel(1 << get_gpio_index(gpio), reg);
892 
        }
893 
#endif
894 
#ifdef CONFIG_ARCH_OMAP24XX
895 
        if (bank->method == METHOD_GPIO_24XX) {
896 
                /* Disable wake-up during idle for dynamic tick */
897 
                void __iomem *reg = bank->base + OMAP24XX_GPIO_CLEARWKUENA;
898 
                __raw_writel(1 << get_gpio_index(gpio), reg);
899 
        }
900 
#endif
901 
        bank->reserved_map &= ~(1 << get_gpio_index(gpio));
902 
        _reset_gpio(bank, gpio);
903 
        spin_unlock(&bank->lock);
904 
}
905 
 
906 
/*
907 
 * We need to unmask the GPIO bank interrupt as soon as possible to
908 
 * avoid missing GPIO interrupts for other lines in the bank.
909 
 * Then we need to mask-read-clear-unmask the triggered GPIO lines
910 
 * in the bank to avoid missing nested interrupts for a GPIO line.
911 
 * If we wait to unmask individual GPIO lines in the bank after the
912 
 * line's interrupt handler has been run, we may miss some nested
913 
 * interrupts.
914 
 */
915 
static void gpio_irq_handler(unsigned int irq, struct irq_desc *desc)
916 
{
917 
        void __iomem *isr_reg = NULL;
918 
        u32 isr;
919 
        unsigned int gpio_irq;
920 
        struct gpio_bank *bank;
921 
        u32 retrigger = 0;
922 
        int unmasked = 0;
923 
 
924 
        desc->chip->ack(irq);
925 
 
926 
        bank = get_irq_data(irq);
927 
#ifdef CONFIG_ARCH_OMAP1
928 
        if (bank->method == METHOD_MPUIO)
929 
                isr_reg = bank->base + OMAP_MPUIO_GPIO_INT;
930 
#endif
931 
#ifdef CONFIG_ARCH_OMAP15XX
932 
        if (bank->method == METHOD_GPIO_1510)
933 
                isr_reg = bank->base + OMAP1510_GPIO_INT_STATUS;
934 
#endif
935 
#if defined(CONFIG_ARCH_OMAP16XX)
936 
        if (bank->method == METHOD_GPIO_1610)
937 
                isr_reg = bank->base + OMAP1610_GPIO_IRQSTATUS1;
938 
#endif
939 
#ifdef CONFIG_ARCH_OMAP730
940 
        if (bank->method == METHOD_GPIO_730)
941 
                isr_reg = bank->base + OMAP730_GPIO_INT_STATUS;
942 
#endif
943 
#ifdef CONFIG_ARCH_OMAP24XX
944 
        if (bank->method == METHOD_GPIO_24XX)
945 
                isr_reg = bank->base + OMAP24XX_GPIO_IRQSTATUS1;
946 
#endif
947 
        while(1) {
948 
                u32 isr_saved, level_mask = 0;
949 
                u32 enabled;
950 
 
951 
                enabled = _get_gpio_irqbank_mask(bank);
952 
                isr_saved = isr = __raw_readl(isr_reg) & enabled;
953 
 
954 
                if (cpu_is_omap15xx() && (bank->method == METHOD_MPUIO))
955 
                        isr &= 0x0000ffff;
956 
 
957 
                if (cpu_is_omap24xx()) {
958 
                        level_mask =
959 
                                __raw_readl(bank->base +
960 
                                        OMAP24XX_GPIO_LEVELDETECT0) |
961 
                                __raw_readl(bank->base +
962 
                                        OMAP24XX_GPIO_LEVELDETECT1);
963 
                        level_mask &= enabled;
964 
                }
965 
 
966 
                /* clear edge sensitive interrupts before handler(s) are
967 
                called so that we don't miss any interrupt occurred while
968 
                executing them */
969 
                _enable_gpio_irqbank(bank, isr_saved & ~level_mask, 0);
970 
                _clear_gpio_irqbank(bank, isr_saved & ~level_mask);
971 
                _enable_gpio_irqbank(bank, isr_saved & ~level_mask, 1);
972 
 
973 
                /* if there is only edge sensitive GPIO pin interrupts
974 
                configured, we could unmask GPIO bank interrupt immediately */
975 
                if (!level_mask && !unmasked) {
976 
                        unmasked = 1;
977 
                        desc->chip->unmask(irq);
978 
                }
979 
 
980 
                isr |= retrigger;
981 
                retrigger = 0;
982 
                if (!isr)
983 
                        break;
984 
 
985 
                gpio_irq = bank->virtual_irq_start;
986 
                for (; isr != 0; isr >>= 1, gpio_irq++) {
987 
                        struct irq_desc *d;
988 
                        int irq_mask;
989 
                        if (!(isr & 1))
990 
                                continue;
991 
                        d = irq_desc + gpio_irq;
992 
                        /* Don't run the handler if it's already running
993 
                         * or was disabled lazely.
994 
                         */
995 
                        if (unlikely((d->depth ||
996 
                                      (d->status & IRQ_INPROGRESS)))) {
997 
                                irq_mask = 1 <<
998 
                                        (gpio_irq - bank->virtual_irq_start);
999 
                                /* The unmasking will be done by
1000 
                                 * enable_irq in case it is disabled or
1001 
                                 * after returning from the handler if
1002 
                                 * it's already running.
1003 
                                 */
1004 
                                _enable_gpio_irqbank(bank, irq_mask, 0);
1005 
                                if (!d->depth) {
1006 
                                        /* Level triggered interrupts
1007 
                                         * won't ever be reentered
1008 
                                         */
1009 
                                        BUG_ON(level_mask & irq_mask);
1010 
                                        d->status |= IRQ_PENDING;
1011 
                                }
1012 
                                continue;
1013 
                        }
1014 
 
1015 
                        desc_handle_irq(gpio_irq, d);
1016 
 
1017 
                        if (unlikely((d->status & IRQ_PENDING) && !d->depth)) {
1018 
                                irq_mask = 1 <<
1019 
                                        (gpio_irq - bank->virtual_irq_start);
1020 
                                d->status &= ~IRQ_PENDING;
1021 
                                _enable_gpio_irqbank(bank, irq_mask, 1);
1022 
                                retrigger |= irq_mask;
1023 
                        }
1024 
                }
1025 
 
1026 
                if (cpu_is_omap24xx()) {
1027 
                        /* clear level sensitive interrupts after handler(s) */
1028 
                        _enable_gpio_irqbank(bank, isr_saved & level_mask, 0);
1029 
                        _clear_gpio_irqbank(bank, isr_saved & level_mask);
1030 
                        _enable_gpio_irqbank(bank, isr_saved & level_mask, 1);
1031 
                }
1032 
 
1033 
        }
1034 
        /* if bank has any level sensitive GPIO pin interrupt
1035 
        configured, we must unmask the bank interrupt only after
1036 
        handler(s) are executed in order to avoid spurious bank
1037 
        interrupt */
1038 
        if (!unmasked)
1039 
                desc->chip->unmask(irq);
1040 
 
1041 
}
1042 
 
1043 
static void gpio_irq_shutdown(unsigned int irq)
1044 
{
1045 
        unsigned int gpio = irq - IH_GPIO_BASE;
1046 
        struct gpio_bank *bank = get_irq_chip_data(irq);
1047 
 
1048 
        _reset_gpio(bank, gpio);
1049 
}
1050 
 
1051 
static void gpio_ack_irq(unsigned int irq)
1052 
{
1053 
        unsigned int gpio = irq - IH_GPIO_BASE;
1054 
        struct gpio_bank *bank = get_irq_chip_data(irq);
1055 
 
1056 
        _clear_gpio_irqstatus(bank, gpio);
1057 
}
1058 
 
1059 
static void gpio_mask_irq(unsigned int irq)
1060 
{
1061 
        unsigned int gpio = irq - IH_GPIO_BASE;
1062 
        struct gpio_bank *bank = get_irq_chip_data(irq);
1063 
 
1064 
        _set_gpio_irqenable(bank, gpio, 0);
1065 
}
1066 
 
1067 
static void gpio_unmask_irq(unsigned int irq)
1068 
{
1069 
        unsigned int gpio = irq - IH_GPIO_BASE;
1070 
        unsigned int gpio_idx = get_gpio_index(gpio);
1071 
        struct gpio_bank *bank = get_irq_chip_data(irq);
1072 
 
1073 
        _set_gpio_irqenable(bank, gpio_idx, 1);
1074 
}
1075 
 
1076 
static struct irq_chip gpio_irq_chip = {
1077 
        .name           = "GPIO",
1078 
        .shutdown       = gpio_irq_shutdown,
1079 
        .ack            = gpio_ack_irq,
1080 
        .mask           = gpio_mask_irq,
1081 
        .unmask         = gpio_unmask_irq,
1082 
        .set_type       = gpio_irq_type,
1083 
        .set_wake       = gpio_wake_enable,
1084 
};
1085 
 
1086 
/*---------------------------------------------------------------------*/
1087 
 
1088 
#ifdef CONFIG_ARCH_OMAP1
1089 
 
1090 
/* MPUIO uses the always-on 32k clock */
1091 
 
1092 
static void mpuio_ack_irq(unsigned int irq)
1093 
{
1094 
        /* The ISR is reset automatically, so do nothing here. */
1095 
}
1096 
 
1097 
static void mpuio_mask_irq(unsigned int irq)
1098 
{
1099 
        unsigned int gpio = OMAP_MPUIO(irq - IH_MPUIO_BASE);
1100 
        struct gpio_bank *bank = get_irq_chip_data(irq);
1101 
 
1102 
        _set_gpio_irqenable(bank, gpio, 0);
1103 
}
1104 
 
1105 
static void mpuio_unmask_irq(unsigned int irq)
1106 
{
1107 
        unsigned int gpio = OMAP_MPUIO(irq - IH_MPUIO_BASE);
1108 
        struct gpio_bank *bank = get_irq_chip_data(irq);
1109 
 
1110 
        _set_gpio_irqenable(bank, gpio, 1);
1111 
}
1112 
 
1113 
static struct irq_chip mpuio_irq_chip = {
1114 
        .name           = "MPUIO",
1115 
        .ack            = mpuio_ack_irq,
1116 
        .mask           = mpuio_mask_irq,
1117 
        .unmask         = mpuio_unmask_irq,
1118 
        .set_type       = gpio_irq_type,
1119 
#ifdef CONFIG_ARCH_OMAP16XX
1120 
        /* REVISIT: assuming only 16xx supports MPUIO wake events */
1121 
        .set_wake       = gpio_wake_enable,
1122 
#endif
1123 
};
1124 
 
1125 
 
1126 
#define bank_is_mpuio(bank)     ((bank)->method == METHOD_MPUIO)
1127 
 
1128 
 
1129 
#ifdef CONFIG_ARCH_OMAP16XX
1130 
 
1131 
#include <linux/platform_device.h>
1132 
 
1133 
static int omap_mpuio_suspend_late(struct platform_device *pdev, pm_message_t mesg)
1134 
{
1135 
        struct gpio_bank        *bank = platform_get_drvdata(pdev);
1136 
        void __iomem            *mask_reg = bank->base + OMAP_MPUIO_GPIO_MASKIT;
1137 
 
1138 
        spin_lock(&bank->lock);
1139 
        bank->saved_wakeup = __raw_readl(mask_reg);
1140 
        __raw_writel(0xffff & ~bank->suspend_wakeup, mask_reg);
1141 
        spin_unlock(&bank->lock);
1142 
 
1143 
        return 0;
1144 
}
1145 
 
1146 
static int omap_mpuio_resume_early(struct platform_device *pdev)
1147 
{
1148 
        struct gpio_bank        *bank = platform_get_drvdata(pdev);
1149 
        void __iomem            *mask_reg = bank->base + OMAP_MPUIO_GPIO_MASKIT;
1150 
 
1151 
        spin_lock(&bank->lock);
1152 
        __raw_writel(bank->saved_wakeup, mask_reg);
1153 
        spin_unlock(&bank->lock);
1154 
 
1155 
        return 0;
1156 
}
1157 
 
1158 
/* use platform_driver for this, now that there's no longer any
1159 
 * point to sys_device (other than not disturbing old code).
1160 
 */
1161 
static struct platform_driver omap_mpuio_driver = {
1162 
        .suspend_late   = omap_mpuio_suspend_late,
1163 
        .resume_early   = omap_mpuio_resume_early,
1164 
        .driver         = {
1165 
                .name   = "mpuio",
1166 
        },
1167 
};
1168 
 
1169 
static struct platform_device omap_mpuio_device = {
1170 
        .name           = "mpuio",
1171 
        .id             = -1,
1172 
        .dev = {
1173 
                .driver = &omap_mpuio_driver.driver,
1174 
        }
1175 
        /* could list the /proc/iomem resources */
1176 
};
1177 
 
1178 
static inline void mpuio_init(void)
1179 
{
1180 
        platform_set_drvdata(&omap_mpuio_device, &gpio_bank_1610[0]);
1181 
 
1182 
        if (platform_driver_register(&omap_mpuio_driver) == 0)
1183 
                (void) platform_device_register(&omap_mpuio_device);
1184 
}
1185 
 
1186 
#else
1187 
static inline void mpuio_init(void) {}
1188 
#endif  /* 16xx */
1189 
 
1190 
#else
1191 
 
1192 
extern struct irq_chip mpuio_irq_chip;
1193 
 
1194 
#define bank_is_mpuio(bank)     0
1195 
static inline void mpuio_init(void) {}
1196 
 
1197 
#endif
1198 
 
1199 
/*---------------------------------------------------------------------*/
1200 
 
1201 
static int initialized;
1202 
static struct clk * gpio_ick;
1203 
static struct clk * gpio_fck;
1204 
 
1205 
#ifdef CONFIG_ARCH_OMAP2430
1206 
static struct clk * gpio5_ick;
1207 
static struct clk * gpio5_fck;
1208 
#endif
1209 
 
1210 
static int __init _omap_gpio_init(void)
1211 
{
1212 
        int i;
1213 
        struct gpio_bank *bank;
1214 
 
1215 
        initialized = 1;
1216 
 
1217 
        if (cpu_is_omap15xx()) {
1218 
                gpio_ick = clk_get(NULL, "arm_gpio_ck");
1219 
                if (IS_ERR(gpio_ick))
1220 
                        printk("Could not get arm_gpio_ck\n");
1221 
                else
1222 
                        clk_enable(gpio_ick);
1223 
        }
1224 
        if (cpu_is_omap24xx()) {
1225 
                gpio_ick = clk_get(NULL, "gpios_ick");
1226 
                if (IS_ERR(gpio_ick))
1227 
                        printk("Could not get gpios_ick\n");
1228 
                else
1229 
                        clk_enable(gpio_ick);
1230 
                gpio_fck = clk_get(NULL, "gpios_fck");
1231 
                if (IS_ERR(gpio_fck))
1232 
                        printk("Could not get gpios_fck\n");
1233 
                else
1234 
                        clk_enable(gpio_fck);
1235 
 
1236 
                /*
1237 
                 * On 2430 GPIO 5 uses CORE L4 ICLK
1238 
                 */
1239 
#ifdef CONFIG_ARCH_OMAP2430
1240 
                if (cpu_is_omap2430()) {
1241 
                        gpio5_ick = clk_get(NULL, "gpio5_ick");
1242 
                        if (IS_ERR(gpio5_ick))
1243 
                                printk("Could not get gpio5_ick\n");
1244 
                        else
1245 
                                clk_enable(gpio5_ick);
1246 
                        gpio5_fck = clk_get(NULL, "gpio5_fck");
1247 
                        if (IS_ERR(gpio5_fck))
1248 
                                printk("Could not get gpio5_fck\n");
1249 
                        else
1250 
                                clk_enable(gpio5_fck);
1251 
                }
1252 
#endif
1253 
}
1254 
 
1255 
#ifdef CONFIG_ARCH_OMAP15XX
1256 
        if (cpu_is_omap15xx()) {
1257 
                printk(KERN_INFO "OMAP1510 GPIO hardware\n");
1258 
                gpio_bank_count = 2;
1259 
                gpio_bank = gpio_bank_1510;
1260 
        }
1261 
#endif
1262 
#if defined(CONFIG_ARCH_OMAP16XX)
1263 
        if (cpu_is_omap16xx()) {
1264 
                u32 rev;
1265 
 
1266 
                gpio_bank_count = 5;
1267 
                gpio_bank = gpio_bank_1610;
1268 
                rev = omap_readw(gpio_bank[1].base + OMAP1610_GPIO_REVISION);
1269 
                printk(KERN_INFO "OMAP GPIO hardware version %d.%d\n",
1270 
                       (rev >> 4) & 0x0f, rev & 0x0f);
1271 
        }
1272 
#endif
1273 
#ifdef CONFIG_ARCH_OMAP730
1274 
        if (cpu_is_omap730()) {
1275 
                printk(KERN_INFO "OMAP730 GPIO hardware\n");
1276 
                gpio_bank_count = 7;
1277 
                gpio_bank = gpio_bank_730;
1278 
        }
1279 
#endif
1280 
 
1281 
#ifdef CONFIG_ARCH_OMAP24XX
1282 
        if (cpu_is_omap242x()) {
1283 
                int rev;
1284 
 
1285 
                gpio_bank_count = 4;
1286 
                gpio_bank = gpio_bank_242x;
1287 
                rev = omap_readl(gpio_bank[0].base + OMAP24XX_GPIO_REVISION);
1288 
                printk(KERN_INFO "OMAP242x GPIO hardware version %d.%d\n",
1289 
                        (rev >> 4) & 0x0f, rev & 0x0f);
1290 
        }
1291 
        if (cpu_is_omap243x()) {
1292 
                int rev;
1293 
 
1294 
                gpio_bank_count = 5;
1295 
                gpio_bank = gpio_bank_243x;
1296 
                rev = omap_readl(gpio_bank[0].base + OMAP24XX_GPIO_REVISION);
1297 
                printk(KERN_INFO "OMAP243x GPIO hardware version %d.%d\n",
1298 
                        (rev >> 4) & 0x0f, rev & 0x0f);
1299 
        }
1300 
#endif
1301 
        for (i = 0; i < gpio_bank_count; i++) {
1302 
                int j, gpio_count = 16;
1303 
 
1304 
                bank = &gpio_bank[i];
1305 
                bank->reserved_map = 0;
1306 
                bank->base = IO_ADDRESS(bank->base);
1307 
                spin_lock_init(&bank->lock);
1308 
                if (bank_is_mpuio(bank))
1309 
                        omap_writew(0xFFFF, OMAP_MPUIO_BASE + OMAP_MPUIO_GPIO_MASKIT);
1310 
#ifdef CONFIG_ARCH_OMAP15XX
1311 
                if (bank->method == METHOD_GPIO_1510) {
1312 
                        __raw_writew(0xffff, bank->base + OMAP1510_GPIO_INT_MASK);
1313 
                        __raw_writew(0x0000, bank->base + OMAP1510_GPIO_INT_STATUS);
1314 
                }
1315 
#endif
1316 
#if defined(CONFIG_ARCH_OMAP16XX)
1317 
                if (bank->method == METHOD_GPIO_1610) {
1318 
                        __raw_writew(0x0000, bank->base + OMAP1610_GPIO_IRQENABLE1);
1319 
                        __raw_writew(0xffff, bank->base + OMAP1610_GPIO_IRQSTATUS1);
1320 
                        __raw_writew(0x0014, bank->base + OMAP1610_GPIO_SYSCONFIG);
1321 
                }
1322 
#endif
1323 
#ifdef CONFIG_ARCH_OMAP730
1324 
                if (bank->method == METHOD_GPIO_730) {
1325 
                        __raw_writel(0xffffffff, bank->base + OMAP730_GPIO_INT_MASK);
1326 
                        __raw_writel(0x00000000, bank->base + OMAP730_GPIO_INT_STATUS);
1327 
 
1328 
                        gpio_count = 32; /* 730 has 32-bit GPIOs */
1329 
                }
1330 
#endif
1331 
#ifdef CONFIG_ARCH_OMAP24XX
1332 
                if (bank->method == METHOD_GPIO_24XX) {
1333 
                        static const u32 non_wakeup_gpios[] = {
1334 
                                0xe203ffc0, 0x08700040
1335 
                        };
1336 
 
1337 
                        __raw_writel(0x00000000, bank->base + OMAP24XX_GPIO_IRQENABLE1);
1338 
                        __raw_writel(0xffffffff, bank->base + OMAP24XX_GPIO_IRQSTATUS1);
1339 
                        __raw_writew(0x0015, bank->base + OMAP24XX_GPIO_SYSCONFIG);
1340 
 
1341 
                        /* Initialize interface clock ungated, module enabled */
1342 
                        __raw_writel(0, bank->base + OMAP24XX_GPIO_CTRL);
1343 
                        if (i < ARRAY_SIZE(non_wakeup_gpios))
1344 
                                bank->non_wakeup_gpios = non_wakeup_gpios[i];
1345 
                        gpio_count = 32;
1346 
                }
1347 
#endif
1348 
                for (j = bank->virtual_irq_start;
1349 
                     j < bank->virtual_irq_start + gpio_count; j++) {
1350 
                        set_irq_chip_data(j, bank);
1351 
                        if (bank_is_mpuio(bank))
1352 
                                set_irq_chip(j, &mpuio_irq_chip);
1353 
                        else
1354 
                                set_irq_chip(j, &gpio_irq_chip);
1355 
                        set_irq_handler(j, handle_simple_irq);
1356 
                        set_irq_flags(j, IRQF_VALID);
1357 
                }
1358 
                set_irq_chained_handler(bank->irq, gpio_irq_handler);
1359 
                set_irq_data(bank->irq, bank);
1360 
        }
1361 
 
1362 
        /* Enable system clock for GPIO module.
1363 
         * The CAM_CLK_CTRL *is* really the right place. */
1364 
        if (cpu_is_omap16xx())
1365 
                omap_writel(omap_readl(ULPD_CAM_CLK_CTRL) | 0x04, ULPD_CAM_CLK_CTRL);
1366 
 
1367 
#ifdef CONFIG_ARCH_OMAP24XX
1368 
        /* Enable autoidle for the OCP interface */
1369 
        if (cpu_is_omap24xx())
1370 
                omap_writel(1 << 0, 0x48019010);
1371 
#endif
1372 
 
1373 
        return 0;
1374 
}
1375 
 
1376 
#if defined (CONFIG_ARCH_OMAP16XX) || defined (CONFIG_ARCH_OMAP24XX)
1377 
static int omap_gpio_suspend(struct sys_device *dev, pm_message_t mesg)
1378 
{
1379 
        int i;
1380 
 
1381 
        if (!cpu_is_omap24xx() && !cpu_is_omap16xx())
1382 
                return 0;
1383 
 
1384 
        for (i = 0; i < gpio_bank_count; i++) {
1385 
                struct gpio_bank *bank = &gpio_bank[i];
1386 
                void __iomem *wake_status;
1387 
                void __iomem *wake_clear;
1388 
                void __iomem *wake_set;
1389 
 
1390 
                switch (bank->method) {
1391 
#ifdef CONFIG_ARCH_OMAP16XX
1392 
                case METHOD_GPIO_1610:
1393 
                        wake_status = bank->base + OMAP1610_GPIO_WAKEUPENABLE;
1394 
                        wake_clear = bank->base + OMAP1610_GPIO_CLEAR_WAKEUPENA;
1395 
                        wake_set = bank->base + OMAP1610_GPIO_SET_WAKEUPENA;
1396 
                        break;
1397 
#endif
1398 
#ifdef CONFIG_ARCH_OMAP24XX
1399 
                case METHOD_GPIO_24XX:
1400 
                        wake_status = bank->base + OMAP24XX_GPIO_SETWKUENA;
1401 
                        wake_clear = bank->base + OMAP24XX_GPIO_CLEARWKUENA;
1402 
                        wake_set = bank->base + OMAP24XX_GPIO_SETWKUENA;
1403 
                        break;
1404 
#endif
1405 
                default:
1406 
                        continue;
1407 
                }
1408 
 
1409 
                spin_lock(&bank->lock);
1410 
                bank->saved_wakeup = __raw_readl(wake_status);
1411 
                __raw_writel(0xffffffff, wake_clear);
1412 
                __raw_writel(bank->suspend_wakeup, wake_set);
1413 
                spin_unlock(&bank->lock);
1414 
        }
1415 
 
1416 
        return 0;
1417 
}
1418 
 
1419 
static int omap_gpio_resume(struct sys_device *dev)
1420 
{
1421 
        int i;
1422 
 
1423 
        if (!cpu_is_omap24xx() && !cpu_is_omap16xx())
1424 
                return 0;
1425 
 
1426 
        for (i = 0; i < gpio_bank_count; i++) {
1427 
                struct gpio_bank *bank = &gpio_bank[i];
1428 
                void __iomem *wake_clear;
1429 
                void __iomem *wake_set;
1430 
 
1431 
                switch (bank->method) {
1432 
#ifdef CONFIG_ARCH_OMAP16XX
1433 
                case METHOD_GPIO_1610:
1434 
                        wake_clear = bank->base + OMAP1610_GPIO_CLEAR_WAKEUPENA;
1435 
                        wake_set = bank->base + OMAP1610_GPIO_SET_WAKEUPENA;
1436 
                        break;
1437 
#endif
1438 
#ifdef CONFIG_ARCH_OMAP24XX
1439 
                case METHOD_GPIO_24XX:
1440 
                        wake_clear = bank->base + OMAP24XX_GPIO_CLEARWKUENA;
1441 
                        wake_set = bank->base + OMAP24XX_GPIO_SETWKUENA;
1442 
                        break;
1443 
#endif
1444 
                default:
1445 
                        continue;
1446 
                }
1447 
 
1448 
                spin_lock(&bank->lock);
1449 
                __raw_writel(0xffffffff, wake_clear);
1450 
                __raw_writel(bank->saved_wakeup, wake_set);
1451 
                spin_unlock(&bank->lock);
1452 
        }
1453 
 
1454 
        return 0;
1455 
}
1456 
 
1457 
static struct sysdev_class omap_gpio_sysclass = {
1458 
        set_kset_name("gpio"),
1459 
        .suspend        = omap_gpio_suspend,
1460 
        .resume         = omap_gpio_resume,
1461 
};
1462 
 
1463 
static struct sys_device omap_gpio_device = {
1464 
        .id             = 0,
1465 
        .cls            = &omap_gpio_sysclass,
1466 
};
1467 
 
1468 
#endif
1469 
 
1470 
#ifdef CONFIG_ARCH_OMAP24XX
1471 
 
1472 
static int workaround_enabled;
1473 
 
1474 
void omap2_gpio_prepare_for_retention(void)
1475 
{
1476 
        int i, c = 0;
1477 
 
1478 
        /* Remove triggering for all non-wakeup GPIOs.  Otherwise spurious
1479 
         * IRQs will be generated.  See OMAP2420 Errata item 1.101. */
1480 
        for (i = 0; i < gpio_bank_count; i++) {
1481 
                struct gpio_bank *bank = &gpio_bank[i];
1482 
                u32 l1, l2;
1483 
 
1484 
                if (!(bank->enabled_non_wakeup_gpios))
1485 
                        continue;
1486 
                bank->saved_datain = __raw_readl(bank->base + OMAP24XX_GPIO_DATAIN);
1487 
                l1 = __raw_readl(bank->base + OMAP24XX_GPIO_FALLINGDETECT);
1488 
                l2 = __raw_readl(bank->base + OMAP24XX_GPIO_RISINGDETECT);
1489 
                bank->saved_fallingdetect = l1;
1490 
                bank->saved_risingdetect = l2;
1491 
                l1 &= ~bank->enabled_non_wakeup_gpios;
1492 
                l2 &= ~bank->enabled_non_wakeup_gpios;
1493 
                __raw_writel(l1, bank->base + OMAP24XX_GPIO_FALLINGDETECT);
1494 
                __raw_writel(l2, bank->base + OMAP24XX_GPIO_RISINGDETECT);
1495 
                c++;
1496 
        }
1497 
        if (!c) {
1498 
                workaround_enabled = 0;
1499 
                return;
1500 
        }
1501 
        workaround_enabled = 1;
1502 
}
1503 
 
1504 
void omap2_gpio_resume_after_retention(void)
1505 
{
1506 
        int i;
1507 
 
1508 
        if (!workaround_enabled)
1509 
                return;
1510 
        for (i = 0; i < gpio_bank_count; i++) {
1511 
                struct gpio_bank *bank = &gpio_bank[i];
1512 
                u32 l;
1513 
 
1514 
                if (!(bank->enabled_non_wakeup_gpios))
1515 
                        continue;
1516 
                __raw_writel(bank->saved_fallingdetect,
1517 
                                 bank->base + OMAP24XX_GPIO_FALLINGDETECT);
1518 
                __raw_writel(bank->saved_risingdetect,
1519 
                                 bank->base + OMAP24XX_GPIO_RISINGDETECT);
1520 
                /* Check if any of the non-wakeup interrupt GPIOs have changed
1521 
                 * state.  If so, generate an IRQ by software.  This is
1522 
                 * horribly racy, but it's the best we can do to work around
1523 
                 * this silicon bug. */
1524 
                l = __raw_readl(bank->base + OMAP24XX_GPIO_DATAIN);
1525 
                l ^= bank->saved_datain;
1526 
                l &= bank->non_wakeup_gpios;
1527 
                if (l) {
1528 
                        u32 old0, old1;
1529 
 
1530 
                        old0 = __raw_readl(bank->base + OMAP24XX_GPIO_LEVELDETECT0);
1531 
                        old1 = __raw_readl(bank->base + OMAP24XX_GPIO_LEVELDETECT1);
1532 
                        __raw_writel(old0 | l, bank->base + OMAP24XX_GPIO_LEVELDETECT0);
1533 
                        __raw_writel(old1 | l, bank->base + OMAP24XX_GPIO_LEVELDETECT1);
1534 
                        __raw_writel(old0, bank->base + OMAP24XX_GPIO_LEVELDETECT0);
1535 
                        __raw_writel(old1, bank->base + OMAP24XX_GPIO_LEVELDETECT1);
1536 
                }
1537 
        }
1538 
 
1539 
}
1540 
 
1541 
#endif
1542 
 
1543 
/*
1544 
 * This may get called early from board specific init
1545 
 * for boards that have interrupts routed via FPGA.
1546 
 */
1547 
int __init omap_gpio_init(void)
1548 
{
1549 
        if (!initialized)
1550 
                return _omap_gpio_init();
1551 
        else
1552 
                return 0;
1553 
}
1554 
 
1555 
static int __init omap_gpio_sysinit(void)
1556 
{
1557 
        int ret = 0;
1558 
 
1559 
        if (!initialized)
1560 
                ret = _omap_gpio_init();
1561 
 
1562 
        mpuio_init();
1563 
 
1564 
#if defined(CONFIG_ARCH_OMAP16XX) || defined(CONFIG_ARCH_OMAP24XX)
1565 
        if (cpu_is_omap16xx() || cpu_is_omap24xx()) {
1566 
                if (ret == 0) {
1567 
                        ret = sysdev_class_register(&omap_gpio_sysclass);
1568 
                        if (ret == 0)
1569 
                                ret = sysdev_register(&omap_gpio_device);
1570 
                }
1571 
        }
1572 
#endif
1573 
 
1574 
        return ret;
1575 
}
1576 
 
1577 
EXPORT_SYMBOL(omap_request_gpio);
1578 
EXPORT_SYMBOL(omap_free_gpio);
1579 
EXPORT_SYMBOL(omap_set_gpio_direction);
1580 
EXPORT_SYMBOL(omap_set_gpio_dataout);
1581 
EXPORT_SYMBOL(omap_get_gpio_datain);
1582 
 
1583 
arch_initcall(omap_gpio_sysinit);
1584 
 
1585 
 
1586 
#ifdef  CONFIG_DEBUG_FS
1587 
 
1588 
#include <linux/debugfs.h>
1589 
#include <linux/seq_file.h>
1590 
 
1591 
static int gpio_is_input(struct gpio_bank *bank, int mask)
1592 
{
1593 
        void __iomem *reg = bank->base;
1594 
 
1595 
        switch (bank->method) {
1596 
        case METHOD_MPUIO:
1597 
                reg += OMAP_MPUIO_IO_CNTL;
1598 
                break;
1599 
        case METHOD_GPIO_1510:
1600 
                reg += OMAP1510_GPIO_DIR_CONTROL;
1601 
                break;
1602 
        case METHOD_GPIO_1610:
1603 
                reg += OMAP1610_GPIO_DIRECTION;
1604 
                break;
1605 
        case METHOD_GPIO_730:
1606 
                reg += OMAP730_GPIO_DIR_CONTROL;
1607 
                break;
1608 
        case METHOD_GPIO_24XX:
1609 
                reg += OMAP24XX_GPIO_OE;
1610 
                break;
1611 
        }
1612 
        return __raw_readl(reg) & mask;
1613 
}
1614 
 
1615 
 
1616 
static int dbg_gpio_show(struct seq_file *s, void *unused)
1617 
{
1618 
        unsigned        i, j, gpio;
1619 
 
1620 
        for (i = 0, gpio = 0; i < gpio_bank_count; i++) {
1621 
                struct gpio_bank        *bank = gpio_bank + i;
1622 
                unsigned                bankwidth = 16;
1623 
                u32                     mask = 1;
1624 
 
1625 
                if (bank_is_mpuio(bank))
1626 
                        gpio = OMAP_MPUIO(0);
1627 
                else if (cpu_is_omap24xx() || cpu_is_omap730())
1628 
                        bankwidth = 32;
1629 
 
1630 
                for (j = 0; j < bankwidth; j++, gpio++, mask <<= 1) {
1631 
                        unsigned        irq, value, is_in, irqstat;
1632 
 
1633 
                        if (!(bank->reserved_map & mask))
1634 
                                continue;
1635 
 
1636 
                        irq = bank->virtual_irq_start + j;
1637 
                        value = omap_get_gpio_datain(gpio);
1638 
                        is_in = gpio_is_input(bank, mask);
1639 
 
1640 
                        if (bank_is_mpuio(bank))
1641 
                                seq_printf(s, "MPUIO %2d: ", j);
1642 
                        else
1643 
                                seq_printf(s, "GPIO %3d: ", gpio);
1644 
                        seq_printf(s, "%s %s",
1645 
                                        is_in ? "in " : "out",
1646 
                                        value ? "hi"  : "lo");
1647 
 
1648 
                        irqstat = irq_desc[irq].status;
1649 
                        if (is_in && ((bank->suspend_wakeup & mask)
1650 
                                        || irqstat & IRQ_TYPE_SENSE_MASK)) {
1651 
                                char    *trigger = NULL;
1652 
 
1653 
                                switch (irqstat & IRQ_TYPE_SENSE_MASK) {
1654 
                                case IRQ_TYPE_EDGE_FALLING:
1655 
                                        trigger = "falling";
1656 
                                        break;
1657 
                                case IRQ_TYPE_EDGE_RISING:
1658 
                                        trigger = "rising";
1659 
                                        break;
1660 
                                case IRQ_TYPE_EDGE_BOTH:
1661 
                                        trigger = "bothedge";
1662 
                                        break;
1663 
                                case IRQ_TYPE_LEVEL_LOW:
1664 
                                        trigger = "low";
1665 
                                        break;
1666 
                                case IRQ_TYPE_LEVEL_HIGH:
1667 
                                        trigger = "high";
1668 
                                        break;
1669 
                                case IRQ_TYPE_NONE:
1670 
                                        trigger = "(unspecified)";
1671 
                                        break;
1672 
                                }
1673 
                                seq_printf(s, ", irq-%d %s%s",
1674 
                                                irq, trigger,
1675 
                                                (bank->suspend_wakeup & mask)
1676 
                                                        ? " wakeup" : "");
1677 
                        }
1678 
                        seq_printf(s, "\n");
1679 
                }
1680 
 
1681 
                if (bank_is_mpuio(bank)) {
1682 
                        seq_printf(s, "\n");
1683 
                        gpio = 0;
1684 
                }
1685 
        }
1686 
        return 0;
1687 
}
1688 
 
1689 
static int dbg_gpio_open(struct inode *inode, struct file *file)
1690 
{
1691 
        return single_open(file, dbg_gpio_show, &inode->i_private);
1692 
}
1693 
 
1694 
static const struct file_operations debug_fops = {
1695 
        .open           = dbg_gpio_open,
1696 
        .read           = seq_read,
1697 
        .llseek         = seq_lseek,
1698 
        .release        = single_release,
1699 
};
1700 
 
1701 
static int __init omap_gpio_debuginit(void)
1702 
{
1703 
        (void) debugfs_create_file("omap_gpio", S_IRUGO,
1704 
                                        NULL, NULL, &debug_fops);
1705 
        return 0;
1706 
}
1707 
late_initcall(omap_gpio_debuginit);
1708 
#endif

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