| 1 |
3 |
xianfeng |
Running Linux on the Voyager Architecture
|
| 2 |
|
|
=========================================
|
| 3 |
|
|
|
| 4 |
|
|
For full details and current project status, see
|
| 5 |
|
|
|
| 6 |
|
|
http://www.hansenpartnership.com/voyager
|
| 7 |
|
|
|
| 8 |
|
|
The voyager architecture was designed by NCR in the mid 80s to be a
|
| 9 |
|
|
fully SMP capable RAS computing architecture built around intel's 486
|
| 10 |
|
|
chip set. The voyager came in three levels of architectural
|
| 11 |
|
|
sophistication: 3,4 and 5 --- 1 and 2 never made it out of prototype.
|
| 12 |
|
|
The linux patches support only the Level 5 voyager architecture (any
|
| 13 |
|
|
machine class 3435 and above).
|
| 14 |
|
|
|
| 15 |
|
|
The Voyager Architecture
|
| 16 |
|
|
------------------------
|
| 17 |
|
|
|
| 18 |
|
|
Voyager machines consist of a Baseboard with a 386 diagnostic
|
| 19 |
|
|
processor, a Power Supply Interface (PSI) a Primary and possibly
|
| 20 |
|
|
Secondary Microchannel bus and between 2 and 20 voyager slots. The
|
| 21 |
|
|
voyager slots can be populated with memory and cpu cards (up to 4GB
|
| 22 |
|
|
memory and from 1 486 to 32 Pentium Pro processors). Internally, the
|
| 23 |
|
|
voyager has a dual arbitrated system bus and a configuration and test
|
| 24 |
|
|
bus (CAT). The voyager bus speed is 40MHz. Therefore (since all
|
| 25 |
|
|
voyager cards are dual ported for each system bus) the maximum
|
| 26 |
|
|
transfer rate is 320Mb/s but only if you have your slot configuration
|
| 27 |
|
|
tuned (only memory cards can communicate with both busses at once, CPU
|
| 28 |
|
|
cards utilise them one at a time).
|
| 29 |
|
|
|
| 30 |
|
|
Voyager SMP
|
| 31 |
|
|
-----------
|
| 32 |
|
|
|
| 33 |
|
|
Since voyager was the first intel based SMP system, it is slightly
|
| 34 |
|
|
more primitive than the Intel IO-APIC approach to SMP. Voyager allows
|
| 35 |
|
|
arbitrary interrupt routing (including processor affinity routing) of
|
| 36 |
|
|
all 16 PC type interrupts. However it does this by using a modified
|
| 37 |
|
|
5259 master/slave chip set instead of an APIC bus. Additionally,
|
| 38 |
|
|
voyager supports Cross Processor Interrupts (CPI) equivalent to the
|
| 39 |
|
|
APIC IPIs. There are two routed voyager interrupt lines provided to
|
| 40 |
|
|
each slot.
|
| 41 |
|
|
|
| 42 |
|
|
Processor Cards
|
| 43 |
|
|
---------------
|
| 44 |
|
|
|
| 45 |
|
|
These come in single, dyadic and quad configurations (the quads are
|
| 46 |
|
|
problematic--see later). The maximum configuration is 8 quad cards
|
| 47 |
|
|
for 32 way SMP.
|
| 48 |
|
|
|
| 49 |
|
|
Quad Processors
|
| 50 |
|
|
---------------
|
| 51 |
|
|
|
| 52 |
|
|
Because voyager only supplies two interrupt lines to each Processor
|
| 53 |
|
|
card, the Quad processors have to be configured (and Bootstrapped) in
|
| 54 |
|
|
as a pair of Master/Slave processors.
|
| 55 |
|
|
|
| 56 |
|
|
In fact, most Quad cards only accept one VIC interrupt line, so they
|
| 57 |
|
|
have one interrupt handling processor (called the VIC extended
|
| 58 |
|
|
processor) and three non-interrupt handling processors.
|
| 59 |
|
|
|
| 60 |
|
|
Current Status
|
| 61 |
|
|
--------------
|
| 62 |
|
|
|
| 63 |
|
|
The System will boot on Mono, Dyad and Quad cards. There was
|
| 64 |
|
|
originally a Quad boot problem which has been fixed by proper gdt
|
| 65 |
|
|
alignment in the initial boot loader. If you still cannot get your
|
| 66 |
|
|
voyager system to boot, email me at:
|
| 67 |
|
|
|
| 68 |
|
|
|
| 69 |
|
|
|
| 70 |
|
|
|
| 71 |
|
|
The Quad cards now support using the separate Quad CPI vectors instead
|
| 72 |
|
|
of going through the VIC mailbox system.
|
| 73 |
|
|
|
| 74 |
|
|
The Level 4 architecture (3430 and 3360 Machines) should also work
|
| 75 |
|
|
fine.
|
| 76 |
|
|
|
| 77 |
|
|
Dump Switch
|
| 78 |
|
|
-----------
|
| 79 |
|
|
|
| 80 |
|
|
The voyager dump switch sends out a broadcast NMI which the voyager
|
| 81 |
|
|
code intercepts and does a task dump.
|
| 82 |
|
|
|
| 83 |
|
|
Power Switch
|
| 84 |
|
|
------------
|
| 85 |
|
|
|
| 86 |
|
|
The front panel power switch is intercepted by the kernel and should
|
| 87 |
|
|
cause a system shutdown and power off.
|
| 88 |
|
|
|
| 89 |
|
|
A Note About Mixed CPU Systems
|
| 90 |
|
|
------------------------------
|
| 91 |
|
|
|
| 92 |
|
|
Linux isn't designed to handle mixed CPU systems very well. In order
|
| 93 |
|
|
to get everything going you *must* make sure that your lowest
|
| 94 |
|
|
capability CPU is used for booting. Also, mixing CPU classes
|
| 95 |
|
|
(e.g. 486 and 586) is really not going to work very well at all.
|
