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xianfeng |
Most of the text from Keith Owens, hacked by AK
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x86_64 page size (PAGE_SIZE) is 4K.
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Like all other architectures, x86_64 has a kernel stack for every
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active thread. These thread stacks are THREAD_SIZE (2*PAGE_SIZE) big.
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These stacks contain useful data as long as a thread is alive or a
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zombie. While the thread is in user space the kernel stack is empty
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except for the thread_info structure at the bottom.
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In addition to the per thread stacks, there are specialized stacks
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associated with each CPU. These stacks are only used while the kernel
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is in control on that CPU; when a CPU returns to user space the
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specialized stacks contain no useful data. The main CPU stacks are:
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* Interrupt stack. IRQSTACKSIZE
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Used for external hardware interrupts. If this is the first external
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hardware interrupt (i.e. not a nested hardware interrupt) then the
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kernel switches from the current task to the interrupt stack. Like
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the split thread and interrupt stacks on i386 (with CONFIG_4KSTACKS),
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this gives more room for kernel interrupt processing without having
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to increase the size of every per thread stack.
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The interrupt stack is also used when processing a softirq.
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Switching to the kernel interrupt stack is done by software based on a
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per CPU interrupt nest counter. This is needed because x86-64 "IST"
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hardware stacks cannot nest without races.
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x86_64 also has a feature which is not available on i386, the ability
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to automatically switch to a new stack for designated events such as
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double fault or NMI, which makes it easier to handle these unusual
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events on x86_64. This feature is called the Interrupt Stack Table
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(IST). There can be up to 7 IST entries per CPU. The IST code is an
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index into the Task State Segment (TSS). The IST entries in the TSS
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point to dedicated stacks; each stack can be a different size.
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An IST is selected by a non-zero value in the IST field of an
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interrupt-gate descriptor. When an interrupt occurs and the hardware
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loads such a descriptor, the hardware automatically sets the new stack
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pointer based on the IST value, then invokes the interrupt handler. If
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software wants to allow nested IST interrupts then the handler must
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adjust the IST values on entry to and exit from the interrupt handler.
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(This is occasionally done, e.g. for debug exceptions.)
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Events with different IST codes (i.e. with different stacks) can be
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nested. For example, a debug interrupt can safely be interrupted by an
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NMI. arch/x86_64/kernel/entry.S::paranoidentry adjusts the stack
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pointers on entry to and exit from all IST events, in theory allowing
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IST events with the same code to be nested. However in most cases, the
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stack size allocated to an IST assumes no nesting for the same code.
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If that assumption is ever broken then the stacks will become corrupt.
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The currently assigned IST stacks are :-
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* STACKFAULT_STACK. EXCEPTION_STKSZ (PAGE_SIZE).
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Used for interrupt 12 - Stack Fault Exception (#SS).
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This allows the CPU to recover from invalid stack segments. Rarely
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happens.
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* DOUBLEFAULT_STACK. EXCEPTION_STKSZ (PAGE_SIZE).
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Used for interrupt 8 - Double Fault Exception (#DF).
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Invoked when handling one exception causes another exception. Happens
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when the kernel is very confused (e.g. kernel stack pointer corrupt).
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Using a separate stack allows the kernel to recover from it well enough
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in many cases to still output an oops.
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* NMI_STACK. EXCEPTION_STKSZ (PAGE_SIZE).
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Used for non-maskable interrupts (NMI).
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NMI can be delivered at any time, including when the kernel is in the
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middle of switching stacks. Using IST for NMI events avoids making
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assumptions about the previous state of the kernel stack.
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* DEBUG_STACK. DEBUG_STKSZ
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Used for hardware debug interrupts (interrupt 1) and for software
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debug interrupts (INT3).
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When debugging a kernel, debug interrupts (both hardware and
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software) can occur at any time. Using IST for these interrupts
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avoids making assumptions about the previous state of the kernel
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stack.
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* MCE_STACK. EXCEPTION_STKSZ (PAGE_SIZE).
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Used for interrupt 18 - Machine Check Exception (#MC).
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MCE can be delivered at any time, including when the kernel is in the
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middle of switching stacks. Using IST for MCE events avoids making
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assumptions about the previous state of the kernel stack.
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For more details see the Intel IA32 or AMD AMD64 architecture manuals.
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