1 |
3 |
xianfeng |
/*
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2 |
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* linux/arch/alpha/kernel/time.c
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3 |
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*
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4 |
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* Copyright (C) 1991, 1992, 1995, 1999, 2000 Linus Torvalds
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5 |
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*
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* This file contains the PC-specific time handling details:
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* reading the RTC at bootup, etc..
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* 1994-07-02 Alan Modra
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* fixed set_rtc_mmss, fixed time.year for >= 2000, new mktime
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* 1995-03-26 Markus Kuhn
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* fixed 500 ms bug at call to set_rtc_mmss, fixed DS12887
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* precision CMOS clock update
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* 1997-09-10 Updated NTP code according to technical memorandum Jan '96
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* "A Kernel Model for Precision Timekeeping" by Dave Mills
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* 1997-01-09 Adrian Sun
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* use interval timer if CONFIG_RTC=y
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* 1997-10-29 John Bowman (bowman@math.ualberta.ca)
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* fixed tick loss calculation in timer_interrupt
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* (round system clock to nearest tick instead of truncating)
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* fixed algorithm in time_init for getting time from CMOS clock
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* 1999-04-16 Thorsten Kranzkowski (dl8bcu@gmx.net)
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* fixed algorithm in do_gettimeofday() for calculating the precise time
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23 |
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* from processor cycle counter (now taking lost_ticks into account)
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* 2000-08-13 Jan-Benedict Glaw <jbglaw@lug-owl.de>
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* Fixed time_init to be aware of epoches != 1900. This prevents
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* booting up in 2048 for me;) Code is stolen from rtc.c.
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* 2003-06-03 R. Scott Bailey <scott.bailey@eds.com>
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* Tighten sanity in time_init from 1% (10,000 PPM) to 250 PPM
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*/
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#include <linux/errno.h>
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#include <linux/module.h>
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#include <linux/sched.h>
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#include <linux/kernel.h>
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#include <linux/param.h>
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#include <linux/string.h>
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#include <linux/mm.h>
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#include <linux/delay.h>
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#include <linux/ioport.h>
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#include <linux/irq.h>
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#include <linux/interrupt.h>
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#include <linux/init.h>
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#include <linux/bcd.h>
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#include <linux/profile.h>
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#include <asm/uaccess.h>
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#include <asm/io.h>
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#include <asm/hwrpb.h>
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#include <asm/8253pit.h>
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#include <linux/mc146818rtc.h>
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#include <linux/time.h>
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#include <linux/timex.h>
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#include "proto.h"
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#include "irq_impl.h"
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static int set_rtc_mmss(unsigned long);
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DEFINE_SPINLOCK(rtc_lock);
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EXPORT_SYMBOL(rtc_lock);
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#define TICK_SIZE (tick_nsec / 1000)
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/*
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* Shift amount by which scaled_ticks_per_cycle is scaled. Shifting
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* by 48 gives us 16 bits for HZ while keeping the accuracy good even
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* for large CPU clock rates.
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*/
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#define FIX_SHIFT 48
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/* lump static variables together for more efficient access: */
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static struct {
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/* cycle counter last time it got invoked */
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__u32 last_time;
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/* ticks/cycle * 2^48 */
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unsigned long scaled_ticks_per_cycle;
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/* last time the CMOS clock got updated */
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time_t last_rtc_update;
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/* partial unused tick */
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unsigned long partial_tick;
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} state;
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unsigned long est_cycle_freq;
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static inline __u32 rpcc(void)
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{
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__u32 result;
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asm volatile ("rpcc %0" : "=r"(result));
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return result;
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}
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/*
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* timer_interrupt() needs to keep up the real-time clock,
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* as well as call the "do_timer()" routine every clocktick
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*/
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irqreturn_t timer_interrupt(int irq, void *dev)
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{
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unsigned long delta;
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__u32 now;
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long nticks;
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#ifndef CONFIG_SMP
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/* Not SMP, do kernel PC profiling here. */
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profile_tick(CPU_PROFILING);
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#endif
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write_seqlock(&xtime_lock);
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/*
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* Calculate how many ticks have passed since the last update,
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* including any previous partial leftover. Save any resulting
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* fraction for the next pass.
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*/
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now = rpcc();
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delta = now - state.last_time;
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state.last_time = now;
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delta = delta * state.scaled_ticks_per_cycle + state.partial_tick;
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state.partial_tick = delta & ((1UL << FIX_SHIFT) - 1);
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nticks = delta >> FIX_SHIFT;
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while (nticks > 0) {
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do_timer(1);
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#ifndef CONFIG_SMP
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update_process_times(user_mode(get_irq_regs()));
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#endif
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nticks--;
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}
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/*
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* If we have an externally synchronized Linux clock, then update
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* CMOS clock accordingly every ~11 minutes. Set_rtc_mmss() has to be
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* called as close as possible to 500 ms before the new second starts.
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*/
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if (ntp_synced()
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&& xtime.tv_sec > state.last_rtc_update + 660
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&& xtime.tv_nsec >= 500000 - ((unsigned) TICK_SIZE) / 2
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&& xtime.tv_nsec <= 500000 + ((unsigned) TICK_SIZE) / 2) {
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int tmp = set_rtc_mmss(xtime.tv_sec);
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state.last_rtc_update = xtime.tv_sec - (tmp ? 600 : 0);
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}
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142 |
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write_sequnlock(&xtime_lock);
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return IRQ_HANDLED;
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}
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void __init
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common_init_rtc(void)
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{
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unsigned char x;
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151 |
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/* Reset periodic interrupt frequency. */
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x = CMOS_READ(RTC_FREQ_SELECT) & 0x3f;
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/* Test includes known working values on various platforms
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where 0x26 is wrong; we refuse to change those. */
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if (x != 0x26 && x != 0x25 && x != 0x19 && x != 0x06) {
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printk("Setting RTC_FREQ to 1024 Hz (%x)\n", x);
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CMOS_WRITE(0x26, RTC_FREQ_SELECT);
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}
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/* Turn on periodic interrupts. */
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x = CMOS_READ(RTC_CONTROL);
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if (!(x & RTC_PIE)) {
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printk("Turning on RTC interrupts.\n");
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x |= RTC_PIE;
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x &= ~(RTC_AIE | RTC_UIE);
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CMOS_WRITE(x, RTC_CONTROL);
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}
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(void) CMOS_READ(RTC_INTR_FLAGS);
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outb(0x36, 0x43); /* pit counter 0: system timer */
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outb(0x00, 0x40);
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outb(0x00, 0x40);
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outb(0xb6, 0x43); /* pit counter 2: speaker */
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outb(0x31, 0x42);
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outb(0x13, 0x42);
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init_rtc_irq();
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}
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/* Validate a computed cycle counter result against the known bounds for
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the given processor core. There's too much brokenness in the way of
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timing hardware for any one method to work everywhere. :-(
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Return 0 if the result cannot be trusted, otherwise return the argument. */
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static unsigned long __init
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validate_cc_value(unsigned long cc)
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{
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static struct bounds {
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unsigned int min, max;
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} cpu_hz[] __initdata = {
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[EV3_CPU] = { 50000000, 200000000 }, /* guess */
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[EV4_CPU] = { 100000000, 300000000 },
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[LCA4_CPU] = { 100000000, 300000000 }, /* guess */
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[EV45_CPU] = { 200000000, 300000000 },
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[EV5_CPU] = { 250000000, 433000000 },
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[EV56_CPU] = { 333000000, 667000000 },
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[PCA56_CPU] = { 400000000, 600000000 }, /* guess */
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[PCA57_CPU] = { 500000000, 600000000 }, /* guess */
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[EV6_CPU] = { 466000000, 600000000 },
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[EV67_CPU] = { 600000000, 750000000 },
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[EV68AL_CPU] = { 750000000, 940000000 },
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[EV68CB_CPU] = { 1000000000, 1333333333 },
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/* None of the following are shipping as of 2001-11-01. */
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[EV68CX_CPU] = { 1000000000, 1700000000 }, /* guess */
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[EV69_CPU] = { 1000000000, 1700000000 }, /* guess */
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[EV7_CPU] = { 800000000, 1400000000 }, /* guess */
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[EV79_CPU] = { 1000000000, 2000000000 }, /* guess */
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};
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/* Allow for some drift in the crystal. 10MHz is more than enough. */
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const unsigned int deviation = 10000000;
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216 |
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struct percpu_struct *cpu;
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unsigned int index;
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cpu = (struct percpu_struct *)((char*)hwrpb + hwrpb->processor_offset);
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index = cpu->type & 0xffffffff;
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/* If index out of bounds, no way to validate. */
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if (index >= ARRAY_SIZE(cpu_hz))
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return cc;
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/* If index contains no data, no way to validate. */
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228 |
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if (cpu_hz[index].max == 0)
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return cc;
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231 |
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if (cc < cpu_hz[index].min - deviation
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|| cc > cpu_hz[index].max + deviation)
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return 0;
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return cc;
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}
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238 |
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239 |
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/*
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240 |
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* Calibrate CPU clock using legacy 8254 timer/counter. Stolen from
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241 |
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* arch/i386/time.c.
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242 |
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*/
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243 |
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244 |
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#define CALIBRATE_LATCH 0xffff
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245 |
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#define TIMEOUT_COUNT 0x100000
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246 |
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247 |
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static unsigned long __init
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248 |
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calibrate_cc_with_pit(void)
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249 |
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{
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250 |
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int cc, count = 0;
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251 |
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252 |
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/* Set the Gate high, disable speaker */
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253 |
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outb((inb(0x61) & ~0x02) | 0x01, 0x61);
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254 |
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255 |
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/*
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256 |
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* Now let's take care of CTC channel 2
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257 |
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*
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258 |
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* Set the Gate high, program CTC channel 2 for mode 0,
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259 |
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* (interrupt on terminal count mode), binary count,
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260 |
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* load 5 * LATCH count, (LSB and MSB) to begin countdown.
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261 |
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*/
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262 |
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outb(0xb0, 0x43); /* binary, mode 0, LSB/MSB, Ch 2 */
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263 |
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outb(CALIBRATE_LATCH & 0xff, 0x42); /* LSB of count */
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264 |
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outb(CALIBRATE_LATCH >> 8, 0x42); /* MSB of count */
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265 |
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266 |
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cc = rpcc();
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267 |
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do {
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268 |
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count++;
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269 |
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} while ((inb(0x61) & 0x20) == 0 && count < TIMEOUT_COUNT);
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270 |
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cc = rpcc() - cc;
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271 |
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272 |
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/* Error: ECTCNEVERSET or ECPUTOOFAST. */
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273 |
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if (count <= 1 || count == TIMEOUT_COUNT)
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274 |
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return 0;
|
275 |
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|
276 |
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return ((long)cc * PIT_TICK_RATE) / (CALIBRATE_LATCH + 1);
|
277 |
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}
|
278 |
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|
279 |
|
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/* The Linux interpretation of the CMOS clock register contents:
|
280 |
|
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When the Update-In-Progress (UIP) flag goes from 1 to 0, the
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281 |
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RTC registers show the second which has precisely just started.
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282 |
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Let's hope other operating systems interpret the RTC the same way. */
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283 |
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|
284 |
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static unsigned long __init
|
285 |
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rpcc_after_update_in_progress(void)
|
286 |
|
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{
|
287 |
|
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do { } while (!(CMOS_READ(RTC_FREQ_SELECT) & RTC_UIP));
|
288 |
|
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do { } while (CMOS_READ(RTC_FREQ_SELECT) & RTC_UIP);
|
289 |
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|
290 |
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return rpcc();
|
291 |
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}
|
292 |
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|
293 |
|
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void __init
|
294 |
|
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time_init(void)
|
295 |
|
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{
|
296 |
|
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unsigned int year, mon, day, hour, min, sec, cc1, cc2, epoch;
|
297 |
|
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unsigned long cycle_freq, tolerance;
|
298 |
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long diff;
|
299 |
|
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|
300 |
|
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/* Calibrate CPU clock -- attempt #1. */
|
301 |
|
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if (!est_cycle_freq)
|
302 |
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est_cycle_freq = validate_cc_value(calibrate_cc_with_pit());
|
303 |
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|
304 |
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cc1 = rpcc();
|
305 |
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|
306 |
|
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/* Calibrate CPU clock -- attempt #2. */
|
307 |
|
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if (!est_cycle_freq) {
|
308 |
|
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cc1 = rpcc_after_update_in_progress();
|
309 |
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cc2 = rpcc_after_update_in_progress();
|
310 |
|
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est_cycle_freq = validate_cc_value(cc2 - cc1);
|
311 |
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cc1 = cc2;
|
312 |
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}
|
313 |
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|
314 |
|
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cycle_freq = hwrpb->cycle_freq;
|
315 |
|
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if (est_cycle_freq) {
|
316 |
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/* If the given value is within 250 PPM of what we calculated,
|
317 |
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accept it. Otherwise, use what we found. */
|
318 |
|
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tolerance = cycle_freq / 4000;
|
319 |
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diff = cycle_freq - est_cycle_freq;
|
320 |
|
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if (diff < 0)
|
321 |
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diff = -diff;
|
322 |
|
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if ((unsigned long)diff > tolerance) {
|
323 |
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cycle_freq = est_cycle_freq;
|
324 |
|
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printk("HWRPB cycle frequency bogus. "
|
325 |
|
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"Estimated %lu Hz\n", cycle_freq);
|
326 |
|
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} else {
|
327 |
|
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est_cycle_freq = 0;
|
328 |
|
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}
|
329 |
|
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} else if (! validate_cc_value (cycle_freq)) {
|
330 |
|
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printk("HWRPB cycle frequency bogus, "
|
331 |
|
|
"and unable to estimate a proper value!\n");
|
332 |
|
|
}
|
333 |
|
|
|
334 |
|
|
/* From John Bowman <bowman@math.ualberta.ca>: allow the values
|
335 |
|
|
to settle, as the Update-In-Progress bit going low isn't good
|
336 |
|
|
enough on some hardware. 2ms is our guess; we haven't found
|
337 |
|
|
bogomips yet, but this is close on a 500Mhz box. */
|
338 |
|
|
__delay(1000000);
|
339 |
|
|
|
340 |
|
|
sec = CMOS_READ(RTC_SECONDS);
|
341 |
|
|
min = CMOS_READ(RTC_MINUTES);
|
342 |
|
|
hour = CMOS_READ(RTC_HOURS);
|
343 |
|
|
day = CMOS_READ(RTC_DAY_OF_MONTH);
|
344 |
|
|
mon = CMOS_READ(RTC_MONTH);
|
345 |
|
|
year = CMOS_READ(RTC_YEAR);
|
346 |
|
|
|
347 |
|
|
if (!(CMOS_READ(RTC_CONTROL) & RTC_DM_BINARY) || RTC_ALWAYS_BCD) {
|
348 |
|
|
BCD_TO_BIN(sec);
|
349 |
|
|
BCD_TO_BIN(min);
|
350 |
|
|
BCD_TO_BIN(hour);
|
351 |
|
|
BCD_TO_BIN(day);
|
352 |
|
|
BCD_TO_BIN(mon);
|
353 |
|
|
BCD_TO_BIN(year);
|
354 |
|
|
}
|
355 |
|
|
|
356 |
|
|
/* PC-like is standard; used for year >= 70 */
|
357 |
|
|
epoch = 1900;
|
358 |
|
|
if (year < 20)
|
359 |
|
|
epoch = 2000;
|
360 |
|
|
else if (year >= 20 && year < 48)
|
361 |
|
|
/* NT epoch */
|
362 |
|
|
epoch = 1980;
|
363 |
|
|
else if (year >= 48 && year < 70)
|
364 |
|
|
/* Digital UNIX epoch */
|
365 |
|
|
epoch = 1952;
|
366 |
|
|
|
367 |
|
|
printk(KERN_INFO "Using epoch = %d\n", epoch);
|
368 |
|
|
|
369 |
|
|
if ((year += epoch) < 1970)
|
370 |
|
|
year += 100;
|
371 |
|
|
|
372 |
|
|
xtime.tv_sec = mktime(year, mon, day, hour, min, sec);
|
373 |
|
|
xtime.tv_nsec = 0;
|
374 |
|
|
|
375 |
|
|
wall_to_monotonic.tv_sec -= xtime.tv_sec;
|
376 |
|
|
wall_to_monotonic.tv_nsec = 0;
|
377 |
|
|
|
378 |
|
|
if (HZ > (1<<16)) {
|
379 |
|
|
extern void __you_loose (void);
|
380 |
|
|
__you_loose();
|
381 |
|
|
}
|
382 |
|
|
|
383 |
|
|
state.last_time = cc1;
|
384 |
|
|
state.scaled_ticks_per_cycle
|
385 |
|
|
= ((unsigned long) HZ << FIX_SHIFT) / cycle_freq;
|
386 |
|
|
state.last_rtc_update = 0;
|
387 |
|
|
state.partial_tick = 0L;
|
388 |
|
|
|
389 |
|
|
/* Startup the timer source. */
|
390 |
|
|
alpha_mv.init_rtc();
|
391 |
|
|
}
|
392 |
|
|
|
393 |
|
|
/*
|
394 |
|
|
* Use the cycle counter to estimate an displacement from the last time
|
395 |
|
|
* tick. Unfortunately the Alpha designers made only the low 32-bits of
|
396 |
|
|
* the cycle counter active, so we overflow on 8.2 seconds on a 500MHz
|
397 |
|
|
* part. So we can't do the "find absolute time in terms of cycles" thing
|
398 |
|
|
* that the other ports do.
|
399 |
|
|
*/
|
400 |
|
|
void
|
401 |
|
|
do_gettimeofday(struct timeval *tv)
|
402 |
|
|
{
|
403 |
|
|
unsigned long flags;
|
404 |
|
|
unsigned long sec, usec, seq;
|
405 |
|
|
unsigned long delta_cycles, delta_usec, partial_tick;
|
406 |
|
|
|
407 |
|
|
do {
|
408 |
|
|
seq = read_seqbegin_irqsave(&xtime_lock, flags);
|
409 |
|
|
|
410 |
|
|
delta_cycles = rpcc() - state.last_time;
|
411 |
|
|
sec = xtime.tv_sec;
|
412 |
|
|
usec = (xtime.tv_nsec / 1000);
|
413 |
|
|
partial_tick = state.partial_tick;
|
414 |
|
|
|
415 |
|
|
} while (read_seqretry_irqrestore(&xtime_lock, seq, flags));
|
416 |
|
|
|
417 |
|
|
#ifdef CONFIG_SMP
|
418 |
|
|
/* Until and unless we figure out how to get cpu cycle counters
|
419 |
|
|
in sync and keep them there, we can't use the rpcc tricks. */
|
420 |
|
|
delta_usec = 0;
|
421 |
|
|
#else
|
422 |
|
|
/*
|
423 |
|
|
* usec = cycles * ticks_per_cycle * 2**48 * 1e6 / (2**48 * ticks)
|
424 |
|
|
* = cycles * (s_t_p_c) * 1e6 / (2**48 * ticks)
|
425 |
|
|
* = cycles * (s_t_p_c) * 15625 / (2**42 * ticks)
|
426 |
|
|
*
|
427 |
|
|
* which, given a 600MHz cycle and a 1024Hz tick, has a
|
428 |
|
|
* dynamic range of about 1.7e17, which is less than the
|
429 |
|
|
* 1.8e19 in an unsigned long, so we are safe from overflow.
|
430 |
|
|
*
|
431 |
|
|
* Round, but with .5 up always, since .5 to even is harder
|
432 |
|
|
* with no clear gain.
|
433 |
|
|
*/
|
434 |
|
|
|
435 |
|
|
delta_usec = (delta_cycles * state.scaled_ticks_per_cycle
|
436 |
|
|
+ partial_tick) * 15625;
|
437 |
|
|
delta_usec = ((delta_usec / ((1UL << (FIX_SHIFT-6-1)) * HZ)) + 1) / 2;
|
438 |
|
|
#endif
|
439 |
|
|
|
440 |
|
|
usec += delta_usec;
|
441 |
|
|
if (usec >= 1000000) {
|
442 |
|
|
sec += 1;
|
443 |
|
|
usec -= 1000000;
|
444 |
|
|
}
|
445 |
|
|
|
446 |
|
|
tv->tv_sec = sec;
|
447 |
|
|
tv->tv_usec = usec;
|
448 |
|
|
}
|
449 |
|
|
|
450 |
|
|
EXPORT_SYMBOL(do_gettimeofday);
|
451 |
|
|
|
452 |
|
|
int
|
453 |
|
|
do_settimeofday(struct timespec *tv)
|
454 |
|
|
{
|
455 |
|
|
time_t wtm_sec, sec = tv->tv_sec;
|
456 |
|
|
long wtm_nsec, nsec = tv->tv_nsec;
|
457 |
|
|
unsigned long delta_nsec;
|
458 |
|
|
|
459 |
|
|
if ((unsigned long)tv->tv_nsec >= NSEC_PER_SEC)
|
460 |
|
|
return -EINVAL;
|
461 |
|
|
|
462 |
|
|
write_seqlock_irq(&xtime_lock);
|
463 |
|
|
|
464 |
|
|
/* The offset that is added into time in do_gettimeofday above
|
465 |
|
|
must be subtracted out here to keep a coherent view of the
|
466 |
|
|
time. Without this, a full-tick error is possible. */
|
467 |
|
|
|
468 |
|
|
#ifdef CONFIG_SMP
|
469 |
|
|
delta_nsec = 0;
|
470 |
|
|
#else
|
471 |
|
|
delta_nsec = rpcc() - state.last_time;
|
472 |
|
|
delta_nsec = (delta_nsec * state.scaled_ticks_per_cycle
|
473 |
|
|
+ state.partial_tick) * 15625;
|
474 |
|
|
delta_nsec = ((delta_nsec / ((1UL << (FIX_SHIFT-6-1)) * HZ)) + 1) / 2;
|
475 |
|
|
delta_nsec *= 1000;
|
476 |
|
|
#endif
|
477 |
|
|
|
478 |
|
|
nsec -= delta_nsec;
|
479 |
|
|
|
480 |
|
|
wtm_sec = wall_to_monotonic.tv_sec + (xtime.tv_sec - sec);
|
481 |
|
|
wtm_nsec = wall_to_monotonic.tv_nsec + (xtime.tv_nsec - nsec);
|
482 |
|
|
|
483 |
|
|
set_normalized_timespec(&xtime, sec, nsec);
|
484 |
|
|
set_normalized_timespec(&wall_to_monotonic, wtm_sec, wtm_nsec);
|
485 |
|
|
|
486 |
|
|
ntp_clear();
|
487 |
|
|
|
488 |
|
|
write_sequnlock_irq(&xtime_lock);
|
489 |
|
|
clock_was_set();
|
490 |
|
|
return 0;
|
491 |
|
|
}
|
492 |
|
|
|
493 |
|
|
EXPORT_SYMBOL(do_settimeofday);
|
494 |
|
|
|
495 |
|
|
|
496 |
|
|
/*
|
497 |
|
|
* In order to set the CMOS clock precisely, set_rtc_mmss has to be
|
498 |
|
|
* called 500 ms after the second nowtime has started, because when
|
499 |
|
|
* nowtime is written into the registers of the CMOS clock, it will
|
500 |
|
|
* jump to the next second precisely 500 ms later. Check the Motorola
|
501 |
|
|
* MC146818A or Dallas DS12887 data sheet for details.
|
502 |
|
|
*
|
503 |
|
|
* BUG: This routine does not handle hour overflow properly; it just
|
504 |
|
|
* sets the minutes. Usually you won't notice until after reboot!
|
505 |
|
|
*/
|
506 |
|
|
|
507 |
|
|
|
508 |
|
|
static int
|
509 |
|
|
set_rtc_mmss(unsigned long nowtime)
|
510 |
|
|
{
|
511 |
|
|
int retval = 0;
|
512 |
|
|
int real_seconds, real_minutes, cmos_minutes;
|
513 |
|
|
unsigned char save_control, save_freq_select;
|
514 |
|
|
|
515 |
|
|
/* irq are locally disabled here */
|
516 |
|
|
spin_lock(&rtc_lock);
|
517 |
|
|
/* Tell the clock it's being set */
|
518 |
|
|
save_control = CMOS_READ(RTC_CONTROL);
|
519 |
|
|
CMOS_WRITE((save_control|RTC_SET), RTC_CONTROL);
|
520 |
|
|
|
521 |
|
|
/* Stop and reset prescaler */
|
522 |
|
|
save_freq_select = CMOS_READ(RTC_FREQ_SELECT);
|
523 |
|
|
CMOS_WRITE((save_freq_select|RTC_DIV_RESET2), RTC_FREQ_SELECT);
|
524 |
|
|
|
525 |
|
|
cmos_minutes = CMOS_READ(RTC_MINUTES);
|
526 |
|
|
if (!(save_control & RTC_DM_BINARY) || RTC_ALWAYS_BCD)
|
527 |
|
|
BCD_TO_BIN(cmos_minutes);
|
528 |
|
|
|
529 |
|
|
/*
|
530 |
|
|
* since we're only adjusting minutes and seconds,
|
531 |
|
|
* don't interfere with hour overflow. This avoids
|
532 |
|
|
* messing with unknown time zones but requires your
|
533 |
|
|
* RTC not to be off by more than 15 minutes
|
534 |
|
|
*/
|
535 |
|
|
real_seconds = nowtime % 60;
|
536 |
|
|
real_minutes = nowtime / 60;
|
537 |
|
|
if (((abs(real_minutes - cmos_minutes) + 15)/30) & 1) {
|
538 |
|
|
/* correct for half hour time zone */
|
539 |
|
|
real_minutes += 30;
|
540 |
|
|
}
|
541 |
|
|
real_minutes %= 60;
|
542 |
|
|
|
543 |
|
|
if (abs(real_minutes - cmos_minutes) < 30) {
|
544 |
|
|
if (!(save_control & RTC_DM_BINARY) || RTC_ALWAYS_BCD) {
|
545 |
|
|
BIN_TO_BCD(real_seconds);
|
546 |
|
|
BIN_TO_BCD(real_minutes);
|
547 |
|
|
}
|
548 |
|
|
CMOS_WRITE(real_seconds,RTC_SECONDS);
|
549 |
|
|
CMOS_WRITE(real_minutes,RTC_MINUTES);
|
550 |
|
|
} else {
|
551 |
|
|
printk(KERN_WARNING
|
552 |
|
|
"set_rtc_mmss: can't update from %d to %d\n",
|
553 |
|
|
cmos_minutes, real_minutes);
|
554 |
|
|
retval = -1;
|
555 |
|
|
}
|
556 |
|
|
|
557 |
|
|
/* The following flags have to be released exactly in this order,
|
558 |
|
|
* otherwise the DS12887 (popular MC146818A clone with integrated
|
559 |
|
|
* battery and quartz) will not reset the oscillator and will not
|
560 |
|
|
* update precisely 500 ms later. You won't find this mentioned in
|
561 |
|
|
* the Dallas Semiconductor data sheets, but who believes data
|
562 |
|
|
* sheets anyway ... -- Markus Kuhn
|
563 |
|
|
*/
|
564 |
|
|
CMOS_WRITE(save_control, RTC_CONTROL);
|
565 |
|
|
CMOS_WRITE(save_freq_select, RTC_FREQ_SELECT);
|
566 |
|
|
spin_unlock(&rtc_lock);
|
567 |
|
|
|
568 |
|
|
return retval;
|
569 |
|
|
}
|