URL https://opencores.org/ocsvn/or1k_soc_on_altera_embedded_dev_kit/or1k_soc_on_altera_embedded_dev_kit/trunk

Subversion Repositories or1k_soc_on_altera_embedded_dev_kit

[/] [or1k_soc_on_altera_embedded_dev_kit/] [trunk/] [linux-2.6/] [linux-2.6.24/] [arch/] [arm/] [lib/] [io-writesl.S] - Blame information for rev 3

Line No.	Rev	Author	Line
1	3	xianfeng	`/*`
2			`* linux/arch/arm/lib/io-writesl.S`
3			`*`
4			`* Copyright (C) 1995-2000 Russell King`
5			`*`
6			`* This program is free software; you can redistribute it and/or modify`
7			`* it under the terms of the GNU General Public License version 2 as`
8			`* published by the Free Software Foundation.`
9			`*/`
10			`#include`
11			`#include`
12
13			`ENTRY(__raw_writesl)`
14			`teq r2, #0 @ do we have to check for the zero len?`
15			`moveq pc, lr`
16			`ands ip, r1, #3`
17			`bne 3f`
18
19			`subs r2, r2, #4`
20			`bmi 2f`
21			`stmfd sp!, {r4, lr}`
22			`1: ldmia r1!, {r3, r4, ip, lr}`
23			`subs r2, r2, #4`
24			`str r3, [r0, #0]`
25			`str r4, [r0, #0]`
26			`str ip, [r0, #0]`
27			`str lr, [r0, #0]`
28			`bpl 1b`
29			`ldmfd sp!, {r4, lr}`
30			`2: movs r2, r2, lsl #31`
31			`ldmcsia r1!, {r3, ip}`
32			`strcs r3, [r0, #0]`
33			`ldrne r3, [r1, #0]`
34			`strcs ip, [r0, #0]`
35			`strne r3, [r0, #0]`
36			`mov pc, lr`
37
38			`3: bic r1, r1, #3`
39			`ldr r3, [r1], #4`
40			`cmp ip, #2`
41			`blt 5f`
42			`bgt 6f`
43
44			`4: mov ip, r3, pull #16`
45			`ldr r3, [r1], #4`
46			`subs r2, r2, #1`
47			`orr ip, ip, r3, push #16`
48			`str ip, [r0]`
49			`bne 4b`
50			`mov pc, lr`
51
52			`5: mov ip, r3, pull #8`
53			`ldr r3, [r1], #4`
54			`subs r2, r2, #1`
55			`orr ip, ip, r3, push #24`
56			`str ip, [r0]`
57			`bne 5b`
58			`mov pc, lr`
59
60			`6: mov ip, r3, pull #24`
61			`ldr r3, [r1], #4`
62			`subs r2, r2, #1`
63			`orr ip, ip, r3, push #8`
64			`str ip, [r0]`
65			`bne 6b`
66			`mov pc, lr`