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[/] [or1k_soc_on_altera_embedded_dev_kit/] [trunk/] [linux-2.6/] [linux-2.6.24/] [arch/] [arm/] [mach-at91/] [at91sam9263.c] - Blame information for rev 3

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1 3 xianfeng 
/*
2 
 * arch/arm/mach-at91/at91sam9263.c
3 
 *
4 
 *  Copyright (C) 2007 Atmel Corporation.
5 
 *
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 * This program is free software; you can redistribute it and/or modify
7 
 * it under the terms of the GNU General Public License as published by
8 
 * the Free Software Foundation; either version 2 of the License, or
9 
 * (at your option) any later version.
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 *
11 
 */
12 
 
13 
#include <linux/module.h>
14 
 
15 
#include <asm/mach/arch.h>
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#include <asm/mach/map.h>
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#include <asm/arch/at91sam9263.h>
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#include <asm/arch/at91_pmc.h>
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#include <asm/arch/at91_rstc.h>
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21 
#include "generic.h"
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#include "clock.h"
23 
 
24 
static struct map_desc at91sam9263_io_desc[] __initdata = {
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        {
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                .virtual        = AT91_VA_BASE_SYS,
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                .pfn            = __phys_to_pfn(AT91_BASE_SYS),
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                .length         = SZ_16K,
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                .type           = MT_DEVICE,
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        }, {
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                .virtual        = AT91_IO_VIRT_BASE - AT91SAM9263_SRAM0_SIZE,
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                .pfn            = __phys_to_pfn(AT91SAM9263_SRAM0_BASE),
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                .length         = AT91SAM9263_SRAM0_SIZE,
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                .type           = MT_DEVICE,
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        }, {
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                .virtual        = AT91_IO_VIRT_BASE - AT91SAM9263_SRAM0_SIZE - AT91SAM9263_SRAM1_SIZE,
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                .pfn            = __phys_to_pfn(AT91SAM9263_SRAM1_BASE),
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                .length         = AT91SAM9263_SRAM1_SIZE,
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                .type           = MT_DEVICE,
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        },
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};
42 
 
43 
/* --------------------------------------------------------------------
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 *  Clocks
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 * -------------------------------------------------------------------- */
46 
 
47 
/*
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 * The peripheral clocks.
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 */
50 
static struct clk pioA_clk = {
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        .name           = "pioA_clk",
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        .pmc_mask       = 1 << AT91SAM9263_ID_PIOA,
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        .type           = CLK_TYPE_PERIPHERAL,
54 
};
55 
static struct clk pioB_clk = {
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        .name           = "pioB_clk",
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        .pmc_mask       = 1 << AT91SAM9263_ID_PIOB,
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        .type           = CLK_TYPE_PERIPHERAL,
59 
};
60 
static struct clk pioCDE_clk = {
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        .name           = "pioCDE_clk",
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        .pmc_mask       = 1 << AT91SAM9263_ID_PIOCDE,
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        .type           = CLK_TYPE_PERIPHERAL,
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};
65 
static struct clk usart0_clk = {
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        .name           = "usart0_clk",
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        .pmc_mask       = 1 << AT91SAM9263_ID_US0,
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        .type           = CLK_TYPE_PERIPHERAL,
69 
};
70 
static struct clk usart1_clk = {
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        .name           = "usart1_clk",
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        .pmc_mask       = 1 << AT91SAM9263_ID_US1,
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        .type           = CLK_TYPE_PERIPHERAL,
74 
};
75 
static struct clk usart2_clk = {
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        .name           = "usart2_clk",
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        .pmc_mask       = 1 << AT91SAM9263_ID_US2,
78 
        .type           = CLK_TYPE_PERIPHERAL,
79 
};
80 
static struct clk mmc0_clk = {
81 
        .name           = "mci0_clk",
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        .pmc_mask       = 1 << AT91SAM9263_ID_MCI0,
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        .type           = CLK_TYPE_PERIPHERAL,
84 
};
85 
static struct clk mmc1_clk = {
86 
        .name           = "mci1_clk",
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        .pmc_mask       = 1 << AT91SAM9263_ID_MCI1,
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        .type           = CLK_TYPE_PERIPHERAL,
89 
};
90 
static struct clk can_clk = {
91 
        .name           = "can_clk",
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        .pmc_mask       = 1 << AT91SAM9263_ID_CAN,
93 
        .type           = CLK_TYPE_PERIPHERAL,
94 
};
95 
static struct clk twi_clk = {
96 
        .name           = "twi_clk",
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        .pmc_mask       = 1 << AT91SAM9263_ID_TWI,
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        .type           = CLK_TYPE_PERIPHERAL,
99 
};
100 
static struct clk spi0_clk = {
101 
        .name           = "spi0_clk",
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        .pmc_mask       = 1 << AT91SAM9263_ID_SPI0,
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        .type           = CLK_TYPE_PERIPHERAL,
104 
};
105 
static struct clk spi1_clk = {
106 
        .name           = "spi1_clk",
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        .pmc_mask       = 1 << AT91SAM9263_ID_SPI1,
108 
        .type           = CLK_TYPE_PERIPHERAL,
109 
};
110 
static struct clk ssc0_clk = {
111 
        .name           = "ssc0_clk",
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        .pmc_mask       = 1 << AT91SAM9263_ID_SSC0,
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        .type           = CLK_TYPE_PERIPHERAL,
114 
};
115 
static struct clk ssc1_clk = {
116 
        .name           = "ssc1_clk",
117 
        .pmc_mask       = 1 << AT91SAM9263_ID_SSC1,
118 
        .type           = CLK_TYPE_PERIPHERAL,
119 
};
120 
static struct clk ac97_clk = {
121 
        .name           = "ac97_clk",
122 
        .pmc_mask       = 1 << AT91SAM9263_ID_AC97C,
123 
        .type           = CLK_TYPE_PERIPHERAL,
124 
};
125 
static struct clk tcb_clk = {
126 
        .name           = "tcb_clk",
127 
        .pmc_mask       = 1 << AT91SAM9263_ID_TCB,
128 
        .type           = CLK_TYPE_PERIPHERAL,
129 
};
130 
static struct clk pwmc_clk = {
131 
        .name           = "pwmc_clk",
132 
        .pmc_mask       = 1 << AT91SAM9263_ID_PWMC,
133 
        .type           = CLK_TYPE_PERIPHERAL,
134 
};
135 
static struct clk macb_clk = {
136 
        .name           = "macb_clk",
137 
        .pmc_mask       = 1 << AT91SAM9263_ID_EMAC,
138 
        .type           = CLK_TYPE_PERIPHERAL,
139 
};
140 
static struct clk dma_clk = {
141 
        .name           = "dma_clk",
142 
        .pmc_mask       = 1 << AT91SAM9263_ID_DMA,
143 
        .type           = CLK_TYPE_PERIPHERAL,
144 
};
145 
static struct clk twodge_clk = {
146 
        .name           = "2dge_clk",
147 
        .pmc_mask       = 1 << AT91SAM9263_ID_2DGE,
148 
        .type           = CLK_TYPE_PERIPHERAL,
149 
};
150 
static struct clk udc_clk = {
151 
        .name           = "udc_clk",
152 
        .pmc_mask       = 1 << AT91SAM9263_ID_UDP,
153 
        .type           = CLK_TYPE_PERIPHERAL,
154 
};
155 
static struct clk isi_clk = {
156 
        .name           = "isi_clk",
157 
        .pmc_mask       = 1 << AT91SAM9263_ID_ISI,
158 
        .type           = CLK_TYPE_PERIPHERAL,
159 
};
160 
static struct clk lcdc_clk = {
161 
        .name           = "lcdc_clk",
162 
        .pmc_mask       = 1 << AT91SAM9263_ID_LCDC,
163 
        .type           = CLK_TYPE_PERIPHERAL,
164 
};
165 
static struct clk ohci_clk = {
166 
        .name           = "ohci_clk",
167 
        .pmc_mask       = 1 << AT91SAM9263_ID_UHP,
168 
        .type           = CLK_TYPE_PERIPHERAL,
169 
};
170 
 
171 
static struct clk *periph_clocks[] __initdata = {
172 
        &pioA_clk,
173 
        &pioB_clk,
174 
        &pioCDE_clk,
175 
        &usart0_clk,
176 
        &usart1_clk,
177 
        &usart2_clk,
178 
        &mmc0_clk,
179 
        &mmc1_clk,
180 
        &can_clk,
181 
        &twi_clk,
182 
        &spi0_clk,
183 
        &spi1_clk,
184 
        &ssc0_clk,
185 
        &ssc1_clk,
186 
        &ac97_clk,
187 
        &tcb_clk,
188 
        &pwmc_clk,
189 
        &macb_clk,
190 
        &twodge_clk,
191 
        &udc_clk,
192 
        &isi_clk,
193 
        &lcdc_clk,
194 
        &dma_clk,
195 
        &ohci_clk,
196 
        // irq0 .. irq1
197 
};
198 
 
199 
/*
200 
 * The four programmable clocks.
201 
 * You must configure pin multiplexing to bring these signals out.
202 
 */
203 
static struct clk pck0 = {
204 
        .name           = "pck0",
205 
        .pmc_mask       = AT91_PMC_PCK0,
206 
        .type           = CLK_TYPE_PROGRAMMABLE,
207 
        .id             = 0,
208 
};
209 
static struct clk pck1 = {
210 
        .name           = "pck1",
211 
        .pmc_mask       = AT91_PMC_PCK1,
212 
        .type           = CLK_TYPE_PROGRAMMABLE,
213 
        .id             = 1,
214 
};
215 
static struct clk pck2 = {
216 
        .name           = "pck2",
217 
        .pmc_mask       = AT91_PMC_PCK2,
218 
        .type           = CLK_TYPE_PROGRAMMABLE,
219 
        .id             = 2,
220 
};
221 
static struct clk pck3 = {
222 
        .name           = "pck3",
223 
        .pmc_mask       = AT91_PMC_PCK3,
224 
        .type           = CLK_TYPE_PROGRAMMABLE,
225 
        .id             = 3,
226 
};
227 
 
228 
static void __init at91sam9263_register_clocks(void)
229 
{
230 
        int i;
231 
 
232 
        for (i = 0; i < ARRAY_SIZE(periph_clocks); i++)
233 
                clk_register(periph_clocks[i]);
234 
 
235 
        clk_register(&pck0);
236 
        clk_register(&pck1);
237 
        clk_register(&pck2);
238 
        clk_register(&pck3);
239 
}
240 
 
241 
/* --------------------------------------------------------------------
242 
 *  GPIO
243 
 * -------------------------------------------------------------------- */
244 
 
245 
static struct at91_gpio_bank at91sam9263_gpio[] = {
246 
        {
247 
                .id             = AT91SAM9263_ID_PIOA,
248 
                .offset         = AT91_PIOA,
249 
                .clock          = &pioA_clk,
250 
        }, {
251 
                .id             = AT91SAM9263_ID_PIOB,
252 
                .offset         = AT91_PIOB,
253 
                .clock          = &pioB_clk,
254 
        }, {
255 
                .id             = AT91SAM9263_ID_PIOCDE,
256 
                .offset         = AT91_PIOC,
257 
                .clock          = &pioCDE_clk,
258 
        }, {
259 
                .id             = AT91SAM9263_ID_PIOCDE,
260 
                .offset         = AT91_PIOD,
261 
                .clock          = &pioCDE_clk,
262 
        }, {
263 
                .id             = AT91SAM9263_ID_PIOCDE,
264 
                .offset         = AT91_PIOE,
265 
                .clock          = &pioCDE_clk,
266 
        }
267 
};
268 
 
269 
static void at91sam9263_reset(void)
270 
{
271 
        at91_sys_write(AT91_RSTC_CR, AT91_RSTC_KEY | AT91_RSTC_PROCRST | AT91_RSTC_PERRST);
272 
}
273 
 
274 
 
275 
/* --------------------------------------------------------------------
276 
 *  AT91SAM9263 processor initialization
277 
 * -------------------------------------------------------------------- */
278 
 
279 
void __init at91sam9263_initialize(unsigned long main_clock)
280 
{
281 
        /* Map peripherals */
282 
        iotable_init(at91sam9263_io_desc, ARRAY_SIZE(at91sam9263_io_desc));
283 
 
284 
        at91_arch_reset = at91sam9263_reset;
285 
        at91_extern_irq = (1 << AT91SAM9263_ID_IRQ0) | (1 << AT91SAM9263_ID_IRQ1);
286 
 
287 
        /* Init clock subsystem */
288 
        at91_clock_init(main_clock);
289 
 
290 
        /* Register the processor-specific clocks */
291 
        at91sam9263_register_clocks();
292 
 
293 
        /* Register GPIO subsystem */
294 
        at91_gpio_init(at91sam9263_gpio, 5);
295 
}
296 
 
297 
/* --------------------------------------------------------------------
298 
 *  Interrupt initialization
299 
 * -------------------------------------------------------------------- */
300 
 
301 
/*
302 
 * The default interrupt priority levels (0 = lowest, 7 = highest).
303 
 */
304 
static unsigned int at91sam9263_default_irq_priority[NR_AIC_IRQS] __initdata = {
305 
        7,      /* Advanced Interrupt Controller (FIQ) */
306 
        7,      /* System Peripherals */
307 
        0,       /* Parallel IO Controller A */
308 
        0,       /* Parallel IO Controller B */
309 
        0,       /* Parallel IO Controller C, D and E */
310 
        0,
311 
        0,
312 
        6,      /* USART 0 */
313 
        6,      /* USART 1 */
314 
        6,      /* USART 2 */
315 
        0,       /* Multimedia Card Interface 0 */
316 
        0,       /* Multimedia Card Interface 1 */
317 
        4,      /* CAN */
318 
        0,       /* Two-Wire Interface */
319 
        6,      /* Serial Peripheral Interface 0 */
320 
        6,      /* Serial Peripheral Interface 1 */
321 
        5,      /* Serial Synchronous Controller 0 */
322 
        5,      /* Serial Synchronous Controller 1 */
323 
        6,      /* AC97 Controller */
324 
        0,       /* Timer Counter 0, 1 and 2 */
325 
        0,       /* Pulse Width Modulation Controller */
326 
        3,      /* Ethernet */
327 
        0,
328 
        0,       /* 2D Graphic Engine */
329 
        3,      /* USB Device Port */
330 
        0,       /* Image Sensor Interface */
331 
        3,      /* LDC Controller */
332 
        0,       /* DMA Controller */
333 
        0,
334 
        3,      /* USB Host port */
335 
        0,       /* Advanced Interrupt Controller (IRQ0) */
336 
        0,       /* Advanced Interrupt Controller (IRQ1) */
337 
};
338 
 
339 
void __init at91sam9263_init_interrupts(unsigned int priority[NR_AIC_IRQS])
340 
{
341 
        if (!priority)
342 
                priority = at91sam9263_default_irq_priority;
343 
 
344 
        /* Initialize the AIC interrupt controller */
345 
        at91_aic_init(priority);
346 
 
347 
        /* Enable GPIO interrupts */
348 
        at91_gpio_irq_setup();
349 
}

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