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[/] [or1k_soc_on_altera_embedded_dev_kit/] [trunk/] [linux-2.6/] [linux-2.6.24/] [arch/] [arm/] [mach-h720x/] [cpu-h7202.c] - Blame information for rev 3

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1 3 xianfeng 
/*
2 
 * linux/arch/arm/mach-h720x/cpu-h7202.c
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 *
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 * Copyright (C) 2003 Thomas Gleixner <tglx@linutronix.de>
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 *               2003 Robert Schwebel <r.schwebel@pengutronix.de>
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 *               2004 Sascha Hauer    <s.hauer@pengutronix.de>
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 *
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 * processor specific stuff for the Hynix h7202
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 *
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 * This program is free software; you can redistribute it and/or modify
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 * it under the terms of the GNU General Public License version 2 as
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 * published by the Free Software Foundation.
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 *
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 */
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#include <linux/init.h>
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#include <linux/interrupt.h>
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#include <linux/module.h>
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#include <asm/types.h>
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#include <asm/hardware.h>
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#include <asm/irq.h>
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#include <asm/arch/irqs.h>
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#include <asm/mach/irq.h>
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#include <asm/mach/time.h>
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#include <linux/device.h>
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#include <linux/serial_8250.h>
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#include "common.h"
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static struct resource h7202ps2_resources[] = {
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        [0] = {
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                .start  = 0x8002c000,
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                .end    = 0x8002c040,
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                .flags  = IORESOURCE_MEM,
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        },
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        [1] = {
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                .start  = IRQ_PS2,
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                .end    = IRQ_PS2,
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                .flags  = IORESOURCE_IRQ,
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        },
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};
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static struct platform_device h7202ps2_device = {
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        .name           = "h7202ps2",
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        .id             = -1,
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        .num_resources  = ARRAY_SIZE(h7202ps2_resources),
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        .resource       = h7202ps2_resources,
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};
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static struct plat_serial8250_port serial_platform_data[] = {
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        {
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                .membase        = (void*)SERIAL0_VIRT,
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                .mapbase        = SERIAL0_BASE,
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                .irq            = IRQ_UART0,
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                .uartclk        = 2*1843200,
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                .regshift       = 2,
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                .iotype         = UPIO_MEM,
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                .flags          = UPF_BOOT_AUTOCONF | UPF_SKIP_TEST,
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        },
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        {
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                .membase        = (void*)SERIAL1_VIRT,
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                .mapbase        = SERIAL1_BASE,
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                .irq            = IRQ_UART1,
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                .uartclk        = 2*1843200,
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                .regshift       = 2,
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                .iotype         = UPIO_MEM,
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                .flags          = UPF_BOOT_AUTOCONF | UPF_SKIP_TEST,
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        },
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#ifdef CONFIG_H7202_SERIAL23
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        {
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                .membase        = (void*)SERIAL2_VIRT,
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                .mapbase        = SERIAL2_BASE,
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                .irq            = IRQ_UART2,
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                .uartclk        = 2*1843200,
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                .regshift       = 2,
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                .iotype         = UPIO_MEM,
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                .flags          = UPF_BOOT_AUTOCONF | UPF_SKIP_TEST,
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        },
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        {
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                .membase        = (void*)SERIAL3_VIRT,
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                .mapbase        = SERIAL3_BASE,
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                .irq            = IRQ_UART3,
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                .uartclk        = 2*1843200,
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                .regshift       = 2,
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                .iotype         = UPIO_MEM,
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                .flags          = UPF_BOOT_AUTOCONF | UPF_SKIP_TEST,
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        },
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#endif
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        { },
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};
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static struct platform_device serial_device = {
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        .name                   = "serial8250",
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        .id                     = PLAT8250_DEV_PLATFORM,
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        .dev                    = {
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                .platform_data  = serial_platform_data,
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        },
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};
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static struct platform_device *devices[] __initdata = {
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        &h7202ps2_device,
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        &serial_device,
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};
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/* Although we have two interrupt lines for the timers, we only have one
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 * status register which clears all pending timer interrupts on reading. So
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 * we have to handle all timer interrupts in one place.
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 */
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static void
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h7202_timerx_demux_handler(unsigned int irq_unused, struct irq_desc *desc)
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{
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        unsigned int mask, irq;
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        mask = CPU_REG (TIMER_VIRT, TIMER_TOPSTAT);
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        if ( mask & TSTAT_T0INT ) {
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                write_seqlock(&xtime_lock);
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                timer_tick();
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                write_sequnlock(&xtime_lock);
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                if( mask == TSTAT_T0INT )
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                        return;
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        }
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        mask >>= 1;
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        irq = IRQ_TIMER1;
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        desc = irq_desc + irq;
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        while (mask) {
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                if (mask & 1)
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                        desc_handle_irq(irq, desc);
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                irq++;
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                desc++;
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                mask >>= 1;
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        }
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}
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/*
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 * Timer interrupt handler
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 */
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static irqreturn_t
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h7202_timer_interrupt(int irq, void *dev_id)
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{
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        h7202_timerx_demux_handler(0, NULL);
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        return IRQ_HANDLED;
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}
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/*
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 * mask multiplexed timer IRQs
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 */
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static void inline mask_timerx_irq (u32 irq)
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{
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        unsigned int bit;
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        bit = 2 << ((irq == IRQ_TIMER64B) ? 4 : (irq - IRQ_TIMER1));
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        CPU_REG (TIMER_VIRT, TIMER_TOPCTRL) &= ~bit;
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}
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/*
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 * unmask multiplexed timer IRQs
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 */
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static void inline unmask_timerx_irq (u32 irq)
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{
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        unsigned int bit;
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        bit = 2 << ((irq == IRQ_TIMER64B) ? 4 : (irq - IRQ_TIMER1));
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        CPU_REG (TIMER_VIRT, TIMER_TOPCTRL) |= bit;
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}
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static struct irq_chip h7202_timerx_chip = {
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        .ack = mask_timerx_irq,
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        .mask = mask_timerx_irq,
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        .unmask = unmask_timerx_irq,
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};
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static struct irqaction h7202_timer_irq = {
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        .name           = "h7202 Timer Tick",
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        .flags          = IRQF_DISABLED | IRQF_TIMER | IRQF_IRQPOLL,
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        .handler        = h7202_timer_interrupt,
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};
176 
 
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/*
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 * Setup TIMER0 as system timer
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 */
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void __init h7202_init_time(void)
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{
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        CPU_REG (TIMER_VIRT, TM0_PERIOD) = LATCH;
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        CPU_REG (TIMER_VIRT, TM0_CTRL) = TM_RESET;
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        CPU_REG (TIMER_VIRT, TM0_CTRL) = TM_REPEAT | TM_START;
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        CPU_REG (TIMER_VIRT, TIMER_TOPCTRL) = ENABLE_TM0_INTR | TIMER_ENABLE_BIT;
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        setup_irq(IRQ_TIMER0, &h7202_timer_irq);
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}
189 
 
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struct sys_timer h7202_timer = {
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        .init           = h7202_init_time,
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        .offset         = h720x_gettimeoffset,
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};
194 
 
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void __init h7202_init_irq (void)
196 
{
197 
        int     irq;
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        CPU_REG (GPIO_E_VIRT, GPIO_MASK) = 0x0;
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        for (irq = IRQ_TIMER1;
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                          irq < IRQ_CHAINED_TIMERX(NR_TIMERX_IRQS); irq++) {
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                mask_timerx_irq(irq);
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                set_irq_chip(irq, &h7202_timerx_chip);
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                set_irq_handler(irq, handle_edge_irq);
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                set_irq_flags(irq, IRQF_VALID );
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        }
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        set_irq_chained_handler(IRQ_TIMERX, h7202_timerx_demux_handler);
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210 
        h720x_init_irq();
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}
212 
 
213 
void __init init_hw_h7202(void)
214 
{
215 
        /* Enable clocks */
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        CPU_REG (PMU_BASE, PMU_PLL_CTRL) |= PLL_2_EN | PLL_1_EN | PLL_3_MUTE;
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218 
        CPU_REG (SERIAL0_VIRT, SERIAL_ENABLE) = SERIAL_ENABLE_EN;
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        CPU_REG (SERIAL1_VIRT, SERIAL_ENABLE) = SERIAL_ENABLE_EN;
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#ifdef CONFIG_H7202_SERIAL23
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        CPU_REG (SERIAL2_VIRT, SERIAL_ENABLE) = SERIAL_ENABLE_EN;
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        CPU_REG (SERIAL3_VIRT, SERIAL_ENABLE) = SERIAL_ENABLE_EN;
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        CPU_IO (GPIO_AMULSEL) = AMULSEL_USIN2 | AMULSEL_USOUT2 |
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                                AMULSEL_USIN3 | AMULSEL_USOUT3;
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#endif
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        (void) platform_add_devices(devices, ARRAY_SIZE(devices));
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}

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