OpenCores
URL https://opencores.org/ocsvn/or1k_soc_on_altera_embedded_dev_kit/or1k_soc_on_altera_embedded_dev_kit/trunk

Subversion Repositories or1k_soc_on_altera_embedded_dev_kit

[/] [or1k_soc_on_altera_embedded_dev_kit/] [trunk/] [linux-2.6/] [linux-2.6.24/] [arch/] [mips/] [bcm47xx/] [irq.c] - Blame information for rev 17

Go to most recent revision | Details | Compare with Previous | View Log

Line No. Rev Author Line
1 3 xianfeng
/*
2
 *  Copyright (C) 2004 Florian Schirmer <jolt@tuxbox.org>
3
 *
4
 *  This program is free software; you can redistribute  it and/or modify it
5
 *  under  the terms of  the GNU General  Public License as published by the
6
 *  Free Software Foundation;  either version 2 of the  License, or (at your
7
 *  option) any later version.
8
 *
9
 *  THIS  SOFTWARE  IS PROVIDED   ``AS  IS'' AND   ANY  EXPRESS OR IMPLIED
10
 *  WARRANTIES,   INCLUDING, BUT NOT  LIMITED  TO, THE IMPLIED WARRANTIES OF
11
 *  MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.  IN
12
 *  NO  EVENT  SHALL   THE AUTHOR  BE    LIABLE FOR ANY   DIRECT, INDIRECT,
13
 *  INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
14
 *  NOT LIMITED   TO, PROCUREMENT OF  SUBSTITUTE GOODS  OR SERVICES; LOSS OF
15
 *  USE, DATA,  OR PROFITS; OR  BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
16
 *  ANY THEORY OF LIABILITY, WHETHER IN  CONTRACT, STRICT LIABILITY, OR TORT
17
 *  (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
18
 *  THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
19
 *
20
 *  You should have received a copy of the  GNU General Public License along
21
 *  with this program; if not, write  to the Free Software Foundation, Inc.,
22
 *  675 Mass Ave, Cambridge, MA 02139, USA.
23
 */
24
 
25
#include <linux/types.h>
26
#include <linux/interrupt.h>
27
#include <linux/irq.h>
28
#include <asm/irq_cpu.h>
29
 
30
void plat_irq_dispatch(void)
31
{
32
        u32 cause;
33
 
34
        cause = read_c0_cause() & read_c0_status() & CAUSEF_IP;
35
 
36
        clear_c0_status(cause);
37
 
38
        if (cause & CAUSEF_IP7)
39
                do_IRQ(7);
40
        if (cause & CAUSEF_IP2)
41
                do_IRQ(2);
42
        if (cause & CAUSEF_IP3)
43
                do_IRQ(3);
44
        if (cause & CAUSEF_IP4)
45
                do_IRQ(4);
46
        if (cause & CAUSEF_IP5)
47
                do_IRQ(5);
48
        if (cause & CAUSEF_IP6)
49
                do_IRQ(6);
50
}
51
 
52
void __init arch_init_irq(void)
53
{
54
        mips_cpu_irq_init();
55
}

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.