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[/] [or1k_soc_on_altera_embedded_dev_kit/] [trunk/] [linux-2.6/] [linux-2.6.24/] [arch/] [mips/] [kernel/] [irq-msc01.c] - Blame information for rev 3

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Line No. Rev Author Line
1 3 xianfeng 
/*
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 * This program is free software; you can redistribute  it and/or modify it
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 * under  the terms of  the GNU General  Public License as published by the
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 * Free Software Foundation;  either version 2 of the  License, or (at your
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 * option) any later version.
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 *
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 * Copyright (c) 2004 MIPS Inc
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 * Author: chris@mips.com
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 *
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 * Copyright (C) 2004, 06 Ralf Baechle <ralf@linux-mips.org>
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 */
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#include <linux/module.h>
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#include <linux/interrupt.h>
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#include <linux/kernel.h>
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#include <linux/sched.h>
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#include <linux/kernel_stat.h>
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#include <asm/io.h>
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#include <asm/irq.h>
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#include <asm/msc01_ic.h>
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static unsigned long _icctrl_msc;
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#define MSC01_IC_REG_BASE       _icctrl_msc
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#define MSCIC_WRITE(reg, data)  do { *(volatile u32 *)(reg) = data; } while (0)
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#define MSCIC_READ(reg, data)   do { data = *(volatile u32 *)(reg); } while (0)
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static unsigned int irq_base;
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/* mask off an interrupt */
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static inline void mask_msc_irq(unsigned int irq)
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{
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        if (irq < (irq_base + 32))
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                MSCIC_WRITE(MSC01_IC_DISL, 1<<(irq - irq_base));
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        else
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                MSCIC_WRITE(MSC01_IC_DISH, 1<<(irq - irq_base - 32));
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}
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/* unmask an interrupt */
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static inline void unmask_msc_irq(unsigned int irq)
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{
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        if (irq < (irq_base + 32))
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                MSCIC_WRITE(MSC01_IC_ENAL, 1<<(irq - irq_base));
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        else
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                MSCIC_WRITE(MSC01_IC_ENAH, 1<<(irq - irq_base - 32));
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}
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/*
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 * Masks and ACKs an IRQ
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 */
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static void level_mask_and_ack_msc_irq(unsigned int irq)
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{
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        mask_msc_irq(irq);
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        if (!cpu_has_veic)
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                MSCIC_WRITE(MSC01_IC_EOI, 0);
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        /* This actually needs to be a call into platform code */
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        smtc_im_ack_irq(irq);
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}
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/*
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 * Masks and ACKs an IRQ
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 */
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static void edge_mask_and_ack_msc_irq(unsigned int irq)
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{
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        mask_msc_irq(irq);
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        if (!cpu_has_veic)
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                MSCIC_WRITE(MSC01_IC_EOI, 0);
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        else {
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                u32 r;
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                MSCIC_READ(MSC01_IC_SUP+irq*8, r);
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                MSCIC_WRITE(MSC01_IC_SUP+irq*8, r | ~MSC01_IC_SUP_EDGE_BIT);
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                MSCIC_WRITE(MSC01_IC_SUP+irq*8, r);
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        }
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        smtc_im_ack_irq(irq);
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}
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/*
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 * End IRQ processing
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 */
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static void end_msc_irq(unsigned int irq)
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{
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        if (!(irq_desc[irq].status & (IRQ_DISABLED|IRQ_INPROGRESS)))
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                unmask_msc_irq(irq);
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}
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/*
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 * Interrupt handler for interrupts coming from SOC-it.
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 */
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void ll_msc_irq(void)
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{
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        unsigned int irq;
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        /* read the interrupt vector register */
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        MSCIC_READ(MSC01_IC_VEC, irq);
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        if (irq < 64)
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                do_IRQ(irq + irq_base);
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        else {
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                /* Ignore spurious interrupt */
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        }
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}
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void
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msc_bind_eic_interrupt(unsigned int irq, unsigned int set)
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{
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        MSCIC_WRITE(MSC01_IC_RAMW,
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                    (irq<<MSC01_IC_RAMW_ADDR_SHF) | (set<<MSC01_IC_RAMW_DATA_SHF));
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}
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struct irq_chip msc_levelirq_type = {
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        .name = "SOC-it-Level",
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        .ack = level_mask_and_ack_msc_irq,
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        .mask = mask_msc_irq,
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        .mask_ack = level_mask_and_ack_msc_irq,
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        .unmask = unmask_msc_irq,
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        .eoi = unmask_msc_irq,
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        .end = end_msc_irq,
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};
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struct irq_chip msc_edgeirq_type = {
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        .name = "SOC-it-Edge",
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        .ack = edge_mask_and_ack_msc_irq,
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        .mask = mask_msc_irq,
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        .mask_ack = edge_mask_and_ack_msc_irq,
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        .unmask = unmask_msc_irq,
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        .eoi = unmask_msc_irq,
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        .end = end_msc_irq,
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};
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void __init init_msc_irqs(unsigned long icubase, unsigned int irqbase, msc_irqmap_t *imp, int nirq)
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{
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        extern void (*board_bind_eic_interrupt)(unsigned int irq, unsigned int regset);
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        _icctrl_msc = (unsigned long) ioremap(icubase, 0x40000);
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        /* Reset interrupt controller - initialises all registers to 0 */
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        MSCIC_WRITE(MSC01_IC_RST, MSC01_IC_RST_RST_BIT);
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        board_bind_eic_interrupt = &msc_bind_eic_interrupt;
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        for (; nirq >= 0; nirq--, imp++) {
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                int n = imp->im_irq;
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                switch (imp->im_type) {
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                case MSC01_IRQ_EDGE:
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                        set_irq_chip(irqbase+n, &msc_edgeirq_type);
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                        if (cpu_has_veic)
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                                MSCIC_WRITE(MSC01_IC_SUP+n*8, MSC01_IC_SUP_EDGE_BIT);
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                        else
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                                MSCIC_WRITE(MSC01_IC_SUP+n*8, MSC01_IC_SUP_EDGE_BIT | imp->im_lvl);
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                        break;
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                case MSC01_IRQ_LEVEL:
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                        set_irq_chip(irqbase+n, &msc_levelirq_type);
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                        if (cpu_has_veic)
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                                MSCIC_WRITE(MSC01_IC_SUP+n*8, 0);
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                        else
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                                MSCIC_WRITE(MSC01_IC_SUP+n*8, imp->im_lvl);
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                }
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        }
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        irq_base = irqbase;
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        MSCIC_WRITE(MSC01_IC_GENA, MSC01_IC_GENA_GENA_BIT);     /* Enable interrupt generation */
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}

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