OpenCores
URL https://opencores.org/ocsvn/or1k_soc_on_altera_embedded_dev_kit/or1k_soc_on_altera_embedded_dev_kit/trunk

Subversion Repositories or1k_soc_on_altera_embedded_dev_kit

[/] [or1k_soc_on_altera_embedded_dev_kit/] [trunk/] [linux-2.6/] [linux-2.6.24/] [arch/] [mips/] [pmc-sierra/] [msp71xx/] [msp_serial.c] - Blame information for rev 3

Details | Compare with Previous | View Log

Line No. Rev Author Line
1 3 xianfeng
/*
2
 * The setup file for serial related hardware on PMC-Sierra MSP processors.
3
 *
4
 * Copyright 2005 PMC-Sierra, Inc.
5
 *
6
 *  This program is free software; you can redistribute  it and/or modify it
7
 *  under  the terms of  the GNU General  Public License as published by the
8
 *  Free Software Foundation;  either version 2 of the  License, or (at your
9
 *  option) any later version.
10
 *
11
 *  THIS  SOFTWARE  IS PROVIDED   ``AS  IS'' AND   ANY  EXPRESS OR IMPLIED
12
 *  WARRANTIES,   INCLUDING, BUT NOT  LIMITED  TO, THE IMPLIED WARRANTIES OF
13
 *  MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.  IN
14
 *  NO  EVENT  SHALL   THE AUTHOR  BE    LIABLE FOR ANY   DIRECT, INDIRECT,
15
 *  INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
16
 *  NOT LIMITED   TO, PROCUREMENT OF  SUBSTITUTE GOODS  OR SERVICES; LOSS OF
17
 *  USE, DATA,  OR PROFITS; OR  BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
18
 *  ANY THEORY OF LIABILITY, WHETHER IN  CONTRACT, STRICT LIABILITY, OR TORT
19
 *  (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
20
 *  THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
21
 *
22
 *  You should have received a copy of the  GNU General Public License along
23
 *  with this program; if not, write  to the Free Software Foundation, Inc.,
24
 *  675 Mass Ave, Cambridge, MA 02139, USA.
25
 */
26
 
27
#include <linux/serial.h>
28
#include <linux/serial_core.h>
29
#include <linux/serial_reg.h>
30
 
31
#include <asm/bootinfo.h>
32
#include <asm/io.h>
33
#include <asm/processor.h>
34
#include <asm/serial.h>
35
#include <linux/serial_8250.h>
36
 
37
#include <msp_prom.h>
38
#include <msp_int.h>
39
#include <msp_regs.h>
40
 
41
#ifdef CONFIG_KGDB
42
/*
43
 * kgdb uses serial port 1 so the console can remain on port 0.
44
 * To use port 0 change the definition to read as follows:
45
 * #define DEBUG_PORT_BASE KSEG1ADDR(MSP_UART0_BASE)
46
 */
47
#define DEBUG_PORT_BASE KSEG1ADDR(MSP_UART1_BASE)
48
 
49
int putDebugChar(char c)
50
{
51
        volatile uint32_t *uart = (volatile uint32_t *)DEBUG_PORT_BASE;
52
        uint32_t val = (uint32_t)c;
53
 
54
        local_irq_disable();
55
        while( !(uart[5] & 0x20) ); /* Wait for TXRDY */
56
        uart[0] = val;
57
        while( !(uart[5] & 0x20) ); /* Wait for TXRDY */
58
        local_irq_enable();
59
 
60
        return 1;
61
}
62
 
63
char getDebugChar(void)
64
{
65
        volatile uint32_t *uart = (volatile uint32_t *)DEBUG_PORT_BASE;
66
        uint32_t val;
67
 
68
        while( !(uart[5] & 0x01) ); /* Wait for RXRDY */
69
        val = uart[0];
70
 
71
        return (char)val;
72
}
73
 
74
void initDebugPort(unsigned int uartclk, unsigned int baudrate)
75
{
76
        unsigned int baud_divisor = (uartclk + 8 * baudrate)/(16 * baudrate);
77
 
78
        /* Enable FIFOs */
79
        writeb(UART_FCR_ENABLE_FIFO | UART_FCR_CLEAR_RCVR |
80
                        UART_FCR_CLEAR_XMIT | UART_FCR_TRIGGER_4,
81
                (char *)DEBUG_PORT_BASE + (UART_FCR * 4));
82
 
83
        /* Select brtc divisor */
84
        writeb(UART_LCR_DLAB, (char *)DEBUG_PORT_BASE + (UART_LCR * 4));
85
 
86
        /* Store divisor lsb */
87
        writeb(baud_divisor, (char *)DEBUG_PORT_BASE + (UART_TX * 4));
88
 
89
        /* Store divisor msb */
90
        writeb(baud_divisor >> 8, (char *)DEBUG_PORT_BASE + (UART_IER * 4));
91
 
92
        /* Set 8N1 mode */
93
        writeb(UART_LCR_WLEN8, (char *)DEBUG_PORT_BASE + (UART_LCR * 4));
94
 
95
        /* Disable flow control */
96
        writeb(0, (char *)DEBUG_PORT_BASE + (UART_MCR * 4));
97
 
98
        /* Disable receive interrupt(!) */
99
        writeb(0, (char *)DEBUG_PORT_BASE + (UART_IER * 4));
100
}
101
#endif
102
 
103
void __init msp_serial_setup(void)
104
{
105
        char    *s;
106
        char    *endp;
107
        struct uart_port up;
108
        unsigned int uartclk;
109
 
110
        memset(&up, 0, sizeof(up));
111
 
112
        /* Check if clock was specified in environment */
113
        s = prom_getenv("uartfreqhz");
114
        if(!(s && *s && (uartclk = simple_strtoul(s, &endp, 10)) && *endp == 0))
115
                uartclk = MSP_BASE_BAUD;
116
        ppfinit("UART clock set to %d\n", uartclk);
117
 
118
        /* Initialize first serial port */
119
        up.mapbase      = MSP_UART0_BASE;
120
        up.membase      = ioremap_nocache(up.mapbase, MSP_UART_REG_LEN);
121
        up.irq          = MSP_INT_UART0;
122
        up.uartclk      = uartclk;
123
        up.regshift     = 2;
124
        up.iotype       = UPIO_DWAPB; /* UPIO_MEM like */
125
        up.flags        = ASYNC_BOOT_AUTOCONF | ASYNC_SKIP_TEST;
126
        up.type         = PORT_16550A;
127
        up.line         = 0;
128
        up.private_data         = (void*)UART0_STATUS_REG;
129
        if (early_serial_setup(&up))
130
                printk(KERN_ERR "Early serial init of port 0 failed\n");
131
 
132
        /* Initialize the second serial port, if one exists */
133
        switch (mips_machtype) {
134
                case MACH_MSP4200_EVAL:
135
                case MACH_MSP4200_GW:
136
                case MACH_MSP4200_FPGA:
137
                case MACH_MSP7120_EVAL:
138
                case MACH_MSP7120_GW:
139
                case MACH_MSP7120_FPGA:
140
                        /* Enable UART1 on MSP4200 and MSP7120 */
141
                        *GPIO_CFG2_REG = 0x00002299;
142
 
143
#ifdef CONFIG_KGDB
144
                        /* Initialize UART1 for kgdb since PMON doesn't */
145
                        if( DEBUG_PORT_BASE == KSEG1ADDR(MSP_UART1_BASE) ) {
146
                                if( mips_machtype == MACH_MSP4200_FPGA
147
                                 || mips_machtype == MACH_MSP7120_FPGA )
148
                                        initDebugPort(uartclk, 19200);
149
                                else
150
                                        initDebugPort(uartclk, 57600);
151
                        }
152
#endif
153
                        break;
154
 
155
                default:
156
                        return; /* No second serial port, good-bye. */
157
        }
158
 
159
        up.mapbase      = MSP_UART1_BASE;
160
        up.membase      = ioremap_nocache(up.mapbase, MSP_UART_REG_LEN);
161
        up.irq          = MSP_INT_UART1;
162
        up.line         = 1;
163
        up.private_data         = (void*)UART1_STATUS_REG;
164
        if (early_serial_setup(&up))
165
                printk(KERN_ERR "Early serial init of port 1 failed\n");
166
}

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.