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3 |
xianfeng |
/*
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* linux/arch/mips/tx4938/toshiba_rbtx4938/setup.c
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*
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* Setup pointers to hardware-dependent routines.
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* Copyright (C) 2000-2001 Toshiba Corporation
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*
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* 2003-2005 (c) MontaVista Software, Inc. This file is licensed under the
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* terms of the GNU General Public License version 2. This program is
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* licensed "as is" without any warranty of any kind, whether express
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* or implied.
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*
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* Support for TX4938 in 2.6 - Manish Lachwani (mlachwani@mvista.com)
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*/
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#include <linux/init.h>
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#include <linux/types.h>
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#include <linux/ioport.h>
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#include <linux/delay.h>
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#include <linux/interrupt.h>
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#include <linux/console.h>
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#include <linux/pci.h>
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#include <linux/pm.h>
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#include <linux/platform_device.h>
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#include <linux/clk.h>
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#include <asm/wbflush.h>
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#include <asm/reboot.h>
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#include <asm/irq.h>
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#include <asm/time.h>
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#include <asm/txx9tmr.h>
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#include <asm/uaccess.h>
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#include <asm/io.h>
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#include <asm/bootinfo.h>
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#include <asm/tx4938/rbtx4938.h>
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#ifdef CONFIG_SERIAL_TXX9
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#include <linux/tty.h>
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#include <linux/serial.h>
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#include <linux/serial_core.h>
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#endif
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#include <linux/spi/spi.h>
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#include <asm/tx4938/spi.h>
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#include <asm/gpio.h>
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extern char * __init prom_getcmdline(void);
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static inline void tx4938_report_pcic_status1(struct tx4938_pcic_reg *pcicptr);
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/* These functions are used for rebooting or halting the machine*/
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extern void rbtx4938_machine_restart(char *command);
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extern void rbtx4938_machine_halt(void);
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extern void rbtx4938_machine_power_off(void);
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/* clocks */
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unsigned int txx9_master_clock;
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unsigned int txx9_cpu_clock;
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unsigned int txx9_gbus_clock;
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unsigned long rbtx4938_ce_base[8];
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unsigned long rbtx4938_ce_size[8];
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int txboard_pci66_mode;
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static int tx4938_pcic_trdyto; /* default: disabled */
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static int tx4938_pcic_retryto; /* default: disabled */
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static int tx4938_ccfg_toeon = 1;
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struct tx4938_pcic_reg *pcicptrs[4] = {
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tx4938_pcicptr /* default setting for TX4938 */
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};
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static struct {
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unsigned long base;
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unsigned long size;
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} phys_regions[16] __initdata;
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static int num_phys_regions __initdata;
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#define PHYS_REGION_MINSIZE 0x10000
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void rbtx4938_machine_halt(void)
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{
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printk(KERN_NOTICE "System Halted\n");
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local_irq_disable();
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while (1)
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__asm__(".set\tmips3\n\t"
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"wait\n\t"
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".set\tmips0");
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}
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void rbtx4938_machine_power_off(void)
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{
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rbtx4938_machine_halt();
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/* no return */
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}
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void rbtx4938_machine_restart(char *command)
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{
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local_irq_disable();
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printk("Rebooting...");
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*rbtx4938_softresetlock_ptr = 1;
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*rbtx4938_sfvol_ptr = 1;
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*rbtx4938_softreset_ptr = 1;
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wbflush();
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while(1);
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}
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void __init
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txboard_add_phys_region(unsigned long base, unsigned long size)
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{
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if (num_phys_regions >= ARRAY_SIZE(phys_regions)) {
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printk("phys_region overflow\n");
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return;
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}
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phys_regions[num_phys_regions].base = base;
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phys_regions[num_phys_regions].size = size;
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num_phys_regions++;
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}
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unsigned long __init
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txboard_find_free_phys_region(unsigned long begin, unsigned long end,
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unsigned long size)
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{
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unsigned long base;
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int i;
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for (base = begin / size * size; base < end; base += size) {
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for (i = 0; i < num_phys_regions; i++) {
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if (phys_regions[i].size &&
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base <= phys_regions[i].base + (phys_regions[i].size - 1) &&
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base + (size - 1) >= phys_regions[i].base)
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break;
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}
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if (i == num_phys_regions)
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return base;
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}
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return 0;
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}
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unsigned long __init
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txboard_find_free_phys_region_shrink(unsigned long begin, unsigned long end,
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unsigned long *size)
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{
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unsigned long sz, base;
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for (sz = *size; sz >= PHYS_REGION_MINSIZE; sz /= 2) {
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base = txboard_find_free_phys_region(begin, end, sz);
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if (base) {
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*size = sz;
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return base;
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}
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}
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return 0;
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}
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unsigned long __init
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txboard_request_phys_region_range(unsigned long begin, unsigned long end,
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unsigned long size)
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{
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unsigned long base;
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base = txboard_find_free_phys_region(begin, end, size);
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if (base)
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txboard_add_phys_region(base, size);
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return base;
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}
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unsigned long __init
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txboard_request_phys_region(unsigned long size)
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{
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unsigned long base;
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unsigned long begin = 0, end = 0x20000000; /* search low 512MB */
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base = txboard_find_free_phys_region(begin, end, size);
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if (base)
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txboard_add_phys_region(base, size);
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return base;
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}
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unsigned long __init
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txboard_request_phys_region_shrink(unsigned long *size)
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{
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unsigned long base;
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unsigned long begin = 0, end = 0x20000000; /* search low 512MB */
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base = txboard_find_free_phys_region_shrink(begin, end, size);
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if (base)
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txboard_add_phys_region(base, *size);
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return base;
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}
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#ifdef CONFIG_PCI
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void __init
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tx4938_pcic_setup(struct tx4938_pcic_reg *pcicptr,
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struct pci_controller *channel,
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unsigned long pci_io_base,
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int extarb)
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{
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int i;
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/* Disable All Initiator Space */
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pcicptr->pciccfg &= ~(TX4938_PCIC_PCICCFG_G2PMEN(0)|
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TX4938_PCIC_PCICCFG_G2PMEN(1)|
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TX4938_PCIC_PCICCFG_G2PMEN(2)|
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TX4938_PCIC_PCICCFG_G2PIOEN);
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/* GB->PCI mappings */
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pcicptr->g2piomask = (channel->io_resource->end - channel->io_resource->start) >> 4;
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pcicptr->g2piogbase = pci_io_base |
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#ifdef __BIG_ENDIAN
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TX4938_PCIC_G2PIOGBASE_ECHG
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#else
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TX4938_PCIC_G2PIOGBASE_BSDIS
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#endif
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;
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pcicptr->g2piopbase = 0;
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for (i = 0; i < 3; i++) {
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pcicptr->g2pmmask[i] = 0;
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pcicptr->g2pmgbase[i] = 0;
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pcicptr->g2pmpbase[i] = 0;
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}
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if (channel->mem_resource->end) {
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pcicptr->g2pmmask[0] = (channel->mem_resource->end - channel->mem_resource->start) >> 4;
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pcicptr->g2pmgbase[0] = channel->mem_resource->start |
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#ifdef __BIG_ENDIAN
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TX4938_PCIC_G2PMnGBASE_ECHG
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#else
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TX4938_PCIC_G2PMnGBASE_BSDIS
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#endif
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;
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219 |
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pcicptr->g2pmpbase[0] = channel->mem_resource->start;
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}
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/* PCI->GB mappings (I/O 256B) */
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pcicptr->p2giopbase = 0; /* 256B */
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pcicptr->p2giogbase = 0;
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/* PCI->GB mappings (MEM 512MB (64MB on R1.x)) */
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pcicptr->p2gm0plbase = 0;
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pcicptr->p2gm0pubase = 0;
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227 |
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pcicptr->p2gmgbase[0] = 0 |
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TX4938_PCIC_P2GMnGBASE_TMEMEN |
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#ifdef __BIG_ENDIAN
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TX4938_PCIC_P2GMnGBASE_TECHG
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#else
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TX4938_PCIC_P2GMnGBASE_TBSDIS
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#endif
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;
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/* PCI->GB mappings (MEM 16MB) */
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pcicptr->p2gm1plbase = 0xffffffff;
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pcicptr->p2gm1pubase = 0xffffffff;
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pcicptr->p2gmgbase[1] = 0;
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239 |
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/* PCI->GB mappings (MEM 1MB) */
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pcicptr->p2gm2pbase = 0xffffffff; /* 1MB */
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241 |
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pcicptr->p2gmgbase[2] = 0;
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243 |
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pcicptr->pciccfg &= TX4938_PCIC_PCICCFG_GBWC_MASK;
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244 |
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/* Enable Initiator Memory Space */
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245 |
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if (channel->mem_resource->end)
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246 |
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pcicptr->pciccfg |= TX4938_PCIC_PCICCFG_G2PMEN(0);
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247 |
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/* Enable Initiator I/O Space */
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248 |
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if (channel->io_resource->end)
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249 |
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pcicptr->pciccfg |= TX4938_PCIC_PCICCFG_G2PIOEN;
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250 |
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/* Enable Initiator Config */
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251 |
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pcicptr->pciccfg |=
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252 |
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TX4938_PCIC_PCICCFG_ICAEN |
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253 |
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TX4938_PCIC_PCICCFG_TCAR;
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255 |
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/* Do not use MEMMUL, MEMINF: YMFPCI card causes M_ABORT. */
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256 |
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pcicptr->pcicfg1 = 0;
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257 |
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258 |
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pcicptr->g2ptocnt &= ~0xffff;
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259 |
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260 |
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if (tx4938_pcic_trdyto >= 0) {
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261 |
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pcicptr->g2ptocnt &= ~0xff;
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262 |
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pcicptr->g2ptocnt |= (tx4938_pcic_trdyto & 0xff);
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263 |
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}
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264 |
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265 |
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if (tx4938_pcic_retryto >= 0) {
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266 |
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pcicptr->g2ptocnt &= ~0xff00;
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267 |
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pcicptr->g2ptocnt |= ((tx4938_pcic_retryto<<8) & 0xff00);
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268 |
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}
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269 |
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|
270 |
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/* Clear All Local Bus Status */
|
271 |
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pcicptr->pcicstatus = TX4938_PCIC_PCICSTATUS_ALL;
|
272 |
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/* Enable All Local Bus Interrupts */
|
273 |
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pcicptr->pcicmask = TX4938_PCIC_PCICSTATUS_ALL;
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274 |
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/* Clear All Initiator Status */
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275 |
|
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pcicptr->g2pstatus = TX4938_PCIC_G2PSTATUS_ALL;
|
276 |
|
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/* Enable All Initiator Interrupts */
|
277 |
|
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pcicptr->g2pmask = TX4938_PCIC_G2PSTATUS_ALL;
|
278 |
|
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/* Clear All PCI Status Error */
|
279 |
|
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pcicptr->pcistatus =
|
280 |
|
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(pcicptr->pcistatus & 0x0000ffff) |
|
281 |
|
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(TX4938_PCIC_PCISTATUS_ALL << 16);
|
282 |
|
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/* Enable All PCI Status Error Interrupts */
|
283 |
|
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pcicptr->pcimask = TX4938_PCIC_PCISTATUS_ALL;
|
284 |
|
|
|
285 |
|
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if (!extarb) {
|
286 |
|
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/* Reset Bus Arbiter */
|
287 |
|
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pcicptr->pbacfg = TX4938_PCIC_PBACFG_RPBA;
|
288 |
|
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pcicptr->pbabm = 0;
|
289 |
|
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/* Enable Bus Arbiter */
|
290 |
|
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pcicptr->pbacfg = TX4938_PCIC_PBACFG_PBAEN;
|
291 |
|
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}
|
292 |
|
|
|
293 |
|
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/* PCIC Int => IRC IRQ16 */
|
294 |
|
|
pcicptr->pcicfg2 =
|
295 |
|
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(pcicptr->pcicfg2 & 0xffffff00) | TX4938_IR_PCIC;
|
296 |
|
|
|
297 |
|
|
pcicptr->pcistatus = PCI_COMMAND_MASTER |
|
298 |
|
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PCI_COMMAND_MEMORY |
|
299 |
|
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PCI_COMMAND_PARITY | PCI_COMMAND_SERR;
|
300 |
|
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}
|
301 |
|
|
|
302 |
|
|
int __init
|
303 |
|
|
tx4938_report_pciclk(void)
|
304 |
|
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{
|
305 |
|
|
unsigned long pcode = TX4938_REV_PCODE();
|
306 |
|
|
int pciclk = 0;
|
307 |
|
|
printk("TX%lx PCIC --%s PCICLK:",
|
308 |
|
|
pcode,
|
309 |
|
|
(tx4938_ccfgptr->ccfg & TX4938_CCFG_PCI66) ? " PCI66" : "");
|
310 |
|
|
if (tx4938_ccfgptr->pcfg & TX4938_PCFG_PCICLKEN_ALL) {
|
311 |
|
|
|
312 |
|
|
switch ((unsigned long)tx4938_ccfgptr->ccfg & TX4938_CCFG_PCIDIVMODE_MASK) {
|
313 |
|
|
case TX4938_CCFG_PCIDIVMODE_4:
|
314 |
|
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pciclk = txx9_cpu_clock / 4; break;
|
315 |
|
|
case TX4938_CCFG_PCIDIVMODE_4_5:
|
316 |
|
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pciclk = txx9_cpu_clock * 2 / 9; break;
|
317 |
|
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case TX4938_CCFG_PCIDIVMODE_5:
|
318 |
|
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pciclk = txx9_cpu_clock / 5; break;
|
319 |
|
|
case TX4938_CCFG_PCIDIVMODE_5_5:
|
320 |
|
|
pciclk = txx9_cpu_clock * 2 / 11; break;
|
321 |
|
|
case TX4938_CCFG_PCIDIVMODE_8:
|
322 |
|
|
pciclk = txx9_cpu_clock / 8; break;
|
323 |
|
|
case TX4938_CCFG_PCIDIVMODE_9:
|
324 |
|
|
pciclk = txx9_cpu_clock / 9; break;
|
325 |
|
|
case TX4938_CCFG_PCIDIVMODE_10:
|
326 |
|
|
pciclk = txx9_cpu_clock / 10; break;
|
327 |
|
|
case TX4938_CCFG_PCIDIVMODE_11:
|
328 |
|
|
pciclk = txx9_cpu_clock / 11; break;
|
329 |
|
|
}
|
330 |
|
|
printk("Internal(%dMHz)", pciclk / 1000000);
|
331 |
|
|
} else {
|
332 |
|
|
printk("External");
|
333 |
|
|
pciclk = -1;
|
334 |
|
|
}
|
335 |
|
|
printk("\n");
|
336 |
|
|
return pciclk;
|
337 |
|
|
}
|
338 |
|
|
|
339 |
|
|
void __init set_tx4938_pcicptr(int ch, struct tx4938_pcic_reg *pcicptr)
|
340 |
|
|
{
|
341 |
|
|
pcicptrs[ch] = pcicptr;
|
342 |
|
|
}
|
343 |
|
|
|
344 |
|
|
struct tx4938_pcic_reg *get_tx4938_pcicptr(int ch)
|
345 |
|
|
{
|
346 |
|
|
return pcicptrs[ch];
|
347 |
|
|
}
|
348 |
|
|
|
349 |
|
|
static struct pci_dev *fake_pci_dev(struct pci_controller *hose,
|
350 |
|
|
int top_bus, int busnr, int devfn)
|
351 |
|
|
{
|
352 |
|
|
static struct pci_dev dev;
|
353 |
|
|
static struct pci_bus bus;
|
354 |
|
|
|
355 |
|
|
dev.sysdata = bus.sysdata = hose;
|
356 |
|
|
dev.devfn = devfn;
|
357 |
|
|
bus.number = busnr;
|
358 |
|
|
bus.ops = hose->pci_ops;
|
359 |
|
|
bus.parent = NULL;
|
360 |
|
|
dev.bus = &bus;
|
361 |
|
|
|
362 |
|
|
return &dev;
|
363 |
|
|
}
|
364 |
|
|
|
365 |
|
|
#define EARLY_PCI_OP(rw, size, type) \
|
366 |
|
|
static int early_##rw##_config_##size(struct pci_controller *hose, \
|
367 |
|
|
int top_bus, int bus, int devfn, int offset, type value) \
|
368 |
|
|
{ \
|
369 |
|
|
return pci_##rw##_config_##size( \
|
370 |
|
|
fake_pci_dev(hose, top_bus, bus, devfn), \
|
371 |
|
|
offset, value); \
|
372 |
|
|
}
|
373 |
|
|
|
374 |
|
|
EARLY_PCI_OP(read, word, u16 *)
|
375 |
|
|
|
376 |
|
|
int txboard_pci66_check(struct pci_controller *hose, int top_bus, int current_bus)
|
377 |
|
|
{
|
378 |
|
|
u32 pci_devfn;
|
379 |
|
|
unsigned short vid;
|
380 |
|
|
int devfn_start = 0;
|
381 |
|
|
int devfn_stop = 0xff;
|
382 |
|
|
int cap66 = -1;
|
383 |
|
|
u16 stat;
|
384 |
|
|
|
385 |
|
|
printk("PCI: Checking 66MHz capabilities...\n");
|
386 |
|
|
|
387 |
|
|
for (pci_devfn=devfn_start; pci_devfn<devfn_stop; pci_devfn++) {
|
388 |
|
|
if (early_read_config_word(hose, top_bus, current_bus,
|
389 |
|
|
pci_devfn, PCI_VENDOR_ID,
|
390 |
|
|
&vid) != PCIBIOS_SUCCESSFUL)
|
391 |
|
|
continue;
|
392 |
|
|
|
393 |
|
|
if (vid == 0xffff) continue;
|
394 |
|
|
|
395 |
|
|
/* check 66MHz capability */
|
396 |
|
|
if (cap66 < 0)
|
397 |
|
|
cap66 = 1;
|
398 |
|
|
if (cap66) {
|
399 |
|
|
early_read_config_word(hose, top_bus, current_bus, pci_devfn,
|
400 |
|
|
PCI_STATUS, &stat);
|
401 |
|
|
if (!(stat & PCI_STATUS_66MHZ)) {
|
402 |
|
|
printk(KERN_DEBUG "PCI: %02x:%02x not 66MHz capable.\n",
|
403 |
|
|
current_bus, pci_devfn);
|
404 |
|
|
cap66 = 0;
|
405 |
|
|
break;
|
406 |
|
|
}
|
407 |
|
|
}
|
408 |
|
|
}
|
409 |
|
|
return cap66 > 0;
|
410 |
|
|
}
|
411 |
|
|
|
412 |
|
|
int __init
|
413 |
|
|
tx4938_pciclk66_setup(void)
|
414 |
|
|
{
|
415 |
|
|
int pciclk;
|
416 |
|
|
|
417 |
|
|
/* Assert M66EN */
|
418 |
|
|
tx4938_ccfgptr->ccfg |= TX4938_CCFG_PCI66;
|
419 |
|
|
/* Double PCICLK (if possible) */
|
420 |
|
|
if (tx4938_ccfgptr->pcfg & TX4938_PCFG_PCICLKEN_ALL) {
|
421 |
|
|
unsigned int pcidivmode =
|
422 |
|
|
tx4938_ccfgptr->ccfg & TX4938_CCFG_PCIDIVMODE_MASK;
|
423 |
|
|
switch (pcidivmode) {
|
424 |
|
|
case TX4938_CCFG_PCIDIVMODE_8:
|
425 |
|
|
case TX4938_CCFG_PCIDIVMODE_4:
|
426 |
|
|
pcidivmode = TX4938_CCFG_PCIDIVMODE_4;
|
427 |
|
|
pciclk = txx9_cpu_clock / 4;
|
428 |
|
|
break;
|
429 |
|
|
case TX4938_CCFG_PCIDIVMODE_9:
|
430 |
|
|
case TX4938_CCFG_PCIDIVMODE_4_5:
|
431 |
|
|
pcidivmode = TX4938_CCFG_PCIDIVMODE_4_5;
|
432 |
|
|
pciclk = txx9_cpu_clock * 2 / 9;
|
433 |
|
|
break;
|
434 |
|
|
case TX4938_CCFG_PCIDIVMODE_10:
|
435 |
|
|
case TX4938_CCFG_PCIDIVMODE_5:
|
436 |
|
|
pcidivmode = TX4938_CCFG_PCIDIVMODE_5;
|
437 |
|
|
pciclk = txx9_cpu_clock / 5;
|
438 |
|
|
break;
|
439 |
|
|
case TX4938_CCFG_PCIDIVMODE_11:
|
440 |
|
|
case TX4938_CCFG_PCIDIVMODE_5_5:
|
441 |
|
|
default:
|
442 |
|
|
pcidivmode = TX4938_CCFG_PCIDIVMODE_5_5;
|
443 |
|
|
pciclk = txx9_cpu_clock * 2 / 11;
|
444 |
|
|
break;
|
445 |
|
|
}
|
446 |
|
|
tx4938_ccfgptr->ccfg =
|
447 |
|
|
(tx4938_ccfgptr->ccfg & ~TX4938_CCFG_PCIDIVMODE_MASK)
|
448 |
|
|
| pcidivmode;
|
449 |
|
|
printk(KERN_DEBUG "PCICLK: ccfg:%08lx\n",
|
450 |
|
|
(unsigned long)tx4938_ccfgptr->ccfg);
|
451 |
|
|
} else {
|
452 |
|
|
pciclk = -1;
|
453 |
|
|
}
|
454 |
|
|
return pciclk;
|
455 |
|
|
}
|
456 |
|
|
|
457 |
|
|
extern struct pci_controller tx4938_pci_controller[];
|
458 |
|
|
static int __init tx4938_pcibios_init(void)
|
459 |
|
|
{
|
460 |
|
|
unsigned long mem_base[2];
|
461 |
|
|
unsigned long mem_size[2] = {TX4938_PCIMEM_SIZE_0, TX4938_PCIMEM_SIZE_1}; /* MAX 128M,64K */
|
462 |
|
|
unsigned long io_base[2];
|
463 |
|
|
unsigned long io_size[2] = {TX4938_PCIIO_SIZE_0, TX4938_PCIIO_SIZE_1}; /* MAX 16M,64K */
|
464 |
|
|
/* TX4938 PCIC1: 64K MEM/IO is enough for ETH0,ETH1 */
|
465 |
|
|
int extarb = !(tx4938_ccfgptr->ccfg & TX4938_CCFG_PCIXARB);
|
466 |
|
|
|
467 |
|
|
PCIBIOS_MIN_IO = 0x00001000UL;
|
468 |
|
|
|
469 |
|
|
mem_base[0] = txboard_request_phys_region_shrink(&mem_size[0]);
|
470 |
|
|
io_base[0] = txboard_request_phys_region_shrink(&io_size[0]);
|
471 |
|
|
|
472 |
|
|
printk("TX4938 PCIC -- DID:%04x VID:%04x RID:%02x Arbiter:%s\n",
|
473 |
|
|
(unsigned short)(tx4938_pcicptr->pciid >> 16),
|
474 |
|
|
(unsigned short)(tx4938_pcicptr->pciid & 0xffff),
|
475 |
|
|
(unsigned short)(tx4938_pcicptr->pciccrev & 0xff),
|
476 |
|
|
extarb ? "External" : "Internal");
|
477 |
|
|
|
478 |
|
|
/* setup PCI area */
|
479 |
|
|
tx4938_pci_controller[0].io_resource->start = io_base[0];
|
480 |
|
|
tx4938_pci_controller[0].io_resource->end = (io_base[0] + io_size[0]) - 1;
|
481 |
|
|
tx4938_pci_controller[0].mem_resource->start = mem_base[0];
|
482 |
|
|
tx4938_pci_controller[0].mem_resource->end = mem_base[0] + mem_size[0] - 1;
|
483 |
|
|
|
484 |
|
|
set_tx4938_pcicptr(0, tx4938_pcicptr);
|
485 |
|
|
|
486 |
|
|
register_pci_controller(&tx4938_pci_controller[0]);
|
487 |
|
|
|
488 |
|
|
if (tx4938_ccfgptr->ccfg & TX4938_CCFG_PCI66) {
|
489 |
|
|
printk("TX4938_CCFG_PCI66 already configured\n");
|
490 |
|
|
txboard_pci66_mode = -1; /* already configured */
|
491 |
|
|
}
|
492 |
|
|
|
493 |
|
|
/* Reset PCI Bus */
|
494 |
|
|
*rbtx4938_pcireset_ptr = 0;
|
495 |
|
|
/* Reset PCIC */
|
496 |
|
|
tx4938_ccfgptr->clkctr |= TX4938_CLKCTR_PCIRST;
|
497 |
|
|
if (txboard_pci66_mode > 0)
|
498 |
|
|
tx4938_pciclk66_setup();
|
499 |
|
|
mdelay(10);
|
500 |
|
|
/* clear PCIC reset */
|
501 |
|
|
tx4938_ccfgptr->clkctr &= ~TX4938_CLKCTR_PCIRST;
|
502 |
|
|
*rbtx4938_pcireset_ptr = 1;
|
503 |
|
|
wbflush();
|
504 |
|
|
tx4938_report_pcic_status1(tx4938_pcicptr);
|
505 |
|
|
|
506 |
|
|
tx4938_report_pciclk();
|
507 |
|
|
tx4938_pcic_setup(tx4938_pcicptr, &tx4938_pci_controller[0], io_base[0], extarb);
|
508 |
|
|
if (txboard_pci66_mode == 0 &&
|
509 |
|
|
txboard_pci66_check(&tx4938_pci_controller[0], 0, 0)) {
|
510 |
|
|
/* Reset PCI Bus */
|
511 |
|
|
*rbtx4938_pcireset_ptr = 0;
|
512 |
|
|
/* Reset PCIC */
|
513 |
|
|
tx4938_ccfgptr->clkctr |= TX4938_CLKCTR_PCIRST;
|
514 |
|
|
tx4938_pciclk66_setup();
|
515 |
|
|
mdelay(10);
|
516 |
|
|
/* clear PCIC reset */
|
517 |
|
|
tx4938_ccfgptr->clkctr &= ~TX4938_CLKCTR_PCIRST;
|
518 |
|
|
*rbtx4938_pcireset_ptr = 1;
|
519 |
|
|
wbflush();
|
520 |
|
|
/* Reinitialize PCIC */
|
521 |
|
|
tx4938_report_pciclk();
|
522 |
|
|
tx4938_pcic_setup(tx4938_pcicptr, &tx4938_pci_controller[0], io_base[0], extarb);
|
523 |
|
|
}
|
524 |
|
|
|
525 |
|
|
mem_base[1] = txboard_request_phys_region_shrink(&mem_size[1]);
|
526 |
|
|
io_base[1] = txboard_request_phys_region_shrink(&io_size[1]);
|
527 |
|
|
/* Reset PCIC1 */
|
528 |
|
|
tx4938_ccfgptr->clkctr |= TX4938_CLKCTR_PCIC1RST;
|
529 |
|
|
/* PCI1DMD==0 => PCI1CLK==GBUSCLK/2 => PCI66 */
|
530 |
|
|
if (!(tx4938_ccfgptr->ccfg & TX4938_CCFG_PCI1DMD))
|
531 |
|
|
tx4938_ccfgptr->ccfg |= TX4938_CCFG_PCI1_66;
|
532 |
|
|
else
|
533 |
|
|
tx4938_ccfgptr->ccfg &= ~TX4938_CCFG_PCI1_66;
|
534 |
|
|
mdelay(10);
|
535 |
|
|
/* clear PCIC1 reset */
|
536 |
|
|
tx4938_ccfgptr->clkctr &= ~TX4938_CLKCTR_PCIC1RST;
|
537 |
|
|
tx4938_report_pcic_status1(tx4938_pcic1ptr);
|
538 |
|
|
|
539 |
|
|
printk("TX4938 PCIC1 -- DID:%04x VID:%04x RID:%02x",
|
540 |
|
|
(unsigned short)(tx4938_pcic1ptr->pciid >> 16),
|
541 |
|
|
(unsigned short)(tx4938_pcic1ptr->pciid & 0xffff),
|
542 |
|
|
(unsigned short)(tx4938_pcic1ptr->pciccrev & 0xff));
|
543 |
|
|
printk("%s PCICLK:%dMHz\n",
|
544 |
|
|
(tx4938_ccfgptr->ccfg & TX4938_CCFG_PCI1_66) ? " PCI66" : "",
|
545 |
|
|
txx9_gbus_clock /
|
546 |
|
|
((tx4938_ccfgptr->ccfg & TX4938_CCFG_PCI1DMD) ? 4 : 2) /
|
547 |
|
|
1000000);
|
548 |
|
|
|
549 |
|
|
/* assumption: CPHYSADDR(mips_io_port_base) == io_base[0] */
|
550 |
|
|
tx4938_pci_controller[1].io_resource->start =
|
551 |
|
|
io_base[1] - io_base[0];
|
552 |
|
|
tx4938_pci_controller[1].io_resource->end =
|
553 |
|
|
io_base[1] - io_base[0] + io_size[1] - 1;
|
554 |
|
|
tx4938_pci_controller[1].mem_resource->start = mem_base[1];
|
555 |
|
|
tx4938_pci_controller[1].mem_resource->end =
|
556 |
|
|
mem_base[1] + mem_size[1] - 1;
|
557 |
|
|
set_tx4938_pcicptr(1, tx4938_pcic1ptr);
|
558 |
|
|
|
559 |
|
|
register_pci_controller(&tx4938_pci_controller[1]);
|
560 |
|
|
|
561 |
|
|
tx4938_pcic_setup(tx4938_pcic1ptr, &tx4938_pci_controller[1], io_base[1], extarb);
|
562 |
|
|
|
563 |
|
|
/* map ioport 0 to PCI I/O space address 0 */
|
564 |
|
|
set_io_port_base(KSEG1 + io_base[0]);
|
565 |
|
|
|
566 |
|
|
return 0;
|
567 |
|
|
}
|
568 |
|
|
|
569 |
|
|
arch_initcall(tx4938_pcibios_init);
|
570 |
|
|
|
571 |
|
|
#endif /* CONFIG_PCI */
|
572 |
|
|
|
573 |
|
|
/* SPI support */
|
574 |
|
|
|
575 |
|
|
/* chip select for SPI devices */
|
576 |
|
|
#define SEEPROM1_CS 7 /* PIO7 */
|
577 |
|
|
#define SEEPROM2_CS 0 /* IOC */
|
578 |
|
|
#define SEEPROM3_CS 1 /* IOC */
|
579 |
|
|
#define SRTC_CS 2 /* IOC */
|
580 |
|
|
|
581 |
|
|
#ifdef CONFIG_PCI
|
582 |
|
|
static int __init rbtx4938_ethaddr_init(void)
|
583 |
|
|
{
|
584 |
|
|
unsigned char dat[17];
|
585 |
|
|
unsigned char sum;
|
586 |
|
|
int i;
|
587 |
|
|
|
588 |
|
|
/* 0-3: "MAC\0", 4-9:eth0, 10-15:eth1, 16:sum */
|
589 |
|
|
if (spi_eeprom_read(SEEPROM1_CS, 0, dat, sizeof(dat))) {
|
590 |
|
|
printk(KERN_ERR "seeprom: read error.\n");
|
591 |
|
|
return -ENODEV;
|
592 |
|
|
} else {
|
593 |
|
|
if (strcmp(dat, "MAC") != 0)
|
594 |
|
|
printk(KERN_WARNING "seeprom: bad signature.\n");
|
595 |
|
|
for (i = 0, sum = 0; i < sizeof(dat); i++)
|
596 |
|
|
sum += dat[i];
|
597 |
|
|
if (sum)
|
598 |
|
|
printk(KERN_WARNING "seeprom: bad checksum.\n");
|
599 |
|
|
}
|
600 |
|
|
for (i = 0; i < 2; i++) {
|
601 |
|
|
unsigned int id =
|
602 |
|
|
TXX9_IRQ_BASE + (i ? TX4938_IR_ETH1 : TX4938_IR_ETH0);
|
603 |
|
|
struct platform_device *pdev;
|
604 |
|
|
if (!(tx4938_ccfgptr->pcfg &
|
605 |
|
|
(i ? TX4938_PCFG_ETH1_SEL : TX4938_PCFG_ETH0_SEL)))
|
606 |
|
|
continue;
|
607 |
|
|
pdev = platform_device_alloc("tc35815-mac", id);
|
608 |
|
|
if (!pdev ||
|
609 |
|
|
platform_device_add_data(pdev, &dat[4 + 6 * i], 6) ||
|
610 |
|
|
platform_device_add(pdev))
|
611 |
|
|
platform_device_put(pdev);
|
612 |
|
|
}
|
613 |
|
|
return 0;
|
614 |
|
|
}
|
615 |
|
|
device_initcall(rbtx4938_ethaddr_init);
|
616 |
|
|
#endif /* CONFIG_PCI */
|
617 |
|
|
|
618 |
|
|
static void __init rbtx4938_spi_setup(void)
|
619 |
|
|
{
|
620 |
|
|
/* set SPI_SEL */
|
621 |
|
|
tx4938_ccfgptr->pcfg |= TX4938_PCFG_SPI_SEL;
|
622 |
|
|
/* chip selects for SPI devices */
|
623 |
|
|
tx4938_pioptr->dout |= (1 << SEEPROM1_CS);
|
624 |
|
|
tx4938_pioptr->dir |= (1 << SEEPROM1_CS);
|
625 |
|
|
}
|
626 |
|
|
|
627 |
|
|
static struct resource rbtx4938_fpga_resource;
|
628 |
|
|
|
629 |
|
|
static char pcode_str[8];
|
630 |
|
|
static struct resource tx4938_reg_resource = {
|
631 |
|
|
.start = TX4938_REG_BASE,
|
632 |
|
|
.end = TX4938_REG_BASE + TX4938_REG_SIZE,
|
633 |
|
|
.name = pcode_str,
|
634 |
|
|
.flags = IORESOURCE_MEM
|
635 |
|
|
};
|
636 |
|
|
|
637 |
|
|
void __init tx4938_board_setup(void)
|
638 |
|
|
{
|
639 |
|
|
int i;
|
640 |
|
|
unsigned long divmode;
|
641 |
|
|
int cpuclk = 0;
|
642 |
|
|
unsigned long pcode = TX4938_REV_PCODE();
|
643 |
|
|
|
644 |
|
|
ioport_resource.start = 0x1000;
|
645 |
|
|
ioport_resource.end = 0xffffffff;
|
646 |
|
|
iomem_resource.start = 0x1000;
|
647 |
|
|
iomem_resource.end = 0xffffffff; /* expand to 4GB */
|
648 |
|
|
|
649 |
|
|
sprintf(pcode_str, "TX%lx", pcode);
|
650 |
|
|
/* SDRAMC,EBUSC are configured by PROM */
|
651 |
|
|
for (i = 0; i < 8; i++) {
|
652 |
|
|
if (!(tx4938_ebuscptr->cr[i] & 0x8))
|
653 |
|
|
continue; /* disabled */
|
654 |
|
|
rbtx4938_ce_base[i] = (unsigned long)TX4938_EBUSC_BA(i);
|
655 |
|
|
txboard_add_phys_region(rbtx4938_ce_base[i], TX4938_EBUSC_SIZE(i));
|
656 |
|
|
}
|
657 |
|
|
|
658 |
|
|
/* clocks */
|
659 |
|
|
if (txx9_master_clock) {
|
660 |
|
|
/* calculate gbus_clock and cpu_clock_freq from master_clock */
|
661 |
|
|
divmode = (unsigned long)tx4938_ccfgptr->ccfg & TX4938_CCFG_DIVMODE_MASK;
|
662 |
|
|
switch (divmode) {
|
663 |
|
|
case TX4938_CCFG_DIVMODE_8:
|
664 |
|
|
case TX4938_CCFG_DIVMODE_10:
|
665 |
|
|
case TX4938_CCFG_DIVMODE_12:
|
666 |
|
|
case TX4938_CCFG_DIVMODE_16:
|
667 |
|
|
case TX4938_CCFG_DIVMODE_18:
|
668 |
|
|
txx9_gbus_clock = txx9_master_clock * 4; break;
|
669 |
|
|
default:
|
670 |
|
|
txx9_gbus_clock = txx9_master_clock;
|
671 |
|
|
}
|
672 |
|
|
switch (divmode) {
|
673 |
|
|
case TX4938_CCFG_DIVMODE_2:
|
674 |
|
|
case TX4938_CCFG_DIVMODE_8:
|
675 |
|
|
cpuclk = txx9_gbus_clock * 2; break;
|
676 |
|
|
case TX4938_CCFG_DIVMODE_2_5:
|
677 |
|
|
case TX4938_CCFG_DIVMODE_10:
|
678 |
|
|
cpuclk = txx9_gbus_clock * 5 / 2; break;
|
679 |
|
|
case TX4938_CCFG_DIVMODE_3:
|
680 |
|
|
case TX4938_CCFG_DIVMODE_12:
|
681 |
|
|
cpuclk = txx9_gbus_clock * 3; break;
|
682 |
|
|
case TX4938_CCFG_DIVMODE_4:
|
683 |
|
|
case TX4938_CCFG_DIVMODE_16:
|
684 |
|
|
cpuclk = txx9_gbus_clock * 4; break;
|
685 |
|
|
case TX4938_CCFG_DIVMODE_4_5:
|
686 |
|
|
case TX4938_CCFG_DIVMODE_18:
|
687 |
|
|
cpuclk = txx9_gbus_clock * 9 / 2; break;
|
688 |
|
|
}
|
689 |
|
|
txx9_cpu_clock = cpuclk;
|
690 |
|
|
} else {
|
691 |
|
|
if (txx9_cpu_clock == 0) {
|
692 |
|
|
txx9_cpu_clock = 300000000; /* 300MHz */
|
693 |
|
|
}
|
694 |
|
|
/* calculate gbus_clock and master_clock from cpu_clock_freq */
|
695 |
|
|
cpuclk = txx9_cpu_clock;
|
696 |
|
|
divmode = (unsigned long)tx4938_ccfgptr->ccfg & TX4938_CCFG_DIVMODE_MASK;
|
697 |
|
|
switch (divmode) {
|
698 |
|
|
case TX4938_CCFG_DIVMODE_2:
|
699 |
|
|
case TX4938_CCFG_DIVMODE_8:
|
700 |
|
|
txx9_gbus_clock = cpuclk / 2; break;
|
701 |
|
|
case TX4938_CCFG_DIVMODE_2_5:
|
702 |
|
|
case TX4938_CCFG_DIVMODE_10:
|
703 |
|
|
txx9_gbus_clock = cpuclk * 2 / 5; break;
|
704 |
|
|
case TX4938_CCFG_DIVMODE_3:
|
705 |
|
|
case TX4938_CCFG_DIVMODE_12:
|
706 |
|
|
txx9_gbus_clock = cpuclk / 3; break;
|
707 |
|
|
case TX4938_CCFG_DIVMODE_4:
|
708 |
|
|
case TX4938_CCFG_DIVMODE_16:
|
709 |
|
|
txx9_gbus_clock = cpuclk / 4; break;
|
710 |
|
|
case TX4938_CCFG_DIVMODE_4_5:
|
711 |
|
|
case TX4938_CCFG_DIVMODE_18:
|
712 |
|
|
txx9_gbus_clock = cpuclk * 2 / 9; break;
|
713 |
|
|
}
|
714 |
|
|
switch (divmode) {
|
715 |
|
|
case TX4938_CCFG_DIVMODE_8:
|
716 |
|
|
case TX4938_CCFG_DIVMODE_10:
|
717 |
|
|
case TX4938_CCFG_DIVMODE_12:
|
718 |
|
|
case TX4938_CCFG_DIVMODE_16:
|
719 |
|
|
case TX4938_CCFG_DIVMODE_18:
|
720 |
|
|
txx9_master_clock = txx9_gbus_clock / 4; break;
|
721 |
|
|
default:
|
722 |
|
|
txx9_master_clock = txx9_gbus_clock;
|
723 |
|
|
}
|
724 |
|
|
}
|
725 |
|
|
/* change default value to udelay/mdelay take reasonable time */
|
726 |
|
|
loops_per_jiffy = txx9_cpu_clock / HZ / 2;
|
727 |
|
|
|
728 |
|
|
/* CCFG */
|
729 |
|
|
/* clear WatchDogReset,BusErrorOnWrite flag (W1C) */
|
730 |
|
|
tx4938_ccfgptr->ccfg |= TX4938_CCFG_WDRST | TX4938_CCFG_BEOW;
|
731 |
|
|
/* clear PCIC1 reset */
|
732 |
|
|
if (tx4938_ccfgptr->clkctr & TX4938_CLKCTR_PCIC1RST)
|
733 |
|
|
tx4938_ccfgptr->clkctr &= ~TX4938_CLKCTR_PCIC1RST;
|
734 |
|
|
|
735 |
|
|
/* enable Timeout BusError */
|
736 |
|
|
if (tx4938_ccfg_toeon)
|
737 |
|
|
tx4938_ccfgptr->ccfg |= TX4938_CCFG_TOE;
|
738 |
|
|
|
739 |
|
|
/* DMA selection */
|
740 |
|
|
tx4938_ccfgptr->pcfg &= ~TX4938_PCFG_DMASEL_ALL;
|
741 |
|
|
|
742 |
|
|
/* Use external clock for external arbiter */
|
743 |
|
|
if (!(tx4938_ccfgptr->ccfg & TX4938_CCFG_PCIXARB))
|
744 |
|
|
tx4938_ccfgptr->pcfg &= ~TX4938_PCFG_PCICLKEN_ALL;
|
745 |
|
|
|
746 |
|
|
printk("%s -- %dMHz(M%dMHz) CRIR:%08lx CCFG:%Lx PCFG:%Lx\n",
|
747 |
|
|
pcode_str,
|
748 |
|
|
cpuclk / 1000000, txx9_master_clock / 1000000,
|
749 |
|
|
(unsigned long)tx4938_ccfgptr->crir,
|
750 |
|
|
tx4938_ccfgptr->ccfg,
|
751 |
|
|
tx4938_ccfgptr->pcfg);
|
752 |
|
|
|
753 |
|
|
printk("%s SDRAMC --", pcode_str);
|
754 |
|
|
for (i = 0; i < 4; i++) {
|
755 |
|
|
unsigned long long cr = tx4938_sdramcptr->cr[i];
|
756 |
|
|
unsigned long ram_base, ram_size;
|
757 |
|
|
if (!((unsigned long)cr & 0x00000400))
|
758 |
|
|
continue; /* disabled */
|
759 |
|
|
ram_base = (unsigned long)(cr >> 49) << 21;
|
760 |
|
|
ram_size = ((unsigned long)(cr >> 33) + 1) << 21;
|
761 |
|
|
if (ram_base >= 0x20000000)
|
762 |
|
|
continue; /* high memory (ignore) */
|
763 |
|
|
printk(" CR%d:%016Lx", i, cr);
|
764 |
|
|
txboard_add_phys_region(ram_base, ram_size);
|
765 |
|
|
}
|
766 |
|
|
printk(" TR:%09Lx\n", tx4938_sdramcptr->tr);
|
767 |
|
|
|
768 |
|
|
/* SRAM */
|
769 |
|
|
if (pcode == 0x4938 && tx4938_sramcptr->cr & 1) {
|
770 |
|
|
unsigned int size = 0x800;
|
771 |
|
|
unsigned long base =
|
772 |
|
|
(tx4938_sramcptr->cr >> (39-11)) & ~(size - 1);
|
773 |
|
|
txboard_add_phys_region(base, size);
|
774 |
|
|
}
|
775 |
|
|
|
776 |
|
|
/* TMR */
|
777 |
|
|
for (i = 0; i < TX4938_NR_TMR; i++)
|
778 |
|
|
txx9_tmr_init(TX4938_TMR_REG(i) & 0xfffffffffULL);
|
779 |
|
|
|
780 |
|
|
/* enable DMA */
|
781 |
|
|
TX4938_WR64(0xff1fb150, TX4938_DMA_MCR_MSTEN);
|
782 |
|
|
TX4938_WR64(0xff1fb950, TX4938_DMA_MCR_MSTEN);
|
783 |
|
|
|
784 |
|
|
/* PIO */
|
785 |
|
|
tx4938_pioptr->maskcpu = 0;
|
786 |
|
|
tx4938_pioptr->maskext = 0;
|
787 |
|
|
|
788 |
|
|
/* TX4938 internal registers */
|
789 |
|
|
if (request_resource(&iomem_resource, &tx4938_reg_resource))
|
790 |
|
|
printk("request resource for internal registers failed\n");
|
791 |
|
|
}
|
792 |
|
|
|
793 |
|
|
#ifdef CONFIG_PCI
|
794 |
|
|
static inline void tx4938_report_pcic_status1(struct tx4938_pcic_reg *pcicptr)
|
795 |
|
|
{
|
796 |
|
|
unsigned short pcistatus = (unsigned short)(pcicptr->pcistatus >> 16);
|
797 |
|
|
unsigned long g2pstatus = pcicptr->g2pstatus;
|
798 |
|
|
unsigned long pcicstatus = pcicptr->pcicstatus;
|
799 |
|
|
static struct {
|
800 |
|
|
unsigned long flag;
|
801 |
|
|
const char *str;
|
802 |
|
|
} pcistat_tbl[] = {
|
803 |
|
|
{ PCI_STATUS_DETECTED_PARITY, "DetectedParityError" },
|
804 |
|
|
{ PCI_STATUS_SIG_SYSTEM_ERROR, "SignaledSystemError" },
|
805 |
|
|
{ PCI_STATUS_REC_MASTER_ABORT, "ReceivedMasterAbort" },
|
806 |
|
|
{ PCI_STATUS_REC_TARGET_ABORT, "ReceivedTargetAbort" },
|
807 |
|
|
{ PCI_STATUS_SIG_TARGET_ABORT, "SignaledTargetAbort" },
|
808 |
|
|
{ PCI_STATUS_PARITY, "MasterParityError" },
|
809 |
|
|
}, g2pstat_tbl[] = {
|
810 |
|
|
{ TX4938_PCIC_G2PSTATUS_TTOE, "TIOE" },
|
811 |
|
|
{ TX4938_PCIC_G2PSTATUS_RTOE, "RTOE" },
|
812 |
|
|
}, pcicstat_tbl[] = {
|
813 |
|
|
{ TX4938_PCIC_PCICSTATUS_PME, "PME" },
|
814 |
|
|
{ TX4938_PCIC_PCICSTATUS_TLB, "TLB" },
|
815 |
|
|
{ TX4938_PCIC_PCICSTATUS_NIB, "NIB" },
|
816 |
|
|
{ TX4938_PCIC_PCICSTATUS_ZIB, "ZIB" },
|
817 |
|
|
{ TX4938_PCIC_PCICSTATUS_PERR, "PERR" },
|
818 |
|
|
{ TX4938_PCIC_PCICSTATUS_SERR, "SERR" },
|
819 |
|
|
{ TX4938_PCIC_PCICSTATUS_GBE, "GBE" },
|
820 |
|
|
{ TX4938_PCIC_PCICSTATUS_IWB, "IWB" },
|
821 |
|
|
};
|
822 |
|
|
int i;
|
823 |
|
|
|
824 |
|
|
printk("pcistat:%04x(", pcistatus);
|
825 |
|
|
for (i = 0; i < ARRAY_SIZE(pcistat_tbl); i++)
|
826 |
|
|
if (pcistatus & pcistat_tbl[i].flag)
|
827 |
|
|
printk("%s ", pcistat_tbl[i].str);
|
828 |
|
|
printk("), g2pstatus:%08lx(", g2pstatus);
|
829 |
|
|
for (i = 0; i < ARRAY_SIZE(g2pstat_tbl); i++)
|
830 |
|
|
if (g2pstatus & g2pstat_tbl[i].flag)
|
831 |
|
|
printk("%s ", g2pstat_tbl[i].str);
|
832 |
|
|
printk("), pcicstatus:%08lx(", pcicstatus);
|
833 |
|
|
for (i = 0; i < ARRAY_SIZE(pcicstat_tbl); i++)
|
834 |
|
|
if (pcicstatus & pcicstat_tbl[i].flag)
|
835 |
|
|
printk("%s ", pcicstat_tbl[i].str);
|
836 |
|
|
printk(")\n");
|
837 |
|
|
}
|
838 |
|
|
|
839 |
|
|
void tx4938_report_pcic_status(void)
|
840 |
|
|
{
|
841 |
|
|
int i;
|
842 |
|
|
struct tx4938_pcic_reg *pcicptr;
|
843 |
|
|
for (i = 0; (pcicptr = get_tx4938_pcicptr(i)) != NULL; i++)
|
844 |
|
|
tx4938_report_pcic_status1(pcicptr);
|
845 |
|
|
}
|
846 |
|
|
|
847 |
|
|
#endif /* CONFIG_PCI */
|
848 |
|
|
|
849 |
|
|
void __init plat_time_init(void)
|
850 |
|
|
{
|
851 |
|
|
mips_hpt_frequency = txx9_cpu_clock / 2;
|
852 |
|
|
if (tx4938_ccfgptr->ccfg & TX4938_CCFG_TINTDIS)
|
853 |
|
|
txx9_clockevent_init(TX4938_TMR_REG(0) & 0xfffffffffULL,
|
854 |
|
|
TXX9_IRQ_BASE + TX4938_IR_TMR(0),
|
855 |
|
|
txx9_gbus_clock / 2);
|
856 |
|
|
}
|
857 |
|
|
|
858 |
|
|
void __init toshiba_rbtx4938_setup(void)
|
859 |
|
|
{
|
860 |
|
|
unsigned long long pcfg;
|
861 |
|
|
char *argptr;
|
862 |
|
|
|
863 |
|
|
iomem_resource.end = 0xffffffff; /* 4GB */
|
864 |
|
|
|
865 |
|
|
if (txx9_master_clock == 0)
|
866 |
|
|
txx9_master_clock = 25000000; /* 25MHz */
|
867 |
|
|
tx4938_board_setup();
|
868 |
|
|
/* setup serial stuff */
|
869 |
|
|
TX4938_WR(0xff1ff314, 0x00000000); /* h/w flow control off */
|
870 |
|
|
TX4938_WR(0xff1ff414, 0x00000000); /* h/w flow control off */
|
871 |
|
|
|
872 |
|
|
#ifndef CONFIG_PCI
|
873 |
|
|
set_io_port_base(RBTX4938_ETHER_BASE);
|
874 |
|
|
#endif
|
875 |
|
|
|
876 |
|
|
#ifdef CONFIG_SERIAL_TXX9
|
877 |
|
|
{
|
878 |
|
|
extern int early_serial_txx9_setup(struct uart_port *port);
|
879 |
|
|
int i;
|
880 |
|
|
struct uart_port req;
|
881 |
|
|
for(i = 0; i < 2; i++) {
|
882 |
|
|
memset(&req, 0, sizeof(req));
|
883 |
|
|
req.line = i;
|
884 |
|
|
req.iotype = UPIO_MEM;
|
885 |
|
|
req.membase = (char *)(0xff1ff300 + i * 0x100);
|
886 |
|
|
req.mapbase = 0xff1ff300 + i * 0x100;
|
887 |
|
|
req.irq = RBTX4938_IRQ_IRC_SIO(i);
|
888 |
|
|
req.flags |= UPF_BUGGY_UART /*HAVE_CTS_LINE*/;
|
889 |
|
|
req.uartclk = 50000000;
|
890 |
|
|
early_serial_txx9_setup(&req);
|
891 |
|
|
}
|
892 |
|
|
}
|
893 |
|
|
#ifdef CONFIG_SERIAL_TXX9_CONSOLE
|
894 |
|
|
argptr = prom_getcmdline();
|
895 |
|
|
if (strstr(argptr, "console=") == NULL) {
|
896 |
|
|
strcat(argptr, " console=ttyS0,38400");
|
897 |
|
|
}
|
898 |
|
|
#endif
|
899 |
|
|
#endif
|
900 |
|
|
|
901 |
|
|
#ifdef CONFIG_TOSHIBA_RBTX4938_MPLEX_PIO58_61
|
902 |
|
|
printk("PIOSEL: disabling both ata and nand selection\n");
|
903 |
|
|
local_irq_disable();
|
904 |
|
|
tx4938_ccfgptr->pcfg &= ~(TX4938_PCFG_NDF_SEL | TX4938_PCFG_ATA_SEL);
|
905 |
|
|
#endif
|
906 |
|
|
|
907 |
|
|
#ifdef CONFIG_TOSHIBA_RBTX4938_MPLEX_NAND
|
908 |
|
|
printk("PIOSEL: enabling nand selection\n");
|
909 |
|
|
tx4938_ccfgptr->pcfg |= TX4938_PCFG_NDF_SEL;
|
910 |
|
|
tx4938_ccfgptr->pcfg &= ~TX4938_PCFG_ATA_SEL;
|
911 |
|
|
#endif
|
912 |
|
|
|
913 |
|
|
#ifdef CONFIG_TOSHIBA_RBTX4938_MPLEX_ATA
|
914 |
|
|
printk("PIOSEL: enabling ata selection\n");
|
915 |
|
|
tx4938_ccfgptr->pcfg |= TX4938_PCFG_ATA_SEL;
|
916 |
|
|
tx4938_ccfgptr->pcfg &= ~TX4938_PCFG_NDF_SEL;
|
917 |
|
|
#endif
|
918 |
|
|
|
919 |
|
|
#ifdef CONFIG_IP_PNP
|
920 |
|
|
argptr = prom_getcmdline();
|
921 |
|
|
if (strstr(argptr, "ip=") == NULL) {
|
922 |
|
|
strcat(argptr, " ip=any");
|
923 |
|
|
}
|
924 |
|
|
#endif
|
925 |
|
|
|
926 |
|
|
|
927 |
|
|
#ifdef CONFIG_FB
|
928 |
|
|
{
|
929 |
|
|
conswitchp = &dummy_con;
|
930 |
|
|
}
|
931 |
|
|
#endif
|
932 |
|
|
|
933 |
|
|
rbtx4938_spi_setup();
|
934 |
|
|
pcfg = tx4938_ccfgptr->pcfg; /* updated */
|
935 |
|
|
/* fixup piosel */
|
936 |
|
|
if ((pcfg & (TX4938_PCFG_ATA_SEL | TX4938_PCFG_NDF_SEL)) ==
|
937 |
|
|
TX4938_PCFG_ATA_SEL) {
|
938 |
|
|
*rbtx4938_piosel_ptr = (*rbtx4938_piosel_ptr & 0x03) | 0x04;
|
939 |
|
|
}
|
940 |
|
|
else if ((pcfg & (TX4938_PCFG_ATA_SEL | TX4938_PCFG_NDF_SEL)) ==
|
941 |
|
|
TX4938_PCFG_NDF_SEL) {
|
942 |
|
|
*rbtx4938_piosel_ptr = (*rbtx4938_piosel_ptr & 0x03) | 0x08;
|
943 |
|
|
}
|
944 |
|
|
else {
|
945 |
|
|
*rbtx4938_piosel_ptr &= ~(0x08 | 0x04);
|
946 |
|
|
}
|
947 |
|
|
|
948 |
|
|
rbtx4938_fpga_resource.name = "FPGA Registers";
|
949 |
|
|
rbtx4938_fpga_resource.start = CPHYSADDR(RBTX4938_FPGA_REG_ADDR);
|
950 |
|
|
rbtx4938_fpga_resource.end = CPHYSADDR(RBTX4938_FPGA_REG_ADDR) + 0xffff;
|
951 |
|
|
rbtx4938_fpga_resource.flags = IORESOURCE_MEM | IORESOURCE_BUSY;
|
952 |
|
|
if (request_resource(&iomem_resource, &rbtx4938_fpga_resource))
|
953 |
|
|
printk("request resource for fpga failed\n");
|
954 |
|
|
|
955 |
|
|
/* disable all OnBoard I/O interrupts */
|
956 |
|
|
*rbtx4938_imask_ptr = 0;
|
957 |
|
|
|
958 |
|
|
_machine_restart = rbtx4938_machine_restart;
|
959 |
|
|
_machine_halt = rbtx4938_machine_halt;
|
960 |
|
|
pm_power_off = rbtx4938_machine_power_off;
|
961 |
|
|
|
962 |
|
|
*rbtx4938_led_ptr = 0xff;
|
963 |
|
|
printk("RBTX4938 --- FPGA(Rev %02x)", *rbtx4938_fpga_rev_ptr);
|
964 |
|
|
printk(" DIPSW:%02x,%02x\n",
|
965 |
|
|
*rbtx4938_dipsw_ptr, *rbtx4938_bdipsw_ptr);
|
966 |
|
|
}
|
967 |
|
|
|
968 |
|
|
static int __init rbtx4938_ne_init(void)
|
969 |
|
|
{
|
970 |
|
|
struct resource res[] = {
|
971 |
|
|
{
|
972 |
|
|
.start = RBTX4938_RTL_8019_BASE,
|
973 |
|
|
.end = RBTX4938_RTL_8019_BASE + 0x20 - 1,
|
974 |
|
|
.flags = IORESOURCE_IO,
|
975 |
|
|
}, {
|
976 |
|
|
.start = RBTX4938_RTL_8019_IRQ,
|
977 |
|
|
.flags = IORESOURCE_IRQ,
|
978 |
|
|
}
|
979 |
|
|
};
|
980 |
|
|
struct platform_device *dev =
|
981 |
|
|
platform_device_register_simple("ne", -1,
|
982 |
|
|
res, ARRAY_SIZE(res));
|
983 |
|
|
return IS_ERR(dev) ? PTR_ERR(dev) : 0;
|
984 |
|
|
}
|
985 |
|
|
device_initcall(rbtx4938_ne_init);
|
986 |
|
|
|
987 |
|
|
/* GPIO support */
|
988 |
|
|
|
989 |
|
|
static DEFINE_SPINLOCK(rbtx4938_spi_gpio_lock);
|
990 |
|
|
|
991 |
|
|
static void rbtx4938_spi_gpio_set(unsigned gpio, int value)
|
992 |
|
|
{
|
993 |
|
|
u8 val;
|
994 |
|
|
unsigned long flags;
|
995 |
|
|
gpio -= 16;
|
996 |
|
|
spin_lock_irqsave(&rbtx4938_spi_gpio_lock, flags);
|
997 |
|
|
val = *rbtx4938_spics_ptr;
|
998 |
|
|
if (value)
|
999 |
|
|
val |= 1 << gpio;
|
1000 |
|
|
else
|
1001 |
|
|
val &= ~(1 << gpio);
|
1002 |
|
|
*rbtx4938_spics_ptr = val;
|
1003 |
|
|
mmiowb();
|
1004 |
|
|
spin_unlock_irqrestore(&rbtx4938_spi_gpio_lock, flags);
|
1005 |
|
|
}
|
1006 |
|
|
|
1007 |
|
|
static int rbtx4938_spi_gpio_dir_out(unsigned gpio, int value)
|
1008 |
|
|
{
|
1009 |
|
|
rbtx4938_spi_gpio_set(gpio, value);
|
1010 |
|
|
return 0;
|
1011 |
|
|
}
|
1012 |
|
|
|
1013 |
|
|
static DEFINE_SPINLOCK(tx4938_gpio_lock);
|
1014 |
|
|
|
1015 |
|
|
static int tx4938_gpio_get(unsigned gpio)
|
1016 |
|
|
{
|
1017 |
|
|
return tx4938_pioptr->din & (1 << gpio);
|
1018 |
|
|
}
|
1019 |
|
|
|
1020 |
|
|
static void tx4938_gpio_set_raw(unsigned gpio, int value)
|
1021 |
|
|
{
|
1022 |
|
|
u32 val;
|
1023 |
|
|
val = tx4938_pioptr->dout;
|
1024 |
|
|
if (value)
|
1025 |
|
|
val |= 1 << gpio;
|
1026 |
|
|
else
|
1027 |
|
|
val &= ~(1 << gpio);
|
1028 |
|
|
tx4938_pioptr->dout = val;
|
1029 |
|
|
}
|
1030 |
|
|
|
1031 |
|
|
static void tx4938_gpio_set(unsigned gpio, int value)
|
1032 |
|
|
{
|
1033 |
|
|
unsigned long flags;
|
1034 |
|
|
spin_lock_irqsave(&tx4938_gpio_lock, flags);
|
1035 |
|
|
tx4938_gpio_set_raw(gpio, value);
|
1036 |
|
|
mmiowb();
|
1037 |
|
|
spin_unlock_irqrestore(&tx4938_gpio_lock, flags);
|
1038 |
|
|
}
|
1039 |
|
|
|
1040 |
|
|
static int tx4938_gpio_dir_in(unsigned gpio)
|
1041 |
|
|
{
|
1042 |
|
|
spin_lock_irq(&tx4938_gpio_lock);
|
1043 |
|
|
tx4938_pioptr->dir &= ~(1 << gpio);
|
1044 |
|
|
mmiowb();
|
1045 |
|
|
spin_unlock_irq(&tx4938_gpio_lock);
|
1046 |
|
|
return 0;
|
1047 |
|
|
}
|
1048 |
|
|
|
1049 |
|
|
static int tx4938_gpio_dir_out(unsigned int gpio, int value)
|
1050 |
|
|
{
|
1051 |
|
|
spin_lock_irq(&tx4938_gpio_lock);
|
1052 |
|
|
tx4938_gpio_set_raw(gpio, value);
|
1053 |
|
|
tx4938_pioptr->dir |= 1 << gpio;
|
1054 |
|
|
mmiowb();
|
1055 |
|
|
spin_unlock_irq(&tx4938_gpio_lock);
|
1056 |
|
|
return 0;
|
1057 |
|
|
}
|
1058 |
|
|
|
1059 |
|
|
int gpio_direction_input(unsigned gpio)
|
1060 |
|
|
{
|
1061 |
|
|
if (gpio < 16)
|
1062 |
|
|
return tx4938_gpio_dir_in(gpio);
|
1063 |
|
|
return -EINVAL;
|
1064 |
|
|
}
|
1065 |
|
|
|
1066 |
|
|
int gpio_direction_output(unsigned gpio, int value)
|
1067 |
|
|
{
|
1068 |
|
|
if (gpio < 16)
|
1069 |
|
|
return tx4938_gpio_dir_out(gpio, value);
|
1070 |
|
|
if (gpio < 16 + 3)
|
1071 |
|
|
return rbtx4938_spi_gpio_dir_out(gpio, value);
|
1072 |
|
|
return -EINVAL;
|
1073 |
|
|
}
|
1074 |
|
|
|
1075 |
|
|
int gpio_get_value(unsigned gpio)
|
1076 |
|
|
{
|
1077 |
|
|
if (gpio < 16)
|
1078 |
|
|
return tx4938_gpio_get(gpio);
|
1079 |
|
|
return 0;
|
1080 |
|
|
}
|
1081 |
|
|
|
1082 |
|
|
void gpio_set_value(unsigned gpio, int value)
|
1083 |
|
|
{
|
1084 |
|
|
if (gpio < 16)
|
1085 |
|
|
tx4938_gpio_set(gpio, value);
|
1086 |
|
|
else
|
1087 |
|
|
rbtx4938_spi_gpio_set(gpio, value);
|
1088 |
|
|
}
|
1089 |
|
|
|
1090 |
|
|
/* SPI support */
|
1091 |
|
|
|
1092 |
|
|
static void __init txx9_spi_init(unsigned long base, int irq)
|
1093 |
|
|
{
|
1094 |
|
|
struct resource res[] = {
|
1095 |
|
|
{
|
1096 |
|
|
.start = base,
|
1097 |
|
|
.end = base + 0x20 - 1,
|
1098 |
|
|
.flags = IORESOURCE_MEM,
|
1099 |
|
|
.parent = &tx4938_reg_resource,
|
1100 |
|
|
}, {
|
1101 |
|
|
.start = irq,
|
1102 |
|
|
.flags = IORESOURCE_IRQ,
|
1103 |
|
|
},
|
1104 |
|
|
};
|
1105 |
|
|
platform_device_register_simple("spi_txx9", 0,
|
1106 |
|
|
res, ARRAY_SIZE(res));
|
1107 |
|
|
}
|
1108 |
|
|
|
1109 |
|
|
static int __init rbtx4938_spi_init(void)
|
1110 |
|
|
{
|
1111 |
|
|
struct spi_board_info srtc_info = {
|
1112 |
|
|
.modalias = "rtc-rs5c348",
|
1113 |
|
|
.max_speed_hz = 1000000, /* 1.0Mbps @ Vdd 2.0V */
|
1114 |
|
|
.bus_num = 0,
|
1115 |
|
|
.chip_select = 16 + SRTC_CS,
|
1116 |
|
|
/* Mode 1 (High-Active, Shift-Then-Sample), High Avtive CS */
|
1117 |
|
|
.mode = SPI_MODE_1 | SPI_CS_HIGH,
|
1118 |
|
|
};
|
1119 |
|
|
spi_register_board_info(&srtc_info, 1);
|
1120 |
|
|
spi_eeprom_register(SEEPROM1_CS);
|
1121 |
|
|
spi_eeprom_register(16 + SEEPROM2_CS);
|
1122 |
|
|
spi_eeprom_register(16 + SEEPROM3_CS);
|
1123 |
|
|
txx9_spi_init(TX4938_SPI_REG & 0xfffffffffULL, RBTX4938_IRQ_IRC_SPI);
|
1124 |
|
|
return 0;
|
1125 |
|
|
}
|
1126 |
|
|
arch_initcall(rbtx4938_spi_init);
|
1127 |
|
|
|
1128 |
|
|
/* Minimum CLK support */
|
1129 |
|
|
|
1130 |
|
|
struct clk *clk_get(struct device *dev, const char *id)
|
1131 |
|
|
{
|
1132 |
|
|
if (!strcmp(id, "spi-baseclk"))
|
1133 |
|
|
return (struct clk *)(txx9_gbus_clock / 2 / 4);
|
1134 |
|
|
return ERR_PTR(-ENOENT);
|
1135 |
|
|
}
|
1136 |
|
|
EXPORT_SYMBOL(clk_get);
|
1137 |
|
|
|
1138 |
|
|
int clk_enable(struct clk *clk)
|
1139 |
|
|
{
|
1140 |
|
|
return 0;
|
1141 |
|
|
}
|
1142 |
|
|
EXPORT_SYMBOL(clk_enable);
|
1143 |
|
|
|
1144 |
|
|
void clk_disable(struct clk *clk)
|
1145 |
|
|
{
|
1146 |
|
|
}
|
1147 |
|
|
EXPORT_SYMBOL(clk_disable);
|
1148 |
|
|
|
1149 |
|
|
unsigned long clk_get_rate(struct clk *clk)
|
1150 |
|
|
{
|
1151 |
|
|
return (unsigned long)clk;
|
1152 |
|
|
}
|
1153 |
|
|
EXPORT_SYMBOL(clk_get_rate);
|
1154 |
|
|
|
1155 |
|
|
void clk_put(struct clk *clk)
|
1156 |
|
|
{
|
1157 |
|
|
}
|
1158 |
|
|
EXPORT_SYMBOL(clk_put);
|