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[/] [or1k_soc_on_altera_embedded_dev_kit/] [trunk/] [linux-2.6/] [linux-2.6.24/] [arch/] [or32/] [README.or32] - Blame information for rev 7

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Line No. Rev Author Line
1 7 xianfeng 
This is a port of Linux to OpenRISC 1000 family of microprocessors.
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Changes:
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18. 11. 2003    Matjaz Breskvar (phoenix@bsemi.com)
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        initial port of linux to OpenRISC/or32 architecture.
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        all the core stuff is implemented and seams usable.
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08. 12. 2003    Matjaz Breskvar (phoenix@bsemi.com)
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        complete change of TLB miss handling.
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        rewrite of exceptions handling.
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        fully functional sash-3.6 in default initrd.
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        a much improved version with changes all around.
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10. 04. 2004    Matjaz Breskvar (phoenix@bsemi.com)
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        alot of bugfixes all over.
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        ethernet support, functional http and telnet servers.
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        running many standard linux apps.
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26. 06. 2004    Matjaz Breskvar (phoenix@bsemi.com)
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        port to 2.6.x
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30. 11. 2004    Matjaz Breskvar (phoenix@bsemi.com)
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        lots of bugfixes and enhancments.
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        added opencores framebuffer driver.

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