OpenCores
URL https://opencores.org/ocsvn/or1k_soc_on_altera_embedded_dev_kit/or1k_soc_on_altera_embedded_dev_kit/trunk

Subversion Repositories or1k_soc_on_altera_embedded_dev_kit

[/] [or1k_soc_on_altera_embedded_dev_kit/] [trunk/] [linux-2.6/] [linux-2.6.24/] [arch/] [or32/] [kernel/] [idle.c] - Blame information for rev 7

Details | Compare with Previous | View Log

Line No. Rev Author Line
1 7 xianfeng
/*
2
 *  linux/arch/or32/kernel/idle.c
3
 *
4
 *  or32 version
5
 *    author(s): Matjaz Breskvar (phoenix@bsemi.com)
6
 *
7
 *  derived from cris, i386, m68k, ppc, sh ports.
8
 *
9
 *  changes:
10
 *  18. 11. 2003: Matjaz Breskvar (phoenix@bsemi.com)
11
 *    initial port to or32 architecture
12
 *
13
 * Idle daemon for or32.  Idle daemon will handle any action
14
 * that needs to be taken when the system becomes idle.
15
 *
16
 * Based on:
17
 * arch/ppc/kernel/idle.c
18
 * Written by Cort Dougan (cort@cs.nmt.edu)
19
 *
20
 * This program is free software; you can redistribute it and/or
21
 * modify it under the terms of the GNU General Public License
22
 * as published by the Free Software Foundation; either version
23
 * 2 of the License, or (at your option) any later version.
24
 */
25
 
26
#include <linux/errno.h>
27
#include <linux/sched.h>
28
#include <linux/kernel.h>
29
#include <linux/mm.h>
30
#include <linux/smp.h>
31
#include <linux/smp_lock.h>
32
#include <linux/stddef.h>
33
#include <linux/unistd.h>
34
#include <linux/ptrace.h>
35
#include <linux/slab.h>
36
 
37
#include <asm/pgtable.h>
38
#include <asm/uaccess.h>
39
#include <asm/system.h>
40
#include <asm/io.h>
41
#include <asm/processor.h>
42
#include <asm/mmu.h>
43
#include <asm/cache.h>
44
 
45
void (*powersave)(void) = NULL;
46
 
47
void cpu_idle(void)
48
{
49
        int spr_sr;
50
 
51
        for (;;) {
52
 
53
// __PHX__ TODO: make an config option or something
54
#if 1
55
                if (!(SPR_SR_TEE & (spr_sr = mfspr(SPR_SR)))) {
56
                        printk("idled: tick timer disabled, enabling...\n");
57
                        printk("idled: SR 0x%lx, ESR 0x%lx, EPCR 0x%lx, EEAR 0x%lx\n",
58
                               mfspr(SPR_SR), mfspr(SPR_ESR_BASE),
59
                               mfspr(SPR_EPCR_BASE), mfspr(SPR_EEAR_BASE));
60
 
61
                        mtspr(SPR_SR, spr_sr | SPR_SR_TEE);
62
                        // __PHX__ TODO: add trace
63
                }
64
#endif
65
 
66
                if (!need_resched()) {
67
                        if (powersave != NULL) {
68
                                powersave();
69
                        }
70
                }
71
#if 0
72
                if (need_resched())
73
                        schedule();
74
 
75
#else
76
        schedule();
77
#endif
78
 
79
        }
80
}

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.