OpenCores
URL https://opencores.org/ocsvn/or1k_soc_on_altera_embedded_dev_kit/or1k_soc_on_altera_embedded_dev_kit/trunk

Subversion Repositories or1k_soc_on_altera_embedded_dev_kit

[/] [or1k_soc_on_altera_embedded_dev_kit/] [trunk/] [linux-2.6/] [linux-2.6.24/] [arch/] [or32/] [kernel/] [or32_funcs.S] - Blame information for rev 7

Details | Compare with Previous | View Log

Line No. Rev Author Line
1 7 xianfeng 
/*
2 
 *  linux/arch/or32/kernel/or32_funcs.S
3 
 *
4 
 *  or32 version
5 
 *    author(s): Matjaz Breskvar (phoenix@bsemi.com)
6 
 *
7 
 *  some helper functions for or32 assembler programming
8 
 *
9 
 */
10 
 
11 
#ifndef ENTRY
12 
#  define ENTRY(symbol)                 \
13 
          .global symbol                ;\
14 
   symbol:
15 
#endif
16 
 
17 
#define CLEAR_GPR(gpr)                  \
18 
    l.or    gpr,r0,r0
19 
 
20 
#define LOAD_SYMBOL_2_GPR(gpr,symbol)   \
21 
    l.movhi gpr,hi(symbol)              ;\
22 
    l.ori   gpr,gpr,lo(symbol)
23 
 
24 
/*
25 
 * DSCR: lower bits of SPR_SR defined by mask will be set to 1
26 
 *
27 
 * PRMS: t1 is temporary (and destroyed)
28 
 */
29 
#define SR_ENABLE_LO_BITS(mask,t1)      \
30 
    l.mfspr t1,r0,SPR_SR                ;\
31 
    l.ori   t1,t1,lo(mask)              ;\
32 
    l.mtspr r0,t1,SPR_SR
33 
 
34 
/*
35 
 * DSCR: bits set in mask will be set to 1
36 
 *
37 
 * PRMS: t1 is temporary register
38 
 *       t2 is temporary register
39 
 */
40 
#define SR_ENABLE_BITS(mask,t1,t2)      \
41 
    l.mfspr t2,r0,SPR_SR                ;\
42 
    LOAD_SYMBOL_2_GPR(t1,mask)          ;\
43 
    l.or    t2,t2,t1                    ;\
44 
    l.mtspr r0,t2,SPR_SR
45 
 
46 
/*
47 
 * DSCR: bits set in mask will be set to 0
48 
 *
49 
 * PRMS: t1 is temporary register
50 
 *       t2 is temporary register
51 
 */
52 
#define SR_DISABLE_BITS(mask,t1,t2)     \
53 
    l.mfspr t2,r0,SPR_SR                ;\
54 
    LOAD_SYMBOL_2_GPR(t1,(~mask))       ;\
55 
    l.and   t2,t2,t1                    ;\
56 
    l.mtspr r0,t2,SPR_SR
57 
 
58 
 
59 
/*
60 
 * DSCR: lower bits of SPR defined by mask will be set to 1
61 
 *
62 
 * PRMS: t1 is temporary (and destroyed)
63 
 */
64 
#define SPR_ENABLE_LO_BITS(SPR,mask,t1) \
65 
    l.mfspr t1,r0,SPR                   ;\
66 
    l.ori  t1,t1,lo(mask)               ;\
67 
    l.mtspr r0,t1,SPR
68 
 
69 
/*
70 
 * DSCR: lower bits of SPR defined by mask will be set to 0
71 
 *
72 
 * PRMS: t1 is temporary (and destroyed)
73 
 */
74 
#define SPR_DISABLE_LO_BITS(SPR,mask,t1) \
75 
    l.mfspr t1,r0,SPR                   ;\
76 
    l.andi  t1,t1,lo(~mask)             ;\
77 
    l.mtspr r0,t1,SPR
78 
 
79 
 
80 
#define DISABLE_INTERRUPTS(t1,t2)       \
81 
    SR_DISABLE_BITS((SPR_SR_IEE|SPR_SR_TEE),t1,t2)
82 
 
83 
#define ENABLE_INTERRUPTS(t1)           \
84 
    SR_ENABLE_LO_BITS((SPR_SR_IEE|SPR_SR_TEE),t1)
85 
 

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.