OpenCores
URL https://opencores.org/ocsvn/or1k_soc_on_altera_embedded_dev_kit/or1k_soc_on_altera_embedded_dev_kit/trunk

Subversion Repositories or1k_soc_on_altera_embedded_dev_kit

[/] [or1k_soc_on_altera_embedded_dev_kit/] [trunk/] [linux-2.6/] [linux-2.6.24/] [arch/] [or32/] [kernel/] [setup.c] - Blame information for rev 9

Details | Compare with Previous | View Log

Line No. Rev Author Line
1 7 xianfeng
/*
2
 *  linux/arch/or32/kernel/setup.c
3
 *
4
 *  or32 version
5
 *    author(s): Matjaz Breskvar (phoenix@bsemi.com)
6
 *
7
 *  derived from cris, i386, m68k, ppc, sh ports.
8
 *
9
 *  changes:
10
 *  18. 11. 2003: Matjaz Breskvar (phoenix@bsemi.com)
11
 *    initial port to or32 architecture
12
 *
13
 */
14
 
15
/*
16
 * This file handles the architecture-dependent parts of initialization
17
 */
18
 
19
#include <linux/errno.h>
20
#include <linux/sched.h>
21
#include <linux/kernel.h>
22
#include <linux/mm.h>
23
#include <linux/stddef.h>
24
#include <linux/unistd.h>
25
#include <linux/ptrace.h>
26
#include <linux/slab.h>
27
#include <linux/user.h>
28
#include <linux/a.out.h>
29
#include <linux/tty.h>
30
#include <linux/ioport.h>
31
#include <linux/delay.h>
32
#include <linux/console.h>
33
#include <linux/init.h>
34
#include <linux/bootmem.h>
35
#include <linux/seq_file.h>
36
#include <linux/serial.h>
37
 
38
#include <asm/board.h>
39
#include <asm/segment.h>
40
#include <asm/system.h>
41
#include <asm/smp.h>
42
#include <asm/pgtable.h>
43
#include <asm/types.h>
44
#include <asm/setup.h>
45
#include <asm/io.h>
46
 
47
/*
48
 * Debugging stuff
49
 */
50
 
51
int __phx_mmu__ = 0;
52
int __phx_warn__ = 0;
53
int __phx_debug__ = 0;
54
int __phx_signal__ = 0;
55
 
56
/*
57
 * Setup options
58
 */
59
 
60
extern int root_mountflags;
61
extern char _stext, _etext, _edata, _end;
62
extern int __init setup_early_serial8250_console(char *cmdline);
63
#ifdef CONFIG_BLK_DEV_INITRD
64
extern unsigned long initrd_start, initrd_end;
65
extern char __initrd_start, __initrd_end;
66
extern char __initramfs_start, __initramfs_end;
67
#endif
68
 
69
#include <asm/machdep.h>
70
 
71
extern void config_BSP(char *command, int len);
72
 
73
void (*mach_tick)(void) = NULL;
74
int (*mach_set_clock_mmss) (unsigned long) = NULL;
75
void (*mach_sched_init) (void) = NULL;
76
unsigned long (*mach_gettimeoffset)(void) = NULL;
77
void (*mach_gettod)(int *year, int *mon, int *day, int *hour, int *min, int *sec) = NULL;
78
int (*mach_hwclk)(int, struct hwclk_time*) = NULL;
79
void (*mach_mksound)( unsigned int count, unsigned int ticks) = NULL;
80
void (*mach_reset)( void ) = NULL;
81
void (*mach_debug_init)(void) = NULL;
82
 
83
 
84
unsigned long fb_mem_start;
85 9 xianfeng
static char command_line[COMMAND_LINE_SIZE] = "root=/dev/ram console=uart,mmio,0x30000000";
86 7 xianfeng
/*static char command_line[COMMAND_LINE_SIZE] = "root=/dev/ram console=ttyS0";*/
87
extern const unsigned long text_start, edata; /* set by the linker script */
88
 
89
static unsigned long __init setup_memory(void)
90
{
91
        unsigned long bootmap_size, start_pfn, max_low_pfn;
92
 
93
 
94
#define PFN_UP(x)       (((x) + PAGE_SIZE-1) >> PAGE_SHIFT)
95
#define PFN_DOWN(x)     ((x) >> PAGE_SHIFT)
96
#define PFN_PHYS(x)     ((x) << PAGE_SHIFT)
97
 
98
#ifndef CONFIG_FB_OC_SHMEM_SIZE
99
#define CONFIG_FB_OC_SHMEM_SIZE 0
100
#endif /* CONFIG_FB_OC_SHMEM_SIZE */
101
 
102
 
103
        /* min_low_pfn points to the start of DRAM, start_pfn points
104
         * to the first DRAM pages after the kernel, and max_low_pfn
105
         * to the end of DRAM. Partial pages are not useful, so round it
106
         * down.
107
         */
108
        start_pfn   = PFN_UP(__pa(&_end));
109
        max_low_pfn = PFN_DOWN(CONFIG_OR32_MEMORY_SIZE
110
                               -CONFIG_FB_OC_SHMEM_SIZE
111
                               -CONFIG_OR32_RESERVED_MEM_SIZE);
112
        min_low_pfn = PAGE_OFFSET >> PAGE_SHIFT;
113
 
114
#undef CONFIG_FB_OC_SHMEM_SIZE
115
 
116
        /*
117
         * set the beginning of frame buffer
118
         */
119
        fb_mem_start = PFN_PHYS(max_low_pfn);
120
 
121
        /*
122
         * initialize the boot-time allocator (with low memory only)
123
         */
124
        bootmap_size = init_bootmem(start_pfn, max_low_pfn);
125
        free_bootmem(PFN_PHYS(start_pfn), PFN_PHYS(max_low_pfn - start_pfn));
126
        reserve_bootmem(PFN_PHYS(start_pfn), bootmap_size);
127
 
128
        return(max_low_pfn);
129
}
130
 
131
static inline unsigned long extract_value_bits(unsigned long reg,
132
                                               short bit_nr, short width)
133
{
134
        return((reg >> bit_nr) & (0 << width));
135
}
136
 
137
static inline unsigned long extract_value(unsigned long reg,
138
                                          unsigned long mask)
139
{
140
        while (!(mask & 0x1)) {
141
                reg  = reg  >> 1;
142
                mask = mask >> 1;
143
        }
144
        return(mask & reg);
145
}
146
 
147
void __init detect_timer(void)
148
{
149
        unsigned long cfg;
150
 
151
        cfg = mfspr(SPR_TTMR);
152
        printk("period 0x%x\n", SPR_TTMR & SPR_TTMR_PERIOD);
153
}
154
 
155
void __init detect_unit_config(unsigned long upr, unsigned long mask,
156
                               char *text, void (*func)(void))
157
{
158
        if (text != NULL)
159
                printk("%s", text);
160
 
161
        if ( upr & mask ) {
162
                if (func != NULL)
163
                        func();
164
                else
165
                        printk("present\n");
166
        }
167
        else
168
                printk("N/A\n");
169
}
170
 
171
 
172
void __init detect_soc_generic(unsigned long upr)
173
{
174
        detect_unit_config(upr, SPR_UPR_DCP,  "  dCACHE: ", NULL);
175
        detect_unit_config(upr, SPR_UPR_ICP,  "  iCACHE: ", NULL);
176
        detect_unit_config(upr, SPR_UPR_DMP,  "  dMMU\t: ", NULL);
177
        detect_unit_config(upr, SPR_UPR_IMP,  "  iMMU\t: ", NULL);
178
        detect_unit_config(upr, SPR_UPR_DUP,  "  debug : ", NULL);
179
        detect_unit_config(upr, SPR_UPR_PCUP, "  PerfC : ", NULL);
180
        detect_unit_config(upr, SPR_UPR_PMP,  "  PM    : ", NULL);
181
        detect_unit_config(upr, SPR_UPR_PICP, "  PIC   : ", NULL);
182
        detect_unit_config(upr, SPR_UPR_TTP,  "  TIMER : ", detect_timer);
183
        detect_unit_config(upr, SPR_UPR_CUST, "  CUs   : ", NULL);
184
 
185
/* add amount configured memory
186
 */
187
}
188
 
189
void __init detect_soc_rev_0(unsigned long upr)
190
{
191
 
192
        printk("  WARNING, using default values !\n"
193
               "           (some early revision 0 processors don't have unit present register\n"
194
               "            populated with all avaliable units)\n");
195
 
196
        printk("  dCACHE: assumed %4d Kb size, %2d bytes/line, %d way(s)",
197
               CONFIG_OR32_DC_SIZE, CONFIG_OR32_DC_LINE, 1);
198
        detect_unit_config(upr, SPR_UPR_DCP,  ", detected: ", NULL);
199
 
200
        printk("  iCACHE: assumed %4d Kb size, %2d bytes/line, %d way(s)",
201
               CONFIG_OR32_IC_SIZE, CONFIG_OR32_IC_LINE, 1);
202
        detect_unit_config(upr, SPR_UPR_ICP,  ", detected: ", NULL);
203
 
204
        printk("  dMMU\t: assumed %4d entries, %d way(s)",
205
               CONFIG_OR32_DTLB_ENTRIES, 1);
206
        detect_unit_config(upr, SPR_UPR_DMP,  ", detected: ", NULL);
207
 
208
        printk("  iMMU\t: assumed %4d entries, %d way(s)",
209
               CONFIG_OR32_ITLB_ENTRIES, 1);
210
        detect_unit_config(upr, SPR_UPR_IMP,  ", detected: ", NULL);
211
        detect_unit_config(upr, SPR_UPR_DUP,  "  debug : unknown (guess yes), detected: ", NULL);
212
        detect_unit_config(upr, SPR_UPR_PCUP, "  PerfC : unknown (guess no ), detected: ", NULL);
213
        detect_unit_config(upr, SPR_UPR_PMP,  "  PM    : unknown (guess yes), detected: ", NULL);
214
        detect_unit_config(upr, SPR_UPR_PICP, "  PIC   : unknown (guess yes), detected: ", NULL);
215
        detect_unit_config(upr, SPR_UPR_TTP,  "  TIMER : unknown (guess yes), detected: ", NULL);
216
        detect_unit_config(upr, SPR_UPR_CUST, "  CUs   : unknown (guess no ), detected: ", NULL);
217
 
218
/* add amount configured memory
219
 */
220
}
221
 
222
unsigned long su_asm(void);
223
 
224
void __init detect_soc(void)
225
{
226
        unsigned long upr, cfg, version, revision;
227
 
228
        upr = mfspr(SPR_UPR);
229
        if (upr &  SPR_UPR_UP)
230
                printk("Detecting Processor units:\n");
231
        else {
232
                printk("Unit Present Register not avaliable\n");
233
                return;
234
        }
235
 
236
        cfg = mfspr(SPR_VR);
237
        version=extract_value(cfg, SPR_VR_VER);
238
        revision=extract_value(cfg, SPR_VR_REV);
239
 
240
#ifndef CONFIG_OR32_ANONYMOUS
241
        printk("  CPU\t: or32/OpenRISC-%lx, revision %lx, @%d MHz, %s\n",
242
               version, revision,
243
               CONFIG_OR32_SYS_CLK,
244
               (upr & (unsigned long)SPR_UPR_SRP) ?
245
               "with shadow registers" : "with no shadow registers");
246
 
247
        if ((version == 0x1200) & (revision == 0)) {
248
                detect_soc_rev_0(upr);
249
        } else {
250
                detect_soc_generic(upr);
251
        }
252
#endif /* CONFIG_OR32_ANONYMOUS */
253
 
254
        printk("  Signed 0x%lx\n", su_asm());
255
}
256
 
257
 
258
void __init setup_arch(char **cmdline_p)
259
{
260
        unsigned long max_low_pfn;
261
 
262
        config_BSP(&command_line[0], COMMAND_LINE_SIZE);
263
 
264
        /* detect System on Chip parameters */
265
        detect_soc();
266
 
267
        /* process 1's initial memory region is the kernel code/data */
268
        init_mm.start_code = (unsigned long) &_stext;
269
        init_mm.end_code =   (unsigned long) &_etext;
270
        init_mm.end_data =   (unsigned long) &_edata;
271
        init_mm.brk =        (unsigned long) &_end;
272
 
273
#ifdef CONFIG_BLK_DEV_INITRD
274
        initrd_start = (unsigned long)&__initrd_start;
275
        initrd_end = (unsigned long)&__initrd_end;
276
#endif
277
 
278
        /* setup bootmem allocator */
279
        max_low_pfn = setup_memory();
280
 
281
        /* paging_init() sets up the MMU and marks all pages as reserved */
282
        paging_init();
283
 
284
#ifdef CONFIG_SERIAL_8250_CONSOLE
285
        //      early_serial_console_init(command_line); RGD
286
        setup_early_serial8250_console(command_line);
287
#endif
288
 
289
#if defined(CONFIG_VT) && defined(CONFIG_DUMMY_CONSOLE)
290
        if(!conswitchp)
291
                conswitchp = &dummy_con;
292
#endif
293
 
294
        *cmdline_p = command_line;
295
 
296
        /* Save command line copy for /proc/cmdline RGD removed 2.6.21*/
297
        //memcpy(saved_command_line, command_line, COMMAND_LINE_SIZE);
298
        //saved_command_line[COMMAND_LINE_SIZE-1] = '\0';
299
 
300
        /* fire up 8051 */
301
//      printk("Starting 8051...\n");
302
//      oc8051_init();
303
 
304 9 xianfeng
#ifdef CONFIG_OR32_ANONYMOUS
305 7 xianfeng
        printk("Linux/or32 port 2003-2005 OpenCores <phoenix@bsemi.com>\n");
306
#endif /* CONFIG_OR32_ANONYMOUS */
307
}
308
 
309
static int show_cpuinfo(struct seq_file *m, void *v)
310
{
311
 
312
#ifndef CONFIG_OR32_ANONYMOUS
313
        return seq_printf(m,
314
                          "cpu\t\t: or32\n"
315
                          "cpu revision\t: %lu\n"
316
                          "cpu model\t: %s\n"
317
                          "icache size\t: %d kB\n"
318
                          "dcache size\t: %d kB\n"
319
                          "immu\t\t: %s\n"
320
                          "dmmu\t\t: %s\n"
321
                          "fpu\t\t: %s\n"
322
                          "ethernet\t: %s Mbps\n"
323
                          "bogomips\t: %lu.%02lu\n",
324
 
325
                          0UL,
326
                          "Marvin",
327
                          8,
328
                          8,
329
                          "64 entries, 1 way",
330
                          "64 entries, 1 way",
331
                          "no",
332
                          "10/100",
333
                          (loops_per_jiffy * HZ) / 500000,
334
                          ((loops_per_jiffy * HZ) / 5000) % 100);
335
#else /* CONFIG_OR32_ANONYMOUS */
336
        return seq_printf(m,
337
                          "cpu revision\t: %lu\n"
338
                          "icache size\t: %d kB\n"
339
                          "dcache size\t: %d kB\n"
340
                          "immu\t\t: %s\n"
341
                          "dmmu\t\t: %s\n"
342
                          "ethernet\t: %s Mbps\n",
343
 
344
                          0UL,
345
                          8,
346
                          8,
347
                          "64 entries, 1 way",
348
                          "64 entries, 1 way",
349
                          "10/100");
350
#endif /* CONFIG_OR32_ANONYMOUS */
351
 
352
 
353
}
354
 
355
static void *c_start(struct seq_file *m, loff_t *pos)
356
{
357
        /* We only got one CPU... */
358
        return *pos < 1 ? (void *)1 : NULL;
359
}
360
 
361
static void *c_next(struct seq_file *m, void *v, loff_t *pos)
362
{
363
        ++*pos;
364
        return NULL;
365
}
366
 
367
static void c_stop(struct seq_file *m, void *v)
368
{
369
}
370
 
371
struct seq_operations cpuinfo_op = {
372
        start:  c_start,
373
        next:   c_next,
374
        stop:   c_stop,
375
        show:   show_cpuinfo,
376
};
377
 
378
void arch_gettod(int *year, int *mon, int *day, int *hour,
379
                                  int *min, int *sec)
380
{
381
 
382
        if (mach_gettod)
383
                mach_gettod(year, mon, day, hour, min, sec);
384
        else
385
                *year = *mon = *day = *hour = *min = *sec = 0;
386
}
387
 
388
/*RGD this awful hack is because our compiler does
389
 *support the "weak" attribute correctly at this time
390
 *once we do (support weak) this should be removed!!
391
 */
392
extern const void __start_notes(){}
393
extern const void __stop_notes(){}

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.