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[/] [or1k_soc_on_altera_embedded_dev_kit/] [trunk/] [linux-2.6/] [linux-2.6.24/] [arch/] [powerpc/] [boot/] [mv64x60_i2c.c] - Blame information for rev 3

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Line No. Rev Author Line
1 3 xianfeng
/*
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 * Bootloader version of the i2c driver for the MV64x60.
3
 *
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 * Author: Dale Farnsworth <dfarnsworth@mvista.com>
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 * Maintained by: Mark A. Greer <mgreer@mvista.com>
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 *
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 * 2003, 2007 (c) MontaVista, Software, Inc.  This file is licensed under
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 * the terms of the GNU General Public License version 2.  This program is
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 * licensed "as is" without any warranty of any kind, whether express or
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 * implied.
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 */
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13
#include <stdarg.h>
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#include <stddef.h>
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#include "types.h"
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#include "elf.h"
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#include "page.h"
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#include "string.h"
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#include "stdio.h"
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#include "io.h"
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#include "ops.h"
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#include "mv64x60.h"
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/* Register defines */
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#define MV64x60_I2C_REG_SLAVE_ADDR                      0x00
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#define MV64x60_I2C_REG_DATA                            0x04
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#define MV64x60_I2C_REG_CONTROL                         0x08
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#define MV64x60_I2C_REG_STATUS                          0x0c
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#define MV64x60_I2C_REG_BAUD                            0x0c
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#define MV64x60_I2C_REG_EXT_SLAVE_ADDR                  0x10
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#define MV64x60_I2C_REG_SOFT_RESET                      0x1c
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#define MV64x60_I2C_CONTROL_ACK                         0x04
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#define MV64x60_I2C_CONTROL_IFLG                        0x08
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#define MV64x60_I2C_CONTROL_STOP                        0x10
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#define MV64x60_I2C_CONTROL_START                       0x20
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#define MV64x60_I2C_CONTROL_TWSIEN                      0x40
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#define MV64x60_I2C_CONTROL_INTEN                       0x80
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#define MV64x60_I2C_STATUS_BUS_ERR                      0x00
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#define MV64x60_I2C_STATUS_MAST_START                   0x08
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#define MV64x60_I2C_STATUS_MAST_REPEAT_START            0x10
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#define MV64x60_I2C_STATUS_MAST_WR_ADDR_ACK             0x18
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#define MV64x60_I2C_STATUS_MAST_WR_ADDR_NO_ACK          0x20
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#define MV64x60_I2C_STATUS_MAST_WR_ACK                  0x28
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#define MV64x60_I2C_STATUS_MAST_WR_NO_ACK               0x30
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#define MV64x60_I2C_STATUS_MAST_LOST_ARB                0x38
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#define MV64x60_I2C_STATUS_MAST_RD_ADDR_ACK             0x40
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#define MV64x60_I2C_STATUS_MAST_RD_ADDR_NO_ACK          0x48
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#define MV64x60_I2C_STATUS_MAST_RD_DATA_ACK             0x50
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#define MV64x60_I2C_STATUS_MAST_RD_DATA_NO_ACK          0x58
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#define MV64x60_I2C_STATUS_MAST_WR_ADDR_2_ACK           0xd0
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#define MV64x60_I2C_STATUS_MAST_WR_ADDR_2_NO_ACK        0xd8
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#define MV64x60_I2C_STATUS_MAST_RD_ADDR_2_ACK           0xe0
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#define MV64x60_I2C_STATUS_MAST_RD_ADDR_2_NO_ACK        0xe8
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#define MV64x60_I2C_STATUS_NO_STATUS                    0xf8
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58
static u8 *ctlr_base;
59
 
60
static int mv64x60_i2c_wait_for_status(int wanted)
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{
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        int i;
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        int status;
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        for (i=0; i<1000; i++) {
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                udelay(10);
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                status = in_le32((u32 *)(ctlr_base + MV64x60_I2C_REG_STATUS))
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                        & 0xff;
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                if (status == wanted)
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                        return status;
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        }
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        return -status;
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}
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static int mv64x60_i2c_control(int control, int status)
76
{
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        out_le32((u32 *)(ctlr_base + MV64x60_I2C_REG_CONTROL), control & 0xff);
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        return mv64x60_i2c_wait_for_status(status);
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}
80
 
81
static int mv64x60_i2c_read_byte(int control, int status)
82
{
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        out_le32((u32 *)(ctlr_base + MV64x60_I2C_REG_CONTROL), control & 0xff);
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        if (mv64x60_i2c_wait_for_status(status) < 0)
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                return -1;
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        return in_le32((u32 *)(ctlr_base + MV64x60_I2C_REG_DATA)) & 0xff;
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}
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static int mv64x60_i2c_write_byte(int data, int control, int status)
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{
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        out_le32((u32 *)(ctlr_base + MV64x60_I2C_REG_DATA), data & 0xff);
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        out_le32((u32 *)(ctlr_base + MV64x60_I2C_REG_CONTROL), control & 0xff);
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        return mv64x60_i2c_wait_for_status(status);
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}
95
 
96
int mv64x60_i2c_read(u32 devaddr, u8 *buf, u32 offset, u32 offset_size,
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                 u32 count)
98
{
99
        int i;
100
        int data;
101
        int control;
102
        int status;
103
 
104
        if (ctlr_base == NULL)
105
                return -1;
106
 
107
        /* send reset */
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        out_le32((u32 *)(ctlr_base + MV64x60_I2C_REG_SOFT_RESET), 0);
109
        out_le32((u32 *)(ctlr_base + MV64x60_I2C_REG_SLAVE_ADDR), 0);
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        out_le32((u32 *)(ctlr_base + MV64x60_I2C_REG_EXT_SLAVE_ADDR), 0);
111
        out_le32((u32 *)(ctlr_base + MV64x60_I2C_REG_BAUD), (4 << 3) | 0x4);
112
 
113
        if (mv64x60_i2c_control(MV64x60_I2C_CONTROL_TWSIEN,
114
                                MV64x60_I2C_STATUS_NO_STATUS) < 0)
115
                return -1;
116
 
117
        /* send start */
118
        control = MV64x60_I2C_CONTROL_START | MV64x60_I2C_CONTROL_TWSIEN;
119
        status = MV64x60_I2C_STATUS_MAST_START;
120
        if (mv64x60_i2c_control(control, status) < 0)
121
                return -1;
122
 
123
        /* select device for writing */
124
        data = devaddr & ~0x1;
125
        control = MV64x60_I2C_CONTROL_TWSIEN;
126
        status = MV64x60_I2C_STATUS_MAST_WR_ADDR_ACK;
127
        if (mv64x60_i2c_write_byte(data, control, status) < 0)
128
                return -1;
129
 
130
        /* send offset of data */
131
        control = MV64x60_I2C_CONTROL_TWSIEN;
132
        status = MV64x60_I2C_STATUS_MAST_WR_ACK;
133
        if (offset_size > 1) {
134
                if (mv64x60_i2c_write_byte(offset >> 8, control, status) < 0)
135
                        return -1;
136
        }
137
        if (mv64x60_i2c_write_byte(offset, control, status) < 0)
138
                return -1;
139
 
140
        /* resend start */
141
        control = MV64x60_I2C_CONTROL_START | MV64x60_I2C_CONTROL_TWSIEN;
142
        status = MV64x60_I2C_STATUS_MAST_REPEAT_START;
143
        if (mv64x60_i2c_control(control, status) < 0)
144
                return -1;
145
 
146
        /* select device for reading */
147
        data = devaddr | 0x1;
148
        control = MV64x60_I2C_CONTROL_TWSIEN;
149
        status = MV64x60_I2C_STATUS_MAST_RD_ADDR_ACK;
150
        if (mv64x60_i2c_write_byte(data, control, status) < 0)
151
                return -1;
152
 
153
        /* read all but last byte of data */
154
        control = MV64x60_I2C_CONTROL_ACK | MV64x60_I2C_CONTROL_TWSIEN;
155
        status = MV64x60_I2C_STATUS_MAST_RD_DATA_ACK;
156
 
157
        for (i=1; i<count; i++) {
158
                data = mv64x60_i2c_read_byte(control, status);
159
                if (data < 0) {
160
                        printf("errors on iteration %d\n", i);
161
                        return -1;
162
                }
163
                *buf++ = data;
164
        }
165
 
166
        /* read last byte of data */
167
        control = MV64x60_I2C_CONTROL_TWSIEN;
168
        status = MV64x60_I2C_STATUS_MAST_RD_DATA_NO_ACK;
169
        data = mv64x60_i2c_read_byte(control, status);
170
        if (data < 0)
171
                return -1;
172
        *buf++ = data;
173
 
174
        /* send stop */
175
        control = MV64x60_I2C_CONTROL_STOP | MV64x60_I2C_CONTROL_TWSIEN;
176
        status = MV64x60_I2C_STATUS_NO_STATUS;
177
        if (mv64x60_i2c_control(control, status) < 0)
178
                return -1;
179
 
180
        return count;
181
}
182
 
183
int mv64x60_i2c_open(void)
184
{
185
        u32 v;
186
        void *devp;
187
 
188
        devp = finddevice("/mv64x60/i2c");
189
        if (devp == NULL)
190
                goto err_out;
191
        if (getprop(devp, "virtual-reg", &v, sizeof(v)) != sizeof(v))
192
                goto err_out;
193
 
194
        ctlr_base = (u8 *)v;
195
        return 0;
196
 
197
err_out:
198
        return -1;
199
}
200
 
201
void mv64x60_i2c_close(void)
202
{
203
        ctlr_base = NULL;
204
}

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