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[/] [or1k_soc_on_altera_embedded_dev_kit/] [trunk/] [linux-2.6/] [linux-2.6.24/] [arch/] [powerpc/] [boot/] [treeboot-walnut.c] - Blame information for rev 3

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Line No. Rev Author Line
1 3 xianfeng
/*
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 * Old U-boot compatibility for Walnut
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 *
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 * Author: Josh Boyer <jwboyer@linux.vnet.ibm.com>
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 *
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 * Copyright 2007 IBM Corporation
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 *   Based on cuboot-83xx.c, which is:
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 * Copyright (c) 2007 Freescale Semiconductor, Inc.
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 *
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 * This program is free software; you can redistribute it and/or modify it
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 * under the terms of the GNU General Public License version 2 as published
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 * by the Free Software Foundation.
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 */
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#include "ops.h"
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#include "stdio.h"
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#include "dcr.h"
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#include "4xx.h"
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#include "io.h"
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BSS_STACK(4096);
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void ibm405gp_fixup_clocks(unsigned int sysclk, unsigned int ser_clk)
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{
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        u32 pllmr = mfdcr(DCRN_CPC0_PLLMR);
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        u32 cpc0_cr0 = mfdcr(DCRN_405_CPC0_CR0);
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        u32 cpc0_cr1 = mfdcr(DCRN_405_CPC0_CR1);
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        u32 cpu, plb, opb, ebc, tb, uart0, uart1, m;
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        u32 fwdv, fbdv, cbdv, opdv, epdv, udiv;
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        fwdv = (8 - ((pllmr & 0xe0000000) >> 29));
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        fbdv = (pllmr & 0x1e000000) >> 25;
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        cbdv = ((pllmr & 0x00060000) >> 17) + 1;
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        opdv = ((pllmr & 0x00018000) >> 15) + 1;
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        epdv = ((pllmr & 0x00001800) >> 13) + 2;
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        udiv = ((cpc0_cr0 & 0x3e) >> 1) + 1;
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        m = fwdv * fbdv * cbdv;
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        cpu = sysclk * m / fwdv;
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        plb = cpu / cbdv;
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        opb = plb / opdv;
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        ebc = plb / epdv;
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        if (cpc0_cr0 & 0x80) {
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                /* uart0 uses the external clock */
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                uart0 = ser_clk;
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        } else {
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                uart0 = cpu / udiv;
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        }
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        if (cpc0_cr0 & 0x40) {
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                /* uart1 uses the external clock */
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                uart1 = ser_clk;
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        } else {
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                uart1 = cpu / udiv;
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        }
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        /* setup the timebase clock to tick at the cpu frequency */
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        cpc0_cr1 = cpc0_cr1 & ~0x00800000;
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        mtdcr(DCRN_405_CPC0_CR1, cpc0_cr1);
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        tb = cpu;
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        dt_fixup_cpu_clocks(cpu, tb, 0);
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        dt_fixup_clock("/plb", plb);
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        dt_fixup_clock("/plb/opb", opb);
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        dt_fixup_clock("/plb/ebc", ebc);
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        dt_fixup_clock("/plb/opb/serial@ef600300", uart0);
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        dt_fixup_clock("/plb/opb/serial@ef600400", uart1);
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}
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static void walnut_flashsel_fixup(void)
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{
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        void *devp, *sram;
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        u32 reg_flash[3] = {0x0, 0x0, 0x80000};
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        u32 reg_sram[3] = {0x0, 0x0, 0x80000};
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        u8 *fpga;
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        u8 fpga_brds1 = 0x0;
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        devp = finddevice("/plb/ebc/fpga");
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        if (!devp)
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                fatal("Couldn't locate FPGA node\n\r");
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        if (getprop(devp, "virtual-reg", &fpga, sizeof(fpga)) != sizeof(fpga))
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                fatal("no virtual-reg property\n\r");
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        fpga_brds1 = in_8(fpga);
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        devp = finddevice("/plb/ebc/flash");
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        if (!devp)
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                fatal("Couldn't locate flash node\n\r");
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        if (getprop(devp, "reg", reg_flash, sizeof(reg_flash)) != sizeof(reg_flash))
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                fatal("flash reg property has unexpected size\n\r");
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        sram = finddevice("/plb/ebc/sram");
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        if (!sram)
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                fatal("Couldn't locate sram node\n\r");
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        if (getprop(sram, "reg", reg_sram, sizeof(reg_sram)) != sizeof(reg_sram))
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                fatal("sram reg property has unexpected size\n\r");
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        if (fpga_brds1 & 0x1) {
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                reg_flash[1] ^= 0x80000;
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                reg_sram[1] ^= 0x80000;
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        }
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        setprop(devp, "reg", reg_flash, sizeof(reg_flash));
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        setprop(sram, "reg", reg_sram, sizeof(reg_sram));
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}
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#define WALNUT_OPENBIOS_MAC_OFF 0xfffffe0b
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static void walnut_fixups(void)
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{
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        ibm4xx_fixup_memsize();
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        ibm405gp_fixup_clocks(33330000, 0xa8c000);
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        ibm4xx_quiesce_eth((u32 *)0xef600800, NULL);
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        ibm4xx_fixup_ebc_ranges("/plb/ebc");
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        walnut_flashsel_fixup();
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        dt_fixup_mac_addresses((u8 *) WALNUT_OPENBIOS_MAC_OFF);
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}
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void platform_init(void)
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{
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        unsigned long end_of_ram = 0x2000000;
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        unsigned long avail_ram = end_of_ram - (unsigned long) _end;
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        simple_alloc_init(_end, avail_ram, 32, 32);
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        platform_ops.fixups = walnut_fixups;
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        platform_ops.exit = ibm40x_dbcr_reset;
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        ft_init(_dtb_start, _dtb_end - _dtb_start, 32);
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        serial_console_init();
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}

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