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URL https://opencores.org/ocsvn/or1k_soc_on_altera_embedded_dev_kit/or1k_soc_on_altera_embedded_dev_kit/trunk

Subversion Repositories or1k_soc_on_altera_embedded_dev_kit

[/] [or1k_soc_on_altera_embedded_dev_kit/] [trunk/] [linux-2.6/] [linux-2.6.24/] [arch/] [powerpc/] [sysdev/] [dcr-low.S] - Blame information for rev 3

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Line No. Rev Author Line
1 3 xianfeng
/*
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 * "Indirect" DCR access
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 *
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 * Copyright (c) 2004 Eugene Surovegin 
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 *
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 * This program is free software; you can redistribute it and/or modify it
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 * under  the terms of  the GNU General Public License as published by the
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 * Free Software Foundation;  either version 2 of the License, or (at your
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 * option) any later version.
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 */
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#include 
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#include 
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#define DCR_ACCESS_PROLOG(table) \
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        rlwinm  r3,r3,4,18,27;   \
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        lis     r5,table@h;      \
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        ori     r5,r5,table@l;   \
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        add     r3,r3,r5;        \
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        mtctr   r3;              \
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        bctr
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_GLOBAL(__mfdcr)
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        DCR_ACCESS_PROLOG(__mfdcr_table)
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_GLOBAL(__mtdcr)
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        DCR_ACCESS_PROLOG(__mtdcr_table)
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__mfdcr_table:
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        mfdcr  r3,0; blr
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__mtdcr_table:
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        mtdcr  0,r4; blr
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dcr     = 1
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        .rept   1023
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        mfdcr   r3,dcr; blr
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        mtdcr   dcr,r4; blr
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        dcr     = dcr + 1
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        .endr

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