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[/] [or1k_soc_on_altera_embedded_dev_kit/] [trunk/] [linux-2.6/] [linux-2.6.24/] [arch/] [powerpc/] [sysdev/] [qe_lib/] [ucc.c] - Blame information for rev 3

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Line No. Rev Author Line
1 3 xianfeng 
/*
2 
 * arch/powerpc/sysdev/qe_lib/ucc.c
3 
 *
4 
 * QE UCC API Set - UCC specific routines implementations.
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 *
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 * Copyright (C) 2006 Freescale Semicondutor, Inc. All rights reserved.
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 *
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 * Authors:     Shlomi Gridish <gridish@freescale.com>
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 *              Li Yang <leoli@freescale.com>
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 *
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 * This program is free software; you can redistribute  it and/or modify it
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 * under  the terms of  the GNU General  Public License as published by the
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 * Free Software Foundation;  either version 2 of the  License, or (at your
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 * option) any later version.
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 */
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#include <linux/kernel.h>
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#include <linux/init.h>
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#include <linux/errno.h>
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#include <linux/slab.h>
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#include <linux/stddef.h>
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#include <linux/module.h>
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#include <asm/irq.h>
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#include <asm/io.h>
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#include <asm/immap_qe.h>
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#include <asm/qe.h>
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#include <asm/ucc.h>
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static DEFINE_SPINLOCK(ucc_lock);
30 
 
31 
int ucc_set_qe_mux_mii_mng(unsigned int ucc_num)
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{
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        unsigned long flags;
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        if (ucc_num > UCC_MAX_NUM - 1)
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                return -EINVAL;
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        spin_lock_irqsave(&ucc_lock, flags);
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        clrsetbits_be32(&qe_immr->qmx.cmxgcr, QE_CMXGCR_MII_ENET_MNG,
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                ucc_num << QE_CMXGCR_MII_ENET_MNG_SHIFT);
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        spin_unlock_irqrestore(&ucc_lock, flags);
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        return 0;
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}
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EXPORT_SYMBOL(ucc_set_qe_mux_mii_mng);
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/* Configure the UCC to either Slow or Fast.
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 *
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 * A given UCC can be figured to support either "slow" devices (e.g. UART)
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 * or "fast" devices (e.g. Ethernet).
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 *
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 * 'ucc_num' is the UCC number, from 0 - 7.
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 *
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 * This function also sets the UCC_GUEMR_SET_RESERVED3 bit because that bit
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 * must always be set to 1.
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 */
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int ucc_set_type(unsigned int ucc_num, enum ucc_speed_type speed)
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{
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        u8 __iomem *guemr;
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        /* The GUEMR register is at the same location for both slow and fast
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           devices, so we just use uccX.slow.guemr. */
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        switch (ucc_num) {
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        case 0: guemr = &qe_immr->ucc1.slow.guemr;
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                break;
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        case 1: guemr = &qe_immr->ucc2.slow.guemr;
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                break;
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        case 2: guemr = &qe_immr->ucc3.slow.guemr;
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                break;
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        case 3: guemr = &qe_immr->ucc4.slow.guemr;
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                break;
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        case 4: guemr = &qe_immr->ucc5.slow.guemr;
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                break;
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        case 5: guemr = &qe_immr->ucc6.slow.guemr;
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                break;
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        case 6: guemr = &qe_immr->ucc7.slow.guemr;
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                break;
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        case 7: guemr = &qe_immr->ucc8.slow.guemr;
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                break;
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        default:
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                return -EINVAL;
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        }
83 
 
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        clrsetbits_8(guemr, UCC_GUEMR_MODE_MASK,
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                UCC_GUEMR_SET_RESERVED3 | speed);
86 
 
87 
        return 0;
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}
89 
 
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static void get_cmxucr_reg(unsigned int ucc_num, __be32 **cmxucr,
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        unsigned int *reg_num, unsigned int *shift)
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{
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        unsigned int cmx = ((ucc_num & 1) << 1) + (ucc_num > 3);
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        *reg_num = cmx + 1;
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        *cmxucr = &qe_immr->qmx.cmxucr[cmx];
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        *shift = 16 - 8 * (ucc_num & 2);
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}
99 
 
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int ucc_mux_set_grant_tsa_bkpt(unsigned int ucc_num, int set, u32 mask)
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{
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        __be32 *cmxucr;
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        unsigned int reg_num;
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        unsigned int shift;
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        /* check if the UCC number is in range. */
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        if (ucc_num > UCC_MAX_NUM - 1)
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                return -EINVAL;
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        get_cmxucr_reg(ucc_num, &cmxucr, &reg_num, &shift);
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        if (set)
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                setbits32(cmxucr, mask << shift);
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        else
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                clrbits32(cmxucr, mask << shift);
116 
 
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        return 0;
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}
119 
 
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int ucc_set_qe_mux_rxtx(unsigned int ucc_num, enum qe_clock clock,
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        enum comm_dir mode)
122 
{
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        __be32 *cmxucr;
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        unsigned int reg_num;
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        unsigned int shift;
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        u32 clock_bits = 0;
127 
 
128 
        /* check if the UCC number is in range. */
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        if (ucc_num > UCC_MAX_NUM - 1)
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                return -EINVAL;
131 
 
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        /* The communications direction must be RX or TX */
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        if (!((mode == COMM_DIR_RX) || (mode == COMM_DIR_TX)))
134 
                return -EINVAL;
135 
 
136 
        get_cmxucr_reg(ucc_num, &cmxucr, &reg_num, &shift);
137 
 
138 
        switch (reg_num) {
139 
        case 1:
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                switch (clock) {
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                case QE_BRG1:   clock_bits = 1; break;
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                case QE_BRG2:   clock_bits = 2; break;
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                case QE_BRG7:   clock_bits = 3; break;
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                case QE_BRG8:   clock_bits = 4; break;
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                case QE_CLK9:   clock_bits = 5; break;
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                case QE_CLK10:  clock_bits = 6; break;
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                case QE_CLK11:  clock_bits = 7; break;
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                case QE_CLK12:  clock_bits = 8; break;
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                case QE_CLK15:  clock_bits = 9; break;
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                case QE_CLK16:  clock_bits = 10; break;
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                default: break;
152 
                }
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                break;
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        case 2:
155 
                switch (clock) {
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                case QE_BRG5:   clock_bits = 1; break;
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                case QE_BRG6:   clock_bits = 2; break;
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                case QE_BRG7:   clock_bits = 3; break;
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                case QE_BRG8:   clock_bits = 4; break;
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                case QE_CLK13:  clock_bits = 5; break;
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                case QE_CLK14:  clock_bits = 6; break;
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                case QE_CLK19:  clock_bits = 7; break;
163 
                case QE_CLK20:  clock_bits = 8; break;
164 
                case QE_CLK15:  clock_bits = 9; break;
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                case QE_CLK16:  clock_bits = 10; break;
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                default: break;
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                }
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                break;
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        case 3:
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                switch (clock) {
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                case QE_BRG9:   clock_bits = 1; break;
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                case QE_BRG10:  clock_bits = 2; break;
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                case QE_BRG15:  clock_bits = 3; break;
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                case QE_BRG16:  clock_bits = 4; break;
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                case QE_CLK3:   clock_bits = 5; break;
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                case QE_CLK4:   clock_bits = 6; break;
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                case QE_CLK17:  clock_bits = 7; break;
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                case QE_CLK18:  clock_bits = 8; break;
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                case QE_CLK7:   clock_bits = 9; break;
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                case QE_CLK8:   clock_bits = 10; break;
181 
                case QE_CLK16:  clock_bits = 11; break;
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                default: break;
183 
                }
184 
                break;
185 
        case 4:
186 
                switch (clock) {
187 
                case QE_BRG13:  clock_bits = 1; break;
188 
                case QE_BRG14:  clock_bits = 2; break;
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                case QE_BRG15:  clock_bits = 3; break;
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                case QE_BRG16:  clock_bits = 4; break;
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                case QE_CLK5:   clock_bits = 5; break;
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                case QE_CLK6:   clock_bits = 6; break;
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                case QE_CLK21:  clock_bits = 7; break;
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                case QE_CLK22:  clock_bits = 8; break;
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                case QE_CLK7:   clock_bits = 9; break;
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                case QE_CLK8:   clock_bits = 10; break;
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                case QE_CLK16:  clock_bits = 11; break;
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                default: break;
199 
                }
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                break;
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        default: break;
202 
        }
203 
 
204 
        /* Check for invalid combination of clock and UCC number */
205 
        if (!clock_bits)
206 
                return -ENOENT;
207 
 
208 
        if (mode == COMM_DIR_RX)
209 
                shift += 4;
210 
 
211 
        clrsetbits_be32(cmxucr, QE_CMXUCR_TX_CLK_SRC_MASK << shift,
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                clock_bits << shift);
213 
 
214 
        return 0;
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}

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