OpenCores
URL https://opencores.org/ocsvn/or1k_soc_on_altera_embedded_dev_kit/or1k_soc_on_altera_embedded_dev_kit/trunk

Subversion Repositories or1k_soc_on_altera_embedded_dev_kit

[/] [or1k_soc_on_altera_embedded_dev_kit/] [trunk/] [linux-2.6/] [linux-2.6.24/] [arch/] [sh64/] [mm/] [tlb.c] - Blame information for rev 3

Details | Compare with Previous | View Log

Line No. Rev Author Line
1 3 xianfeng 
/*
2 
 * arch/sh64/mm/tlb.c
3 
 *
4 
 * Copyright (C) 2003  Paul Mundt <lethal@linux-sh.org>
5 
 * Copyright (C) 2003  Richard Curnow <richard.curnow@superh.com>
6 
 *
7 
 * This file is subject to the terms and conditions of the GNU General Public
8 
 * License.  See the file "COPYING" in the main directory of this archive
9 
 * for more details.
10 
 *
11 
 */
12 
#include <linux/mm.h>
13 
#include <linux/init.h>
14 
#include <asm/page.h>
15 
#include <asm/tlb.h>
16 
#include <asm/mmu_context.h>
17 
 
18 
/**
19 
 * sh64_tlb_init
20 
 *
21 
 * Perform initial setup for the DTLB and ITLB.
22 
 */
23 
int __init sh64_tlb_init(void)
24 
{
25 
        /* Assign some sane DTLB defaults */
26 
        cpu_data->dtlb.entries  = 64;
27 
        cpu_data->dtlb.step     = 0x10;
28 
 
29 
        cpu_data->dtlb.first    = DTLB_FIXED | cpu_data->dtlb.step;
30 
        cpu_data->dtlb.next     = cpu_data->dtlb.first;
31 
 
32 
        cpu_data->dtlb.last     = DTLB_FIXED |
33 
                                  ((cpu_data->dtlb.entries - 1) *
34 
                                   cpu_data->dtlb.step);
35 
 
36 
        /* And again for the ITLB */
37 
        cpu_data->itlb.entries  = 64;
38 
        cpu_data->itlb.step     = 0x10;
39 
 
40 
        cpu_data->itlb.first    = ITLB_FIXED | cpu_data->itlb.step;
41 
        cpu_data->itlb.next     = cpu_data->itlb.first;
42 
        cpu_data->itlb.last     = ITLB_FIXED |
43 
                                  ((cpu_data->itlb.entries - 1) *
44 
                                   cpu_data->itlb.step);
45 
 
46 
        return 0;
47 
}
48 
 
49 
/**
50 
 * sh64_next_free_dtlb_entry
51 
 *
52 
 * Find the next available DTLB entry
53 
 */
54 
unsigned long long sh64_next_free_dtlb_entry(void)
55 
{
56 
        return cpu_data->dtlb.next;
57 
}
58 
 
59 
/**
60 
 * sh64_get_wired_dtlb_entry
61 
 *
62 
 * Allocate a wired (locked-in) entry in the DTLB
63 
 */
64 
unsigned long long sh64_get_wired_dtlb_entry(void)
65 
{
66 
        unsigned long long entry = sh64_next_free_dtlb_entry();
67 
 
68 
        cpu_data->dtlb.first += cpu_data->dtlb.step;
69 
        cpu_data->dtlb.next  += cpu_data->dtlb.step;
70 
 
71 
        return entry;
72 
}
73 
 
74 
/**
75 
 * sh64_put_wired_dtlb_entry
76 
 *
77 
 * @entry:      Address of TLB slot.
78 
 *
79 
 * Free a wired (locked-in) entry in the DTLB.
80 
 *
81 
 * Works like a stack, last one to allocate must be first one to free.
82 
 */
83 
int sh64_put_wired_dtlb_entry(unsigned long long entry)
84 
{
85 
        __flush_tlb_slot(entry);
86 
 
87 
        /*
88 
         * We don't do any particularly useful tracking of wired entries,
89 
         * so this approach works like a stack .. last one to be allocated
90 
         * has to be the first one to be freed.
91 
         *
92 
         * We could potentially load wired entries into a list and work on
93 
         * rebalancing the list periodically (which also entails moving the
94 
         * contents of a TLB entry) .. though I have a feeling that this is
95 
         * more trouble than it's worth.
96 
         */
97 
 
98 
        /*
99 
         * Entry must be valid .. we don't want any ITLB addresses!
100 
         */
101 
        if (entry <= DTLB_FIXED)
102 
                return -EINVAL;
103 
 
104 
        /*
105 
         * Next, check if we're within range to be freed. (ie, must be the
106 
         * entry beneath the first 'free' entry!
107 
         */
108 
        if (entry < (cpu_data->dtlb.first - cpu_data->dtlb.step))
109 
                return -EINVAL;
110 
 
111 
        /* If we are, then bring this entry back into the list */
112 
        cpu_data->dtlb.first    -= cpu_data->dtlb.step;
113 
        cpu_data->dtlb.next     = entry;
114 
 
115 
        return 0;
116 
}
117 
 
118 
/**
119 
 * sh64_setup_tlb_slot
120 
 *
121 
 * @config_addr:        Address of TLB slot.
122 
 * @eaddr:              Virtual address.
123 
 * @asid:               Address Space Identifier.
124 
 * @paddr:              Physical address.
125 
 *
126 
 * Load up a virtual<->physical translation for @eaddr<->@paddr in the
127 
 * pre-allocated TLB slot @config_addr (see sh64_get_wired_dtlb_entry).
128 
 */
129 
inline void sh64_setup_tlb_slot(unsigned long long config_addr,
130 
                                unsigned long eaddr,
131 
                                unsigned long asid,
132 
                                unsigned long paddr)
133 
{
134 
        unsigned long long pteh, ptel;
135 
 
136 
        /* Sign extension */
137 
#if (NEFF == 32)
138 
        pteh = (unsigned long long)(signed long long)(signed long) eaddr;
139 
#else
140 
#error "Can't sign extend more than 32 bits yet"
141 
#endif
142 
        pteh &= PAGE_MASK;
143 
        pteh |= (asid << PTEH_ASID_SHIFT) | PTEH_VALID;
144 
#if (NEFF == 32)
145 
        ptel = (unsigned long long)(signed long long)(signed long) paddr;
146 
#else
147 
#error "Can't sign extend more than 32 bits yet"
148 
#endif
149 
        ptel &= PAGE_MASK;
150 
        ptel |= (_PAGE_CACHABLE | _PAGE_READ | _PAGE_WRITE);
151 
 
152 
        asm volatile("putcfg %0, 1, %1\n\t"
153 
                        "putcfg %0, 0, %2\n"
154 
                        : : "r" (config_addr), "r" (ptel), "r" (pteh));
155 
}
156 
 
157 
/**
158 
 * sh64_teardown_tlb_slot
159 
 *
160 
 * @config_addr:        Address of TLB slot.
161 
 *
162 
 * Teardown any existing mapping in the TLB slot @config_addr.
163 
 */
164 
inline void sh64_teardown_tlb_slot(unsigned long long config_addr)
165 
        __attribute__ ((alias("__flush_tlb_slot")));
166 
 

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.