1 |
3 |
xianfeng |
/* sun4m_irq.c
|
2 |
|
|
* arch/sparc/kernel/sun4m_irq.c:
|
3 |
|
|
*
|
4 |
|
|
* djhr: Hacked out of irq.c into a CPU dependent version.
|
5 |
|
|
*
|
6 |
|
|
* Copyright (C) 1995 David S. Miller (davem@caip.rutgers.edu)
|
7 |
|
|
* Copyright (C) 1995 Miguel de Icaza (miguel@nuclecu.unam.mx)
|
8 |
|
|
* Copyright (C) 1995 Pete A. Zaitcev (zaitcev@yahoo.com)
|
9 |
|
|
* Copyright (C) 1996 Dave Redman (djhr@tadpole.co.uk)
|
10 |
|
|
*/
|
11 |
|
|
|
12 |
|
|
#include <linux/errno.h>
|
13 |
|
|
#include <linux/linkage.h>
|
14 |
|
|
#include <linux/kernel_stat.h>
|
15 |
|
|
#include <linux/signal.h>
|
16 |
|
|
#include <linux/sched.h>
|
17 |
|
|
#include <linux/ptrace.h>
|
18 |
|
|
#include <linux/smp.h>
|
19 |
|
|
#include <linux/interrupt.h>
|
20 |
|
|
#include <linux/slab.h>
|
21 |
|
|
#include <linux/init.h>
|
22 |
|
|
#include <linux/ioport.h>
|
23 |
|
|
|
24 |
|
|
#include <asm/ptrace.h>
|
25 |
|
|
#include <asm/processor.h>
|
26 |
|
|
#include <asm/system.h>
|
27 |
|
|
#include <asm/psr.h>
|
28 |
|
|
#include <asm/vaddrs.h>
|
29 |
|
|
#include <asm/timer.h>
|
30 |
|
|
#include <asm/openprom.h>
|
31 |
|
|
#include <asm/oplib.h>
|
32 |
|
|
#include <asm/traps.h>
|
33 |
|
|
#include <asm/pgalloc.h>
|
34 |
|
|
#include <asm/pgtable.h>
|
35 |
|
|
#include <asm/smp.h>
|
36 |
|
|
#include <asm/irq.h>
|
37 |
|
|
#include <asm/io.h>
|
38 |
|
|
#include <asm/sbus.h>
|
39 |
|
|
#include <asm/cacheflush.h>
|
40 |
|
|
|
41 |
|
|
#include "irq.h"
|
42 |
|
|
|
43 |
|
|
/* On the sun4m, just like the timers, we have both per-cpu and master
|
44 |
|
|
* interrupt registers.
|
45 |
|
|
*/
|
46 |
|
|
|
47 |
|
|
/* These registers are used for sending/receiving irqs from/to
|
48 |
|
|
* different cpu's.
|
49 |
|
|
*/
|
50 |
|
|
struct sun4m_intreg_percpu {
|
51 |
|
|
unsigned int tbt; /* Interrupts still pending for this cpu. */
|
52 |
|
|
|
53 |
|
|
/* These next two registers are WRITE-ONLY and are only
|
54 |
|
|
* "on bit" sensitive, "off bits" written have NO affect.
|
55 |
|
|
*/
|
56 |
|
|
unsigned int clear; /* Clear this cpus irqs here. */
|
57 |
|
|
unsigned int set; /* Set this cpus irqs here. */
|
58 |
|
|
unsigned char space[PAGE_SIZE - 12];
|
59 |
|
|
};
|
60 |
|
|
|
61 |
|
|
/*
|
62 |
|
|
* djhr
|
63 |
|
|
* Actually the clear and set fields in this struct are misleading..
|
64 |
|
|
* according to the SLAVIO manual (and the same applies for the SEC)
|
65 |
|
|
* the clear field clears bits in the mask which will ENABLE that IRQ
|
66 |
|
|
* the set field sets bits in the mask to DISABLE the IRQ.
|
67 |
|
|
*
|
68 |
|
|
* Also the undirected_xx address in the SLAVIO is defined as
|
69 |
|
|
* RESERVED and write only..
|
70 |
|
|
*
|
71 |
|
|
* DAVEM_NOTE: The SLAVIO only specifies behavior on uniprocessor
|
72 |
|
|
* sun4m machines, for MP the layout makes more sense.
|
73 |
|
|
*/
|
74 |
|
|
struct sun4m_intregs {
|
75 |
|
|
struct sun4m_intreg_percpu cpu_intregs[SUN4M_NCPUS];
|
76 |
|
|
unsigned int tbt; /* IRQ's that are still pending. */
|
77 |
|
|
unsigned int irqs; /* Master IRQ bits. */
|
78 |
|
|
|
79 |
|
|
/* Again, like the above, two these registers are WRITE-ONLY. */
|
80 |
|
|
unsigned int clear; /* Clear master IRQ's by setting bits here. */
|
81 |
|
|
unsigned int set; /* Set master IRQ's by setting bits here. */
|
82 |
|
|
|
83 |
|
|
/* This register is both READ and WRITE. */
|
84 |
|
|
unsigned int undirected_target; /* Which cpu gets undirected irqs. */
|
85 |
|
|
};
|
86 |
|
|
|
87 |
|
|
static unsigned long dummy;
|
88 |
|
|
|
89 |
|
|
struct sun4m_intregs *sun4m_interrupts;
|
90 |
|
|
unsigned long *irq_rcvreg = &dummy;
|
91 |
|
|
|
92 |
|
|
/* Dave Redman (djhr@tadpole.co.uk)
|
93 |
|
|
* The sun4m interrupt registers.
|
94 |
|
|
*/
|
95 |
|
|
#define SUN4M_INT_ENABLE 0x80000000
|
96 |
|
|
#define SUN4M_INT_E14 0x00000080
|
97 |
|
|
#define SUN4M_INT_E10 0x00080000
|
98 |
|
|
|
99 |
|
|
#define SUN4M_HARD_INT(x) (0x000000001 << (x))
|
100 |
|
|
#define SUN4M_SOFT_INT(x) (0x000010000 << (x))
|
101 |
|
|
|
102 |
|
|
#define SUN4M_INT_MASKALL 0x80000000 /* mask all interrupts */
|
103 |
|
|
#define SUN4M_INT_MODULE_ERR 0x40000000 /* module error */
|
104 |
|
|
#define SUN4M_INT_M2S_WRITE 0x20000000 /* write buffer error */
|
105 |
|
|
#define SUN4M_INT_ECC 0x10000000 /* ecc memory error */
|
106 |
|
|
#define SUN4M_INT_FLOPPY 0x00400000 /* floppy disk */
|
107 |
|
|
#define SUN4M_INT_MODULE 0x00200000 /* module interrupt */
|
108 |
|
|
#define SUN4M_INT_VIDEO 0x00100000 /* onboard video */
|
109 |
|
|
#define SUN4M_INT_REALTIME 0x00080000 /* system timer */
|
110 |
|
|
#define SUN4M_INT_SCSI 0x00040000 /* onboard scsi */
|
111 |
|
|
#define SUN4M_INT_AUDIO 0x00020000 /* audio/isdn */
|
112 |
|
|
#define SUN4M_INT_ETHERNET 0x00010000 /* onboard ethernet */
|
113 |
|
|
#define SUN4M_INT_SERIAL 0x00008000 /* serial ports */
|
114 |
|
|
#define SUN4M_INT_KBDMS 0x00004000 /* keyboard/mouse */
|
115 |
|
|
#define SUN4M_INT_SBUSBITS 0x00003F80 /* sbus int bits */
|
116 |
|
|
|
117 |
|
|
#define SUN4M_INT_SBUS(x) (1 << (x+7))
|
118 |
|
|
#define SUN4M_INT_VME(x) (1 << (x))
|
119 |
|
|
|
120 |
|
|
/* These tables only apply for interrupts greater than 15..
|
121 |
|
|
*
|
122 |
|
|
* any intr value below 0x10 is considered to be a soft-int
|
123 |
|
|
* this may be useful or it may not.. but that's how I've done it.
|
124 |
|
|
* and it won't clash with what OBP is telling us about devices.
|
125 |
|
|
*
|
126 |
|
|
* take an encoded intr value and lookup if it's valid
|
127 |
|
|
* then get the mask bits that match from irq_mask
|
128 |
|
|
*
|
129 |
|
|
* P3: Translation from irq 0x0d to mask 0x2000 is for MrCoffee.
|
130 |
|
|
*/
|
131 |
|
|
static unsigned char irq_xlate[32] = {
|
132 |
|
|
/* 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, a, b, c, d, e, f */
|
133 |
|
|
0, 0, 0, 0, 1, 0, 2, 0, 3, 0, 4, 5, 6, 14, 0, 7,
|
134 |
|
|
0, 0, 8, 9, 0, 10, 0, 11, 0, 12, 0, 13, 0, 14, 0, 0
|
135 |
|
|
};
|
136 |
|
|
|
137 |
|
|
static unsigned long irq_mask[] = {
|
138 |
|
|
0, /* illegal index */
|
139 |
|
|
SUN4M_INT_SCSI, /* 1 irq 4 */
|
140 |
|
|
SUN4M_INT_ETHERNET, /* 2 irq 6 */
|
141 |
|
|
SUN4M_INT_VIDEO, /* 3 irq 8 */
|
142 |
|
|
SUN4M_INT_REALTIME, /* 4 irq 10 */
|
143 |
|
|
SUN4M_INT_FLOPPY, /* 5 irq 11 */
|
144 |
|
|
(SUN4M_INT_SERIAL | SUN4M_INT_KBDMS), /* 6 irq 12 */
|
145 |
|
|
SUN4M_INT_MODULE_ERR, /* 7 irq 15 */
|
146 |
|
|
SUN4M_INT_SBUS(0), /* 8 irq 2 */
|
147 |
|
|
SUN4M_INT_SBUS(1), /* 9 irq 3 */
|
148 |
|
|
SUN4M_INT_SBUS(2), /* 10 irq 5 */
|
149 |
|
|
SUN4M_INT_SBUS(3), /* 11 irq 7 */
|
150 |
|
|
SUN4M_INT_SBUS(4), /* 12 irq 9 */
|
151 |
|
|
SUN4M_INT_SBUS(5), /* 13 irq 11 */
|
152 |
|
|
SUN4M_INT_SBUS(6) /* 14 irq 13 */
|
153 |
|
|
};
|
154 |
|
|
|
155 |
|
|
static int sun4m_pil_map[] = { 0, 2, 3, 5, 7, 9, 11, 13 };
|
156 |
|
|
|
157 |
|
|
unsigned int sun4m_sbint_to_irq(struct sbus_dev *sdev, unsigned int sbint)
|
158 |
|
|
{
|
159 |
|
|
if (sbint >= sizeof(sun4m_pil_map)) {
|
160 |
|
|
printk(KERN_ERR "%s: bogus SBINT %d\n", sdev->prom_name, sbint);
|
161 |
|
|
BUG();
|
162 |
|
|
}
|
163 |
|
|
return sun4m_pil_map[sbint] | 0x30;
|
164 |
|
|
}
|
165 |
|
|
|
166 |
|
|
inline unsigned long sun4m_get_irqmask(unsigned int irq)
|
167 |
|
|
{
|
168 |
|
|
unsigned long mask;
|
169 |
|
|
|
170 |
|
|
if (irq > 0x20) {
|
171 |
|
|
/* OBIO/SBUS interrupts */
|
172 |
|
|
irq &= 0x1f;
|
173 |
|
|
mask = irq_mask[irq_xlate[irq]];
|
174 |
|
|
if (!mask)
|
175 |
|
|
printk("sun4m_get_irqmask: IRQ%d has no valid mask!\n",irq);
|
176 |
|
|
} else {
|
177 |
|
|
/* Soft Interrupts will come here.
|
178 |
|
|
* Currently there is no way to trigger them but I'm sure
|
179 |
|
|
* something could be cooked up.
|
180 |
|
|
*/
|
181 |
|
|
irq &= 0xf;
|
182 |
|
|
mask = SUN4M_SOFT_INT(irq);
|
183 |
|
|
}
|
184 |
|
|
return mask;
|
185 |
|
|
}
|
186 |
|
|
|
187 |
|
|
static void sun4m_disable_irq(unsigned int irq_nr)
|
188 |
|
|
{
|
189 |
|
|
unsigned long mask, flags;
|
190 |
|
|
int cpu = smp_processor_id();
|
191 |
|
|
|
192 |
|
|
mask = sun4m_get_irqmask(irq_nr);
|
193 |
|
|
local_irq_save(flags);
|
194 |
|
|
if (irq_nr > 15)
|
195 |
|
|
sun4m_interrupts->set = mask;
|
196 |
|
|
else
|
197 |
|
|
sun4m_interrupts->cpu_intregs[cpu].set = mask;
|
198 |
|
|
local_irq_restore(flags);
|
199 |
|
|
}
|
200 |
|
|
|
201 |
|
|
static void sun4m_enable_irq(unsigned int irq_nr)
|
202 |
|
|
{
|
203 |
|
|
unsigned long mask, flags;
|
204 |
|
|
int cpu = smp_processor_id();
|
205 |
|
|
|
206 |
|
|
/* Dreadful floppy hack. When we use 0x2b instead of
|
207 |
|
|
* 0x0b the system blows (it starts to whistle!).
|
208 |
|
|
* So we continue to use 0x0b. Fixme ASAP. --P3
|
209 |
|
|
*/
|
210 |
|
|
if (irq_nr != 0x0b) {
|
211 |
|
|
mask = sun4m_get_irqmask(irq_nr);
|
212 |
|
|
local_irq_save(flags);
|
213 |
|
|
if (irq_nr > 15)
|
214 |
|
|
sun4m_interrupts->clear = mask;
|
215 |
|
|
else
|
216 |
|
|
sun4m_interrupts->cpu_intregs[cpu].clear = mask;
|
217 |
|
|
local_irq_restore(flags);
|
218 |
|
|
} else {
|
219 |
|
|
local_irq_save(flags);
|
220 |
|
|
sun4m_interrupts->clear = SUN4M_INT_FLOPPY;
|
221 |
|
|
local_irq_restore(flags);
|
222 |
|
|
}
|
223 |
|
|
}
|
224 |
|
|
|
225 |
|
|
static unsigned long cpu_pil_to_imask[16] = {
|
226 |
|
|
/*0*/ 0x00000000,
|
227 |
|
|
/*1*/ 0x00000000,
|
228 |
|
|
/*2*/ SUN4M_INT_SBUS(0) | SUN4M_INT_VME(0),
|
229 |
|
|
/*3*/ SUN4M_INT_SBUS(1) | SUN4M_INT_VME(1),
|
230 |
|
|
/*4*/ SUN4M_INT_SCSI,
|
231 |
|
|
/*5*/ SUN4M_INT_SBUS(2) | SUN4M_INT_VME(2),
|
232 |
|
|
/*6*/ SUN4M_INT_ETHERNET,
|
233 |
|
|
/*7*/ SUN4M_INT_SBUS(3) | SUN4M_INT_VME(3),
|
234 |
|
|
/*8*/ SUN4M_INT_VIDEO,
|
235 |
|
|
/*9*/ SUN4M_INT_SBUS(4) | SUN4M_INT_VME(4) | SUN4M_INT_MODULE_ERR,
|
236 |
|
|
/*10*/ SUN4M_INT_REALTIME,
|
237 |
|
|
/*11*/ SUN4M_INT_SBUS(5) | SUN4M_INT_VME(5) | SUN4M_INT_FLOPPY,
|
238 |
|
|
/*12*/ SUN4M_INT_SERIAL | SUN4M_INT_KBDMS,
|
239 |
|
|
/*13*/ SUN4M_INT_AUDIO,
|
240 |
|
|
/*14*/ SUN4M_INT_E14,
|
241 |
|
|
/*15*/ 0x00000000
|
242 |
|
|
};
|
243 |
|
|
|
244 |
|
|
/* We assume the caller has disabled local interrupts when these are called,
|
245 |
|
|
* or else very bizarre behavior will result.
|
246 |
|
|
*/
|
247 |
|
|
static void sun4m_disable_pil_irq(unsigned int pil)
|
248 |
|
|
{
|
249 |
|
|
sun4m_interrupts->set = cpu_pil_to_imask[pil];
|
250 |
|
|
}
|
251 |
|
|
|
252 |
|
|
static void sun4m_enable_pil_irq(unsigned int pil)
|
253 |
|
|
{
|
254 |
|
|
sun4m_interrupts->clear = cpu_pil_to_imask[pil];
|
255 |
|
|
}
|
256 |
|
|
|
257 |
|
|
#ifdef CONFIG_SMP
|
258 |
|
|
static void sun4m_send_ipi(int cpu, int level)
|
259 |
|
|
{
|
260 |
|
|
unsigned long mask;
|
261 |
|
|
|
262 |
|
|
mask = sun4m_get_irqmask(level);
|
263 |
|
|
sun4m_interrupts->cpu_intregs[cpu].set = mask;
|
264 |
|
|
}
|
265 |
|
|
|
266 |
|
|
static void sun4m_clear_ipi(int cpu, int level)
|
267 |
|
|
{
|
268 |
|
|
unsigned long mask;
|
269 |
|
|
|
270 |
|
|
mask = sun4m_get_irqmask(level);
|
271 |
|
|
sun4m_interrupts->cpu_intregs[cpu].clear = mask;
|
272 |
|
|
}
|
273 |
|
|
|
274 |
|
|
static void sun4m_set_udt(int cpu)
|
275 |
|
|
{
|
276 |
|
|
sun4m_interrupts->undirected_target = cpu;
|
277 |
|
|
}
|
278 |
|
|
#endif
|
279 |
|
|
|
280 |
|
|
#define OBIO_INTR 0x20
|
281 |
|
|
#define TIMER_IRQ (OBIO_INTR | 10)
|
282 |
|
|
#define PROFILE_IRQ (OBIO_INTR | 14)
|
283 |
|
|
|
284 |
|
|
struct sun4m_timer_regs *sun4m_timers;
|
285 |
|
|
unsigned int lvl14_resolution = (((1000000/HZ) + 1) << 10);
|
286 |
|
|
|
287 |
|
|
static void sun4m_clear_clock_irq(void)
|
288 |
|
|
{
|
289 |
|
|
volatile unsigned int clear_intr;
|
290 |
|
|
clear_intr = sun4m_timers->l10_timer_limit;
|
291 |
|
|
}
|
292 |
|
|
|
293 |
|
|
static void sun4m_clear_profile_irq(int cpu)
|
294 |
|
|
{
|
295 |
|
|
volatile unsigned int clear;
|
296 |
|
|
|
297 |
|
|
clear = sun4m_timers->cpu_timers[cpu].l14_timer_limit;
|
298 |
|
|
}
|
299 |
|
|
|
300 |
|
|
static void sun4m_load_profile_irq(int cpu, unsigned int limit)
|
301 |
|
|
{
|
302 |
|
|
sun4m_timers->cpu_timers[cpu].l14_timer_limit = limit;
|
303 |
|
|
}
|
304 |
|
|
|
305 |
|
|
static void __init sun4m_init_timers(irq_handler_t counter_fn)
|
306 |
|
|
{
|
307 |
|
|
int reg_count, irq, cpu;
|
308 |
|
|
struct linux_prom_registers cnt_regs[PROMREG_MAX];
|
309 |
|
|
int obio_node, cnt_node;
|
310 |
|
|
struct resource r;
|
311 |
|
|
|
312 |
|
|
cnt_node = 0;
|
313 |
|
|
if((obio_node =
|
314 |
|
|
prom_searchsiblings (prom_getchild(prom_root_node), "obio")) == 0 ||
|
315 |
|
|
(obio_node = prom_getchild (obio_node)) == 0 ||
|
316 |
|
|
(cnt_node = prom_searchsiblings (obio_node, "counter")) == 0) {
|
317 |
|
|
prom_printf("Cannot find /obio/counter node\n");
|
318 |
|
|
prom_halt();
|
319 |
|
|
}
|
320 |
|
|
reg_count = prom_getproperty(cnt_node, "reg",
|
321 |
|
|
(void *) cnt_regs, sizeof(cnt_regs));
|
322 |
|
|
reg_count = (reg_count/sizeof(struct linux_prom_registers));
|
323 |
|
|
|
324 |
|
|
/* Apply the obio ranges to the timer registers. */
|
325 |
|
|
prom_apply_obio_ranges(cnt_regs, reg_count);
|
326 |
|
|
|
327 |
|
|
cnt_regs[4].phys_addr = cnt_regs[reg_count-1].phys_addr;
|
328 |
|
|
cnt_regs[4].reg_size = cnt_regs[reg_count-1].reg_size;
|
329 |
|
|
cnt_regs[4].which_io = cnt_regs[reg_count-1].which_io;
|
330 |
|
|
for(obio_node = 1; obio_node < 4; obio_node++) {
|
331 |
|
|
cnt_regs[obio_node].phys_addr =
|
332 |
|
|
cnt_regs[obio_node-1].phys_addr + PAGE_SIZE;
|
333 |
|
|
cnt_regs[obio_node].reg_size = cnt_regs[obio_node-1].reg_size;
|
334 |
|
|
cnt_regs[obio_node].which_io = cnt_regs[obio_node-1].which_io;
|
335 |
|
|
}
|
336 |
|
|
|
337 |
|
|
memset((char*)&r, 0, sizeof(struct resource));
|
338 |
|
|
/* Map the per-cpu Counter registers. */
|
339 |
|
|
r.flags = cnt_regs[0].which_io;
|
340 |
|
|
r.start = cnt_regs[0].phys_addr;
|
341 |
|
|
sun4m_timers = (struct sun4m_timer_regs *) sbus_ioremap(&r, 0,
|
342 |
|
|
PAGE_SIZE*SUN4M_NCPUS, "sun4m_cpu_cnt");
|
343 |
|
|
/* Map the system Counter register. */
|
344 |
|
|
/* XXX Here we expect consequent calls to yeld adjusent maps. */
|
345 |
|
|
r.flags = cnt_regs[4].which_io;
|
346 |
|
|
r.start = cnt_regs[4].phys_addr;
|
347 |
|
|
sbus_ioremap(&r, 0, cnt_regs[4].reg_size, "sun4m_sys_cnt");
|
348 |
|
|
|
349 |
|
|
sun4m_timers->l10_timer_limit = (((1000000/HZ) + 1) << 10);
|
350 |
|
|
master_l10_counter = &sun4m_timers->l10_cur_count;
|
351 |
|
|
master_l10_limit = &sun4m_timers->l10_timer_limit;
|
352 |
|
|
|
353 |
|
|
irq = request_irq(TIMER_IRQ,
|
354 |
|
|
counter_fn,
|
355 |
|
|
(IRQF_DISABLED | SA_STATIC_ALLOC),
|
356 |
|
|
"timer", NULL);
|
357 |
|
|
if (irq) {
|
358 |
|
|
prom_printf("time_init: unable to attach IRQ%d\n",TIMER_IRQ);
|
359 |
|
|
prom_halt();
|
360 |
|
|
}
|
361 |
|
|
|
362 |
|
|
if (!cpu_find_by_instance(1, NULL, NULL)) {
|
363 |
|
|
for(cpu = 0; cpu < 4; cpu++)
|
364 |
|
|
sun4m_timers->cpu_timers[cpu].l14_timer_limit = 0;
|
365 |
|
|
sun4m_interrupts->set = SUN4M_INT_E14;
|
366 |
|
|
} else {
|
367 |
|
|
sun4m_timers->cpu_timers[0].l14_timer_limit = 0;
|
368 |
|
|
}
|
369 |
|
|
#ifdef CONFIG_SMP
|
370 |
|
|
{
|
371 |
|
|
unsigned long flags;
|
372 |
|
|
extern unsigned long lvl14_save[4];
|
373 |
|
|
struct tt_entry *trap_table = &sparc_ttable[SP_TRAP_IRQ1 + (14 - 1)];
|
374 |
|
|
|
375 |
|
|
/* For SMP we use the level 14 ticker, however the bootup code
|
376 |
|
|
* has copied the firmware's level 14 vector into the boot cpu's
|
377 |
|
|
* trap table, we must fix this now or we get squashed.
|
378 |
|
|
*/
|
379 |
|
|
local_irq_save(flags);
|
380 |
|
|
trap_table->inst_one = lvl14_save[0];
|
381 |
|
|
trap_table->inst_two = lvl14_save[1];
|
382 |
|
|
trap_table->inst_three = lvl14_save[2];
|
383 |
|
|
trap_table->inst_four = lvl14_save[3];
|
384 |
|
|
local_flush_cache_all();
|
385 |
|
|
local_irq_restore(flags);
|
386 |
|
|
}
|
387 |
|
|
#endif
|
388 |
|
|
}
|
389 |
|
|
|
390 |
|
|
void __init sun4m_init_IRQ(void)
|
391 |
|
|
{
|
392 |
|
|
int ie_node,i;
|
393 |
|
|
struct linux_prom_registers int_regs[PROMREG_MAX];
|
394 |
|
|
int num_regs;
|
395 |
|
|
struct resource r;
|
396 |
|
|
int mid;
|
397 |
|
|
|
398 |
|
|
local_irq_disable();
|
399 |
|
|
if((ie_node = prom_searchsiblings(prom_getchild(prom_root_node), "obio")) == 0 ||
|
400 |
|
|
(ie_node = prom_getchild (ie_node)) == 0 ||
|
401 |
|
|
(ie_node = prom_searchsiblings (ie_node, "interrupt")) == 0) {
|
402 |
|
|
prom_printf("Cannot find /obio/interrupt node\n");
|
403 |
|
|
prom_halt();
|
404 |
|
|
}
|
405 |
|
|
num_regs = prom_getproperty(ie_node, "reg", (char *) int_regs,
|
406 |
|
|
sizeof(int_regs));
|
407 |
|
|
num_regs = (num_regs/sizeof(struct linux_prom_registers));
|
408 |
|
|
|
409 |
|
|
/* Apply the obio ranges to these registers. */
|
410 |
|
|
prom_apply_obio_ranges(int_regs, num_regs);
|
411 |
|
|
|
412 |
|
|
int_regs[4].phys_addr = int_regs[num_regs-1].phys_addr;
|
413 |
|
|
int_regs[4].reg_size = int_regs[num_regs-1].reg_size;
|
414 |
|
|
int_regs[4].which_io = int_regs[num_regs-1].which_io;
|
415 |
|
|
for(ie_node = 1; ie_node < 4; ie_node++) {
|
416 |
|
|
int_regs[ie_node].phys_addr = int_regs[ie_node-1].phys_addr + PAGE_SIZE;
|
417 |
|
|
int_regs[ie_node].reg_size = int_regs[ie_node-1].reg_size;
|
418 |
|
|
int_regs[ie_node].which_io = int_regs[ie_node-1].which_io;
|
419 |
|
|
}
|
420 |
|
|
|
421 |
|
|
memset((char *)&r, 0, sizeof(struct resource));
|
422 |
|
|
/* Map the interrupt registers for all possible cpus. */
|
423 |
|
|
r.flags = int_regs[0].which_io;
|
424 |
|
|
r.start = int_regs[0].phys_addr;
|
425 |
|
|
sun4m_interrupts = (struct sun4m_intregs *) sbus_ioremap(&r, 0,
|
426 |
|
|
PAGE_SIZE*SUN4M_NCPUS, "interrupts_percpu");
|
427 |
|
|
|
428 |
|
|
/* Map the system interrupt control registers. */
|
429 |
|
|
r.flags = int_regs[4].which_io;
|
430 |
|
|
r.start = int_regs[4].phys_addr;
|
431 |
|
|
sbus_ioremap(&r, 0, int_regs[4].reg_size, "interrupts_system");
|
432 |
|
|
|
433 |
|
|
sun4m_interrupts->set = ~SUN4M_INT_MASKALL;
|
434 |
|
|
for (i = 0; !cpu_find_by_instance(i, NULL, &mid); i++)
|
435 |
|
|
sun4m_interrupts->cpu_intregs[mid].clear = ~0x17fff;
|
436 |
|
|
|
437 |
|
|
if (!cpu_find_by_instance(1, NULL, NULL)) {
|
438 |
|
|
/* system wide interrupts go to cpu 0, this should always
|
439 |
|
|
* be safe because it is guaranteed to be fitted or OBP doesn't
|
440 |
|
|
* come up
|
441 |
|
|
*
|
442 |
|
|
* Not sure, but writing here on SLAVIO systems may puke
|
443 |
|
|
* so I don't do it unless there is more than 1 cpu.
|
444 |
|
|
*/
|
445 |
|
|
irq_rcvreg = (unsigned long *)
|
446 |
|
|
&sun4m_interrupts->undirected_target;
|
447 |
|
|
sun4m_interrupts->undirected_target = 0;
|
448 |
|
|
}
|
449 |
|
|
BTFIXUPSET_CALL(sbint_to_irq, sun4m_sbint_to_irq, BTFIXUPCALL_NORM);
|
450 |
|
|
BTFIXUPSET_CALL(enable_irq, sun4m_enable_irq, BTFIXUPCALL_NORM);
|
451 |
|
|
BTFIXUPSET_CALL(disable_irq, sun4m_disable_irq, BTFIXUPCALL_NORM);
|
452 |
|
|
BTFIXUPSET_CALL(enable_pil_irq, sun4m_enable_pil_irq, BTFIXUPCALL_NORM);
|
453 |
|
|
BTFIXUPSET_CALL(disable_pil_irq, sun4m_disable_pil_irq, BTFIXUPCALL_NORM);
|
454 |
|
|
BTFIXUPSET_CALL(clear_clock_irq, sun4m_clear_clock_irq, BTFIXUPCALL_NORM);
|
455 |
|
|
BTFIXUPSET_CALL(clear_profile_irq, sun4m_clear_profile_irq, BTFIXUPCALL_NORM);
|
456 |
|
|
BTFIXUPSET_CALL(load_profile_irq, sun4m_load_profile_irq, BTFIXUPCALL_NORM);
|
457 |
|
|
sparc_init_timers = sun4m_init_timers;
|
458 |
|
|
#ifdef CONFIG_SMP
|
459 |
|
|
BTFIXUPSET_CALL(set_cpu_int, sun4m_send_ipi, BTFIXUPCALL_NORM);
|
460 |
|
|
BTFIXUPSET_CALL(clear_cpu_int, sun4m_clear_ipi, BTFIXUPCALL_NORM);
|
461 |
|
|
BTFIXUPSET_CALL(set_irq_udt, sun4m_set_udt, BTFIXUPCALL_NORM);
|
462 |
|
|
#endif
|
463 |
|
|
/* Cannot enable interrupts until OBP ticker is disabled. */
|
464 |
|
|
}
|