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[/] [or1k_soc_on_altera_embedded_dev_kit/] [trunk/] [linux-2.6/] [linux-2.6.24/] [arch/] [sparc/] [kernel/] [trampoline.S] - Blame information for rev 3

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1 3 xianfeng 
/* $Id: trampoline.S,v 1.14 2002/01/11 08:45:38 davem Exp $
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 * trampoline.S: SMP cpu boot-up trampoline code.
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 *
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 * Copyright (C) 1995 David S. Miller (davem@caip.rutgers.edu)
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 * Copyright (C) 1998 Jakub Jelinek (jj@sunsite.mff.cuni.cz)
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 */
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#include
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#include
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#include
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#include
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#include
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#include
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#include
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#include
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#include
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        .globl sun4m_cpu_startup, __smp4m_processor_id
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        .globl sun4d_cpu_startup, __smp4d_processor_id
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        __INIT
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        .align 4
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/* When we start up a cpu for the first time it enters this routine.
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 * This initializes the chip from whatever state the prom left it
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 * in and sets PIL in %psr to 15, no irqs.
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 */
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sun4m_cpu_startup:
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cpu1_startup:
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        sethi   %hi(trapbase_cpu1), %g3
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        b       1f
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         or     %g3, %lo(trapbase_cpu1), %g3
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cpu2_startup:
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        sethi   %hi(trapbase_cpu2), %g3
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        b       1f
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         or     %g3, %lo(trapbase_cpu2), %g3
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cpu3_startup:
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        sethi   %hi(trapbase_cpu3), %g3
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        b       1f
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         or     %g3, %lo(trapbase_cpu3), %g3
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1:
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        /* Set up a sane %psr -- PIL<0xf> S<0x1> PS<0x1> CWP<0x0> */
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        set     (PSR_PIL | PSR_S | PSR_PS), %g1
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        wr      %g1, 0x0, %psr          ! traps off though
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        WRITE_PAUSE
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        /* Our %wim is one behind CWP */
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        mov     2, %g1
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        wr      %g1, 0x0, %wim
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        WRITE_PAUSE
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        /* This identifies "this cpu". */
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        wr      %g3, 0x0, %tbr
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        WRITE_PAUSE
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        /* Give ourselves a stack and curptr. */
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        set     current_set, %g5
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        srl     %g3, 10, %g4
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        and     %g4, 0xc, %g4
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        ld      [%g5 + %g4], %g6
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        sethi   %hi(THREAD_SIZE - STACKFRAME_SZ), %sp
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        or      %sp, %lo(THREAD_SIZE - STACKFRAME_SZ), %sp
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        add     %g6, %sp, %sp
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        /* Turn on traps (PSR_ET). */
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        rd      %psr, %g1
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        wr      %g1, PSR_ET, %psr       ! traps on
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        WRITE_PAUSE
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        /* Init our caches, etc. */
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        set     poke_srmmu, %g5
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        ld      [%g5], %g5
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        call    %g5
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         nop
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        /* Start this processor. */
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        call    smp4m_callin
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         nop
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        b,a     smp_do_cpu_idle
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        .text
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        .align  4
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smp_do_cpu_idle:
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        call    cpu_idle
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         mov    0, %o0
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        call    cpu_panic
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         nop
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__smp4m_processor_id:
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        rd      %tbr, %g2
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        srl     %g2, 12, %g2
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        and     %g2, 3, %g2
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        retl
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         mov    %g1, %o7
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__smp4d_processor_id:
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        lda     [%g0] ASI_M_VIKING_TMP1, %g2
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        retl
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         mov    %g1, %o7
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/* CPUID in bootbus can be found at PA 0xff0140000 */
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#define SUN4D_BOOTBUS_CPUID     0xf0140000
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        __INIT
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        .align  4
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sun4d_cpu_startup:
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        /* Set up a sane %psr -- PIL<0xf> S<0x1> PS<0x1> CWP<0x0> */
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        set     (PSR_PIL | PSR_S | PSR_PS), %g1
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        wr      %g1, 0x0, %psr          ! traps off though
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        WRITE_PAUSE
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        /* Our %wim is one behind CWP */
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        mov     2, %g1
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        wr      %g1, 0x0, %wim
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        WRITE_PAUSE
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        /* Set tbr - we use just one trap table. */
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        set     trapbase, %g1
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        wr      %g1, 0x0, %tbr
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        WRITE_PAUSE
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        /* Get our CPU id out of bootbus */
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        set     SUN4D_BOOTBUS_CPUID, %g3
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        lduba   [%g3] ASI_M_CTL, %g3
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        and     %g3, 0xf8, %g3
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        srl     %g3, 3, %g1
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        sta     %g1, [%g0] ASI_M_VIKING_TMP1
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        /* Give ourselves a stack and curptr. */
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        set     current_set, %g5
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        srl     %g3, 1, %g4
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        ld      [%g5 + %g4], %g6
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        sethi   %hi(THREAD_SIZE - STACKFRAME_SZ), %sp
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        or      %sp, %lo(THREAD_SIZE - STACKFRAME_SZ), %sp
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        add     %g6, %sp, %sp
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        /* Turn on traps (PSR_ET). */
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        rd      %psr, %g1
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        wr      %g1, PSR_ET, %psr       ! traps on
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        WRITE_PAUSE
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        /* Init our caches, etc. */
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        set     poke_srmmu, %g5
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        ld      [%g5], %g5
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        call    %g5
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         nop
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        /* Start this processor. */
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        call    smp4d_callin
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         nop
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        b,a     smp_do_cpu_idle

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