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[/] [or1k_soc_on_altera_embedded_dev_kit/] [trunk/] [linux-2.6/] [linux-2.6.24/] [arch/] [sparc/] [mm/] [swift.S] - Blame information for rev 3

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Line No. Rev Author Line
1 3 xianfeng 
/* $Id: swift.S,v 1.9 2002/01/08 11:11:59 davem Exp $
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 * swift.S: MicroSparc-II mmu/cache operations.
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 *
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 * Copyright (C) 1999 David S. Miller (davem@redhat.com)
5 
 */
6 
 
7 
#include
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#include
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#include
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#include
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#include
12 
 
13 
        .text
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        .align  4
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16 
#if 1   /* XXX screw this, I can't get the VAC flushes working
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         * XXX reliably... -DaveM
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         */
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        .globl  swift_flush_cache_all, swift_flush_cache_mm
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        .globl  swift_flush_cache_range, swift_flush_cache_page
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        .globl  swift_flush_page_for_dma
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        .globl  swift_flush_page_to_ram
23 
 
24 
swift_flush_cache_all:
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swift_flush_cache_mm:
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swift_flush_cache_range:
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swift_flush_cache_page:
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swift_flush_page_for_dma:
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swift_flush_page_to_ram:
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        sethi   %hi(0x2000), %o0
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1:      subcc   %o0, 0x10, %o0
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        add     %o0, %o0, %o1
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        sta     %g0, [%o0] ASI_M_DATAC_TAG
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        bne     1b
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         sta    %g0, [%o1] ASI_M_TXTC_TAG
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        retl
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         nop
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#else
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        .globl  swift_flush_cache_all
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swift_flush_cache_all:
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        WINDOW_FLUSH(%g4, %g5)
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        /* Just clear out all the tags. */
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        sethi   %hi(16 * 1024), %o0
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1:      subcc   %o0, 16, %o0
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        sta     %g0, [%o0] ASI_M_TXTC_TAG
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        bne     1b
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         sta    %g0, [%o0] ASI_M_DATAC_TAG
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        retl
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         nop
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53 
        .globl  swift_flush_cache_mm
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swift_flush_cache_mm:
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        ld      [%o0 + AOFF_mm_context], %g2
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        cmp     %g2, -1
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        be      swift_flush_cache_mm_out
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        WINDOW_FLUSH(%g4, %g5)
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        rd      %psr, %g1
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        andn    %g1, PSR_ET, %g3
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        wr      %g3, 0x0, %psr
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        nop
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        nop
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        mov     SRMMU_CTX_REG, %g7
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        lda     [%g7] ASI_M_MMUREGS, %g5
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        sta     %g2, [%g7] ASI_M_MMUREGS
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#if 1
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        sethi   %hi(0x2000), %o0
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1:      subcc   %o0, 0x10, %o0
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        sta     %g0, [%o0] ASI_M_FLUSH_CTX
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        bne     1b
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         nop
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#else
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        clr     %o0
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        or      %g0, 2048, %g7
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        or      %g0, 2048, %o1
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        add     %o1, 2048, %o2
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        add     %o2, 2048, %o3
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        mov     16, %o4
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        add     %o4, 2048, %o5
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        add     %o5, 2048, %g2
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        add     %g2, 2048, %g3
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1:      sta     %g0, [%o0      ] ASI_M_FLUSH_CTX
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        sta     %g0, [%o0 + %o1] ASI_M_FLUSH_CTX
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        sta     %g0, [%o0 + %o2] ASI_M_FLUSH_CTX
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        sta     %g0, [%o0 + %o3] ASI_M_FLUSH_CTX
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        sta     %g0, [%o0 + %o4] ASI_M_FLUSH_CTX
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        sta     %g0, [%o0 + %o5] ASI_M_FLUSH_CTX
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        sta     %g0, [%o0 + %g2] ASI_M_FLUSH_CTX
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        sta     %g0, [%o0 + %g3] ASI_M_FLUSH_CTX
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        subcc   %g7, 32, %g7
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        bne     1b
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         add    %o0, 32, %o0
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#endif
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        mov     SRMMU_CTX_REG, %g7
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        sta     %g5, [%g7] ASI_M_MMUREGS
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        wr      %g1, 0x0, %psr
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        nop
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        nop
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swift_flush_cache_mm_out:
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        retl
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         nop
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106 
        .globl  swift_flush_cache_range
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swift_flush_cache_range:
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        ld      [%o0 + 0x0], %o0                /* XXX vma->vm_mm, GROSS XXX */
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        sub     %o2, %o1, %o2
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        sethi   %hi(4096), %o3
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        cmp     %o2, %o3
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        bgu     swift_flush_cache_mm
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         nop
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        b       70f
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         nop
116 
 
117 
        .globl  swift_flush_cache_page
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swift_flush_cache_page:
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        ld      [%o0 + 0x0], %o0                /* XXX vma->vm_mm, GROSS XXX */
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70:
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        ld      [%o0 + AOFF_mm_context], %g2
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        cmp     %g2, -1
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        be      swift_flush_cache_page_out
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        WINDOW_FLUSH(%g4, %g5)
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        rd      %psr, %g1
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        andn    %g1, PSR_ET, %g3
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        wr      %g3, 0x0, %psr
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        nop
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        nop
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        mov     SRMMU_CTX_REG, %g7
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        lda     [%g7] ASI_M_MMUREGS, %g5
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        sta     %g2, [%g7] ASI_M_MMUREGS
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134 
        andn    %o1, (PAGE_SIZE - 1), %o1
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#if 1
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        sethi   %hi(0x1000), %o0
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1:      subcc   %o0, 0x10, %o0
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        sta     %g0, [%o1 + %o0] ASI_M_FLUSH_PAGE
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        bne     1b
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         nop
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#else
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        or      %g0, 512, %g7
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        or      %g0, 512, %o0
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        add     %o0, 512, %o2
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        add     %o2, 512, %o3
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        add     %o3, 512, %o4
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        add     %o4, 512, %o5
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        add     %o5, 512, %g3
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        add     %g3, 512, %g4
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1:      sta     %g0, [%o1      ] ASI_M_FLUSH_PAGE
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        sta     %g0, [%o1 + %o0] ASI_M_FLUSH_PAGE
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        sta     %g0, [%o1 + %o2] ASI_M_FLUSH_PAGE
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        sta     %g0, [%o1 + %o3] ASI_M_FLUSH_PAGE
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        sta     %g0, [%o1 + %o4] ASI_M_FLUSH_PAGE
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        sta     %g0, [%o1 + %o5] ASI_M_FLUSH_PAGE
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        sta     %g0, [%o1 + %g3] ASI_M_FLUSH_PAGE
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        sta     %g0, [%o1 + %g4] ASI_M_FLUSH_PAGE
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        subcc   %g7, 16, %g7
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        bne     1b
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         add    %o1, 16, %o1
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#endif
162 
 
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        mov     SRMMU_CTX_REG, %g7
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        sta     %g5, [%g7] ASI_M_MMUREGS
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        wr      %g1, 0x0, %psr
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        nop
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        nop
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swift_flush_cache_page_out:
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        retl
170 
         nop
171 
 
172 
        /* Swift is write-thru, however it is not
173 
         * I/O nor TLB-walk coherent.  Also it has
174 
         * caches which are virtually indexed and tagged.
175 
         */
176 
        .globl  swift_flush_page_for_dma
177 
        .globl  swift_flush_page_to_ram
178 
swift_flush_page_for_dma:
179 
swift_flush_page_to_ram:
180 
        andn    %o0, (PAGE_SIZE - 1), %o1
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#if 1
182 
        sethi   %hi(0x1000), %o0
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1:      subcc   %o0, 0x10, %o0
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        sta     %g0, [%o1 + %o0] ASI_M_FLUSH_PAGE
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        bne     1b
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         nop
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#else
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        or      %g0, 512, %g7
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        or      %g0, 512, %o0
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        add     %o0, 512, %o2
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        add     %o2, 512, %o3
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        add     %o3, 512, %o4
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        add     %o4, 512, %o5
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        add     %o5, 512, %g3
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        add     %g3, 512, %g4
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1:      sta     %g0, [%o1      ] ASI_M_FLUSH_PAGE
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        sta     %g0, [%o1 + %o0] ASI_M_FLUSH_PAGE
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        sta     %g0, [%o1 + %o2] ASI_M_FLUSH_PAGE
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        sta     %g0, [%o1 + %o3] ASI_M_FLUSH_PAGE
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        sta     %g0, [%o1 + %o4] ASI_M_FLUSH_PAGE
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        sta     %g0, [%o1 + %o5] ASI_M_FLUSH_PAGE
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        sta     %g0, [%o1 + %g3] ASI_M_FLUSH_PAGE
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        sta     %g0, [%o1 + %g4] ASI_M_FLUSH_PAGE
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        subcc   %g7, 16, %g7
205 
        bne     1b
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         add    %o1, 16, %o1
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#endif
208 
        retl
209 
         nop
210 
#endif
211 
 
212 
        .globl  swift_flush_sig_insns
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swift_flush_sig_insns:
214 
        flush   %o1
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        retl
216 
         flush  %o1 + 4
217 
 
218 
        .globl  swift_flush_tlb_mm
219 
        .globl  swift_flush_tlb_range
220 
        .globl  swift_flush_tlb_all
221 
swift_flush_tlb_range:
222 
        ld      [%o0 + 0x00], %o0       /* XXX vma->vm_mm GROSS XXX */
223 
swift_flush_tlb_mm:
224 
        ld      [%o0 + AOFF_mm_context], %g2
225 
        cmp     %g2, -1
226 
        be      swift_flush_tlb_all_out
227 
swift_flush_tlb_all:
228 
        mov     0x400, %o1
229 
        sta     %g0, [%o1] ASI_M_FLUSH_PROBE
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swift_flush_tlb_all_out:
231 
        retl
232 
         nop
233 
 
234 
        .globl  swift_flush_tlb_page
235 
swift_flush_tlb_page:
236 
        ld      [%o0 + 0x00], %o0       /* XXX vma->vm_mm GROSS XXX */
237 
        mov     SRMMU_CTX_REG, %g1
238 
        ld      [%o0 + AOFF_mm_context], %o3
239 
        andn    %o1, (PAGE_SIZE - 1), %o1
240 
        cmp     %o3, -1
241 
        be      swift_flush_tlb_page_out
242 
         nop
243 
#if 1
244 
        mov     0x400, %o1
245 
        sta     %g0, [%o1] ASI_M_FLUSH_PROBE
246 
#else
247 
        lda     [%g1] ASI_M_MMUREGS, %g5
248 
        sta     %o3, [%g1] ASI_M_MMUREGS
249 
        sta     %g0, [%o1] ASI_M_FLUSH_PAGE     /* rem. virt. cache. prot. */
250 
        sta     %g0, [%o1] ASI_M_FLUSH_PROBE
251 
        sta     %g5, [%g1] ASI_M_MMUREGS
252 
#endif
253 
swift_flush_tlb_page_out:
254 
        retl
255 
         nop

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