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xianfeng |
#include <linux/init.h>
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#include <linux/bitops.h>
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#include <linux/mm.h>
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#include <asm/io.h>
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#include <asm/processor.h>
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#include <asm/apic.h>
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#include <asm/mach_apic.h>
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#include "cpu.h"
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/*
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* B step AMD K6 before B 9730xxxx have hardware bugs that can cause
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* misexecution of code under Linux. Owners of such processors should
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* contact AMD for precise details and a CPU swap.
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*
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* See http://www.multimania.com/poulot/k6bug.html
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* http://www.amd.com/K6/k6docs/revgd.html
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*
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* The following test is erm.. interesting. AMD neglected to up
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* the chip setting when fixing the bug but they also tweaked some
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* performance at the same time..
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*/
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extern void vide(void);
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__asm__(".align 4\nvide: ret");
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#ifdef CONFIG_X86_LOCAL_APIC
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#define ENABLE_C1E_MASK 0x18000000
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#define CPUID_PROCESSOR_SIGNATURE 1
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#define CPUID_XFAM 0x0ff00000
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#define CPUID_XFAM_K8 0x00000000
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#define CPUID_XFAM_10H 0x00100000
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#define CPUID_XFAM_11H 0x00200000
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#define CPUID_XMOD 0x000f0000
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#define CPUID_XMOD_REV_F 0x00040000
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/* AMD systems with C1E don't have a working lAPIC timer. Check for that. */
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static __cpuinit int amd_apic_timer_broken(void)
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{
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u32 lo, hi;
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u32 eax = cpuid_eax(CPUID_PROCESSOR_SIGNATURE);
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switch (eax & CPUID_XFAM) {
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case CPUID_XFAM_K8:
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if ((eax & CPUID_XMOD) < CPUID_XMOD_REV_F)
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break;
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case CPUID_XFAM_10H:
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case CPUID_XFAM_11H:
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rdmsr(MSR_K8_ENABLE_C1E, lo, hi);
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if (lo & ENABLE_C1E_MASK) {
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if (smp_processor_id() != boot_cpu_physical_apicid)
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printk(KERN_INFO "AMD C1E detected late. "
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" Force timer broadcast.\n");
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return 1;
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}
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break;
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default:
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/* err on the side of caution */
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return 1;
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}
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return 0;
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}
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#endif
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int force_mwait __cpuinitdata;
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static void __cpuinit init_amd(struct cpuinfo_x86 *c)
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{
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u32 l, h;
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int mbytes = num_physpages >> (20-PAGE_SHIFT);
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int r;
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#ifdef CONFIG_SMP
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unsigned long long value;
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/* Disable TLB flush filter by setting HWCR.FFDIS on K8
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* bit 6 of msr C001_0015
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*
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* Errata 63 for SH-B3 steppings
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* Errata 122 for all steppings (F+ have it disabled by default)
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*/
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if (c->x86 == 15) {
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rdmsrl(MSR_K7_HWCR, value);
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value |= 1 << 6;
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wrmsrl(MSR_K7_HWCR, value);
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}
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#endif
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/*
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* FIXME: We should handle the K5 here. Set up the write
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* range and also turn on MSR 83 bits 4 and 31 (write alloc,
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* no bus pipeline)
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*/
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/* Bit 31 in normal CPUID used for nonstandard 3DNow ID;
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3DNow is IDd by bit 31 in extended CPUID (1*32+31) anyway */
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clear_bit(0*32+31, c->x86_capability);
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r = get_model_name(c);
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switch(c->x86)
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{
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case 4:
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/*
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* General Systems BIOSen alias the cpu frequency registers
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* of the Elan at 0x000df000. Unfortuantly, one of the Linux
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* drivers subsequently pokes it, and changes the CPU speed.
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* Workaround : Remove the unneeded alias.
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*/
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#define CBAR (0xfffc) /* Configuration Base Address (32-bit) */
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#define CBAR_ENB (0x80000000)
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#define CBAR_KEY (0X000000CB)
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if (c->x86_model==9 || c->x86_model == 10) {
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if (inl (CBAR) & CBAR_ENB)
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outl (0 | CBAR_KEY, CBAR);
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}
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break;
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case 5:
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if( c->x86_model < 6 )
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{
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/* Based on AMD doc 20734R - June 2000 */
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if ( c->x86_model == 0 ) {
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clear_bit(X86_FEATURE_APIC, c->x86_capability);
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set_bit(X86_FEATURE_PGE, c->x86_capability);
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}
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break;
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}
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| 128 |
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if ( c->x86_model == 6 && c->x86_mask == 1 ) {
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const int K6_BUG_LOOP = 1000000;
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int n;
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void (*f_vide)(void);
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unsigned long d, d2;
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printk(KERN_INFO "AMD K6 stepping B detected - ");
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/*
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* It looks like AMD fixed the 2.6.2 bug and improved indirect
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* calls at the same time.
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*/
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n = K6_BUG_LOOP;
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f_vide = vide;
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rdtscl(d);
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while (n--)
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f_vide();
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rdtscl(d2);
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d = d2-d;
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if (d > 20*K6_BUG_LOOP)
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printk("system stability may be impaired when more than 32 MB are used.\n");
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else
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printk("probably OK (after B9730xxxx).\n");
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printk(KERN_INFO "Please see http://membres.lycos.fr/poulot/k6bug.html\n");
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}
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| 156 |
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/* K6 with old style WHCR */
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if (c->x86_model < 8 ||
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(c->x86_model== 8 && c->x86_mask < 8)) {
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/* We can only write allocate on the low 508Mb */
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if(mbytes>508)
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mbytes=508;
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rdmsr(MSR_K6_WHCR, l, h);
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if ((l&0x0000FFFF)==0) {
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unsigned long flags;
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l=(1<<0)|((mbytes/4)<<1);
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local_irq_save(flags);
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wbinvd();
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wrmsr(MSR_K6_WHCR, l, h);
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local_irq_restore(flags);
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printk(KERN_INFO "Enabling old style K6 write allocation for %d Mb\n",
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mbytes);
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}
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break;
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}
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if ((c->x86_model == 8 && c->x86_mask >7) ||
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c->x86_model == 9 || c->x86_model == 13) {
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/* The more serious chips .. */
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if(mbytes>4092)
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mbytes=4092;
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| 184 |
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rdmsr(MSR_K6_WHCR, l, h);
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if ((l&0xFFFF0000)==0) {
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unsigned long flags;
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l=((mbytes>>2)<<22)|(1<<16);
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local_irq_save(flags);
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wbinvd();
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wrmsr(MSR_K6_WHCR, l, h);
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local_irq_restore(flags);
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printk(KERN_INFO "Enabling new style K6 write allocation for %d Mb\n",
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mbytes);
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| 194 |
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}
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| 196 |
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/* Set MTRR capability flag if appropriate */
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| 197 |
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if (c->x86_model == 13 || c->x86_model == 9 ||
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(c->x86_model == 8 && c->x86_mask >= 8))
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set_bit(X86_FEATURE_K6_MTRR, c->x86_capability);
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break;
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| 201 |
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}
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| 203 |
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if (c->x86_model == 10) {
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| 204 |
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/* AMD Geode LX is model 10 */
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| 205 |
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/* placeholder for any needed mods */
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| 206 |
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break;
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| 207 |
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}
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| 208 |
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break;
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case 6: /* An Athlon/Duron */
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| 210 |
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| 211 |
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/* Bit 15 of Athlon specific MSR 15, needs to be 0
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| 212 |
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* to enable SSE on Palomino/Morgan/Barton CPU's.
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| 213 |
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* If the BIOS didn't enable it already, enable it here.
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| 214 |
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*/
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| 215 |
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if (c->x86_model >= 6 && c->x86_model <= 10) {
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| 216 |
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if (!cpu_has(c, X86_FEATURE_XMM)) {
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| 217 |
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printk(KERN_INFO "Enabling disabled K7/SSE Support.\n");
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| 218 |
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rdmsr(MSR_K7_HWCR, l, h);
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| 219 |
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l &= ~0x00008000;
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| 220 |
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wrmsr(MSR_K7_HWCR, l, h);
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| 221 |
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set_bit(X86_FEATURE_XMM, c->x86_capability);
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| 222 |
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}
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| 223 |
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}
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| 224 |
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| 225 |
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/* It's been determined by AMD that Athlons since model 8 stepping 1
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| 226 |
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* are more robust with CLK_CTL set to 200xxxxx instead of 600xxxxx
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| 227 |
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* As per AMD technical note 27212 0.2
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| 228 |
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*/
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| 229 |
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if ((c->x86_model == 8 && c->x86_mask>=1) || (c->x86_model > 8)) {
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| 230 |
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rdmsr(MSR_K7_CLK_CTL, l, h);
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| 231 |
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if ((l & 0xfff00000) != 0x20000000) {
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| 232 |
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printk ("CPU: CLK_CTL MSR was %x. Reprogramming to %x\n", l,
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| 233 |
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((l & 0x000fffff)|0x20000000));
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| 234 |
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wrmsr(MSR_K7_CLK_CTL, (l & 0x000fffff)|0x20000000, h);
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| 235 |
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}
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| 236 |
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}
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| 237 |
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break;
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| 238 |
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}
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| 239 |
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| 240 |
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switch (c->x86) {
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| 241 |
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case 15:
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| 242 |
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/* Use K8 tuning for Fam10h and Fam11h */
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| 243 |
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case 0x10:
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| 244 |
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case 0x11:
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| 245 |
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set_bit(X86_FEATURE_K8, c->x86_capability);
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| 246 |
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break;
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| 247 |
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case 6:
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| 248 |
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set_bit(X86_FEATURE_K7, c->x86_capability);
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| 249 |
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break;
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| 250 |
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}
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| 251 |
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if (c->x86 >= 6)
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| 252 |
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set_bit(X86_FEATURE_FXSAVE_LEAK, c->x86_capability);
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| 253 |
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| 254 |
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display_cacheinfo(c);
|
| 255 |
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|
| 256 |
|
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if (cpuid_eax(0x80000000) >= 0x80000008) {
|
| 257 |
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c->x86_max_cores = (cpuid_ecx(0x80000008) & 0xff) + 1;
|
| 258 |
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}
|
| 259 |
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|
| 260 |
|
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if (cpuid_eax(0x80000000) >= 0x80000007) {
|
| 261 |
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c->x86_power = cpuid_edx(0x80000007);
|
| 262 |
|
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if (c->x86_power & (1<<8))
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| 263 |
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set_bit(X86_FEATURE_CONSTANT_TSC, c->x86_capability);
|
| 264 |
|
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}
|
| 265 |
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|
| 266 |
|
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#ifdef CONFIG_X86_HT
|
| 267 |
|
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/*
|
| 268 |
|
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* On a AMD multi core setup the lower bits of the APIC id
|
| 269 |
|
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* distinguish the cores.
|
| 270 |
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*/
|
| 271 |
|
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if (c->x86_max_cores > 1) {
|
| 272 |
|
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int cpu = smp_processor_id();
|
| 273 |
|
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unsigned bits = (cpuid_ecx(0x80000008) >> 12) & 0xf;
|
| 274 |
|
|
|
| 275 |
|
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if (bits == 0) {
|
| 276 |
|
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while ((1 << bits) < c->x86_max_cores)
|
| 277 |
|
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bits++;
|
| 278 |
|
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}
|
| 279 |
|
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c->cpu_core_id = c->phys_proc_id & ((1<<bits)-1);
|
| 280 |
|
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c->phys_proc_id >>= bits;
|
| 281 |
|
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printk(KERN_INFO "CPU %d(%d) -> Core %d\n",
|
| 282 |
|
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cpu, c->x86_max_cores, c->cpu_core_id);
|
| 283 |
|
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}
|
| 284 |
|
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#endif
|
| 285 |
|
|
|
| 286 |
|
|
if (cpuid_eax(0x80000000) >= 0x80000006) {
|
| 287 |
|
|
if ((c->x86 == 0x10) && (cpuid_edx(0x80000006) & 0xf000))
|
| 288 |
|
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num_cache_leaves = 4;
|
| 289 |
|
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else
|
| 290 |
|
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num_cache_leaves = 3;
|
| 291 |
|
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}
|
| 292 |
|
|
|
| 293 |
|
|
#ifdef CONFIG_X86_LOCAL_APIC
|
| 294 |
|
|
if (amd_apic_timer_broken())
|
| 295 |
|
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local_apic_timer_disabled = 1;
|
| 296 |
|
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#endif
|
| 297 |
|
|
|
| 298 |
|
|
if (c->x86 == 0x10 && !force_mwait)
|
| 299 |
|
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clear_bit(X86_FEATURE_MWAIT, c->x86_capability);
|
| 300 |
|
|
|
| 301 |
|
|
/* K6s reports MCEs but don't actually have all the MSRs */
|
| 302 |
|
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if (c->x86 < 6)
|
| 303 |
|
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clear_bit(X86_FEATURE_MCE, c->x86_capability);
|
| 304 |
|
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}
|
| 305 |
|
|
|
| 306 |
|
|
static unsigned int __cpuinit amd_size_cache(struct cpuinfo_x86 * c, unsigned int size)
|
| 307 |
|
|
{
|
| 308 |
|
|
/* AMD errata T13 (order #21922) */
|
| 309 |
|
|
if ((c->x86 == 6)) {
|
| 310 |
|
|
if (c->x86_model == 3 && c->x86_mask == 0) /* Duron Rev A0 */
|
| 311 |
|
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size = 64;
|
| 312 |
|
|
if (c->x86_model == 4 &&
|
| 313 |
|
|
(c->x86_mask==0 || c->x86_mask==1)) /* Tbird rev A1/A2 */
|
| 314 |
|
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size = 256;
|
| 315 |
|
|
}
|
| 316 |
|
|
return size;
|
| 317 |
|
|
}
|
| 318 |
|
|
|
| 319 |
|
|
static struct cpu_dev amd_cpu_dev __cpuinitdata = {
|
| 320 |
|
|
.c_vendor = "AMD",
|
| 321 |
|
|
.c_ident = { "AuthenticAMD" },
|
| 322 |
|
|
.c_models = {
|
| 323 |
|
|
{ .vendor = X86_VENDOR_AMD, .family = 4, .model_names =
|
| 324 |
|
|
{
|
| 325 |
|
|
[3] = "486 DX/2",
|
| 326 |
|
|
[7] = "486 DX/2-WB",
|
| 327 |
|
|
[8] = "486 DX/4",
|
| 328 |
|
|
[9] = "486 DX/4-WB",
|
| 329 |
|
|
[14] = "Am5x86-WT",
|
| 330 |
|
|
[15] = "Am5x86-WB"
|
| 331 |
|
|
}
|
| 332 |
|
|
},
|
| 333 |
|
|
},
|
| 334 |
|
|
.c_init = init_amd,
|
| 335 |
|
|
.c_size_cache = amd_size_cache,
|
| 336 |
|
|
};
|
| 337 |
|
|
|
| 338 |
|
|
int __init amd_init_cpu(void)
|
| 339 |
|
|
{
|
| 340 |
|
|
cpu_devs[X86_VENDOR_AMD] = &amd_cpu_dev;
|
| 341 |
|
|
return 0;
|
| 342 |
|
|
}
|
