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[/] [or1k_soc_on_altera_embedded_dev_kit/] [trunk/] [linux-2.6/] [linux-2.6.24/] [drivers/] [ata/] [pata_cmd64x.c] - Blame information for rev 3

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/*
 * pata_cmd64x.c        - CMD64x PATA for new ATA layer
 *                        (C) 2005 Red Hat Inc
 *                        Alan Cox <alan@redhat.com>
 *
 * Based upon
 * linux/drivers/ide/pci/cmd64x.c               Version 1.30    Sept 10, 2002
 *
 * cmd64x.c: Enable interrupts at initialization time on Ultra/PCI machines.
 *           Note, this driver is not used at all on other systems because
 *           there the "BIOS" has done all of the following already.
 *           Due to massive hardware bugs, UltraDMA is only supported
 *           on the 646U2 and not on the 646U.
 *
 * Copyright (C) 1998           Eddie C. Dost  (ecd@skynet.be)
 * Copyright (C) 1998           David S. Miller (davem@redhat.com)
 *
 * Copyright (C) 1999-2002      Andre Hedrick <andre@linux-ide.org>
 *
 * TODO
 *      Testing work
 */
 
#include <linux/kernel.h>
#include <linux/module.h>
#include <linux/pci.h>
#include <linux/init.h>
#include <linux/blkdev.h>
#include <linux/delay.h>
#include <scsi/scsi_host.h>
#include <linux/libata.h>
 
#define DRV_NAME "pata_cmd64x"
#define DRV_VERSION "0.2.5"
 
/*
 * CMD64x specific registers definition.
 */
 
enum {
        CFR             = 0x50,
                CFR_INTR_CH0  = 0x02,
        CNTRL           = 0x51,
                CNTRL_DIS_RA0 = 0x40,
                CNTRL_DIS_RA1 = 0x80,
                CNTRL_ENA_2ND = 0x08,
        CMDTIM          = 0x52,
        ARTTIM0         = 0x53,
        DRWTIM0         = 0x54,
        ARTTIM1         = 0x55,
        DRWTIM1         = 0x56,
        ARTTIM23        = 0x57,
                ARTTIM23_DIS_RA2  = 0x04,
                ARTTIM23_DIS_RA3  = 0x08,
                ARTTIM23_INTR_CH1 = 0x10,
        ARTTIM2         = 0x57,
        ARTTIM3         = 0x57,
        DRWTIM23        = 0x58,
        DRWTIM2         = 0x58,
        BRST            = 0x59,
        DRWTIM3         = 0x5b,
        BMIDECR0        = 0x70,
        MRDMODE         = 0x71,
                MRDMODE_INTR_CH0 = 0x04,
                MRDMODE_INTR_CH1 = 0x08,
                MRDMODE_BLK_CH0  = 0x10,
                MRDMODE_BLK_CH1  = 0x20,
        BMIDESR0        = 0x72,
        UDIDETCR0       = 0x73,
        DTPR0           = 0x74,
        BMIDECR1        = 0x78,
        BMIDECSR        = 0x79,
        BMIDESR1        = 0x7A,
        UDIDETCR1       = 0x7B,
        DTPR1           = 0x7C
};
 
static int cmd648_cable_detect(struct ata_port *ap)
{
        struct pci_dev *pdev = to_pci_dev(ap->host->dev);
        u8 r;
 
        /* Check cable detect bits */
        pci_read_config_byte(pdev, BMIDECSR, &r);
        if (r & (1 << ap->port_no))
                return ATA_CBL_PATA80;
        return ATA_CBL_PATA40;
}
 
/**
 *      cmd64x_set_piomode      -       set PIO and MWDMA timing
 *      @ap: ATA interface
 *      @adev: ATA device
 *      @mode: mode
 *
 *      Called to do the PIO and MWDMA mode setup.
 */
 
static void cmd64x_set_timing(struct ata_port *ap, struct ata_device *adev, u8 mode)
{
        struct pci_dev *pdev = to_pci_dev(ap->host->dev);
        struct ata_timing t;
        const unsigned long T = 1000000 / 33;
        const u8 setup_data[] = { 0x40, 0x40, 0x40, 0x80, 0x00 };
 
        u8 reg;
 
        /* Port layout is not logical so use a table */
        const u8 arttim_port[2][2] = {
                { ARTTIM0, ARTTIM1 },
                { ARTTIM23, ARTTIM23 }
        };
        const u8 drwtim_port[2][2] = {
                { DRWTIM0, DRWTIM1 },
                { DRWTIM2, DRWTIM3 }
        };
 
        int arttim = arttim_port[ap->port_no][adev->devno];
        int drwtim = drwtim_port[ap->port_no][adev->devno];
 
        /* ata_timing_compute is smart and will produce timings for MWDMA
           that don't violate the drives PIO capabilities. */
        if (ata_timing_compute(adev, mode, &t, T, 0) < 0) {
                printk(KERN_ERR DRV_NAME ": mode computation failed.\n");
                return;
        }
        if (ap->port_no) {
                /* Slave has shared address setup */
                struct ata_device *pair = ata_dev_pair(adev);
 
                if (pair) {
                        struct ata_timing tp;
                        ata_timing_compute(pair, pair->pio_mode, &tp, T, 0);
                        ata_timing_merge(&t, &tp, &t, ATA_TIMING_SETUP);
                }
        }
 
        printk(KERN_DEBUG DRV_NAME ": active %d recovery %d setup %d.\n",
                t.active, t.recover, t.setup);
        if (t.recover > 16) {
                t.active += t.recover - 16;
                t.recover = 16;
        }
        if (t.active > 16)
                t.active = 16;
 
        /* Now convert the clocks into values we can actually stuff into
           the chip */
 
        if (t.recover > 1)
                t.recover--;
        else
                t.recover = 15;
 
        if (t.setup > 4)
                t.setup = 0xC0;
        else
                t.setup = setup_data[t.setup];
 
        t.active &= 0x0F;       /* 0 = 16 */
 
        /* Load setup timing */
        pci_read_config_byte(pdev, arttim, &reg);
        reg &= 0x3F;
        reg |= t.setup;
        pci_write_config_byte(pdev, arttim, reg);
 
        /* Load active/recovery */
        pci_write_config_byte(pdev, drwtim, (t.active << 4) | t.recover);
}
 
/**
 *      cmd64x_set_piomode      -       set initial PIO mode data
 *      @ap: ATA interface
 *      @adev: ATA device
 *
 *      Used when configuring the devices ot set the PIO timings. All the
 *      actual work is done by the PIO/MWDMA setting helper
 */
 
static void cmd64x_set_piomode(struct ata_port *ap, struct ata_device *adev)
{
        cmd64x_set_timing(ap, adev, adev->pio_mode);
}
 
/**
 *      cmd64x_set_dmamode      -       set initial DMA mode data
 *      @ap: ATA interface
 *      @adev: ATA device
 *
 *      Called to do the DMA mode setup.
 */
 
static void cmd64x_set_dmamode(struct ata_port *ap, struct ata_device *adev)
{
        static const u8 udma_data[] = {
                0x30, 0x20, 0x10, 0x20, 0x10, 0x00
        };
 
        struct pci_dev *pdev = to_pci_dev(ap->host->dev);
        u8 regU, regD;
 
        int pciU = UDIDETCR0 + 8 * ap->port_no;
        int pciD = BMIDESR0 + 8 * ap->port_no;
        int shift = 2 * adev->devno;
 
        pci_read_config_byte(pdev, pciD, &regD);
        pci_read_config_byte(pdev, pciU, &regU);
 
        /* DMA bits off */
        regD &= ~(0x20 << adev->devno);
        /* DMA control bits */
        regU &= ~(0x30 << shift);
        /* DMA timing bits */
        regU &= ~(0x05 << adev->devno);
 
        if (adev->dma_mode >= XFER_UDMA_0) {
                /* Merge the timing value */
                regU |= udma_data[adev->dma_mode - XFER_UDMA_0] << shift;
                /* Merge the control bits */
                regU |= 1 << adev->devno; /* UDMA on */
                if (adev->dma_mode > 2) /* 15nS timing */
                        regU |= 4 << adev->devno;
        } else {
                regU &= ~ (1 << adev->devno);   /* UDMA off */
                cmd64x_set_timing(ap, adev, adev->dma_mode);
        }
 
        regD |= 0x20 << adev->devno;
 
        pci_write_config_byte(pdev, pciU, regU);
        pci_write_config_byte(pdev, pciD, regD);
}
 
/**
 *      cmd648_dma_stop -       DMA stop callback
 *      @qc: Command in progress
 *
 *      DMA has completed.
 */
 
static void cmd648_bmdma_stop(struct ata_queued_cmd *qc)
{
        struct ata_port *ap = qc->ap;
        struct pci_dev *pdev = to_pci_dev(ap->host->dev);
        u8 dma_intr;
        int dma_mask = ap->port_no ? ARTTIM23_INTR_CH1 : CFR_INTR_CH0;
        int dma_reg = ap->port_no ? ARTTIM2 : CFR;
 
        ata_bmdma_stop(qc);
 
        pci_read_config_byte(pdev, dma_reg, &dma_intr);
        pci_write_config_byte(pdev, dma_reg, dma_intr | dma_mask);
}
 
/**
 *      cmd646r1_dma_stop       -       DMA stop callback
 *      @qc: Command in progress
 *
 *      Stub for now while investigating the r1 quirk in the old driver.
 */
 
static void cmd646r1_bmdma_stop(struct ata_queued_cmd *qc)
{
        ata_bmdma_stop(qc);
}
 
static struct scsi_host_template cmd64x_sht = {
        .module                 = THIS_MODULE,
        .name                   = DRV_NAME,
        .ioctl                  = ata_scsi_ioctl,
        .queuecommand           = ata_scsi_queuecmd,
        .can_queue              = ATA_DEF_QUEUE,
        .this_id                = ATA_SHT_THIS_ID,
        .sg_tablesize           = LIBATA_MAX_PRD,
        .cmd_per_lun            = ATA_SHT_CMD_PER_LUN,
        .emulated               = ATA_SHT_EMULATED,
        .use_clustering         = ATA_SHT_USE_CLUSTERING,
        .proc_name              = DRV_NAME,
        .dma_boundary           = ATA_DMA_BOUNDARY,
        .slave_configure        = ata_scsi_slave_config,
        .slave_destroy          = ata_scsi_slave_destroy,
        .bios_param             = ata_std_bios_param,
};
 
static struct ata_port_operations cmd64x_port_ops = {
        .set_piomode    = cmd64x_set_piomode,
        .set_dmamode    = cmd64x_set_dmamode,
        .mode_filter    = ata_pci_default_filter,
        .tf_load        = ata_tf_load,
        .tf_read        = ata_tf_read,
        .check_status   = ata_check_status,
        .exec_command   = ata_exec_command,
        .dev_select     = ata_std_dev_select,
 
        .freeze         = ata_bmdma_freeze,
        .thaw           = ata_bmdma_thaw,
        .error_handler  = ata_bmdma_error_handler,
        .post_internal_cmd = ata_bmdma_post_internal_cmd,
        .cable_detect   = ata_cable_40wire,
 
        .bmdma_setup    = ata_bmdma_setup,
        .bmdma_start    = ata_bmdma_start,
        .bmdma_stop     = ata_bmdma_stop,
        .bmdma_status   = ata_bmdma_status,
 
        .qc_prep        = ata_qc_prep,
        .qc_issue       = ata_qc_issue_prot,
 
        .data_xfer      = ata_data_xfer,
 
        .irq_handler    = ata_interrupt,
        .irq_clear      = ata_bmdma_irq_clear,
        .irq_on         = ata_irq_on,
 
        .port_start     = ata_port_start,
};
 
static struct ata_port_operations cmd646r1_port_ops = {
        .set_piomode    = cmd64x_set_piomode,
        .set_dmamode    = cmd64x_set_dmamode,
        .mode_filter    = ata_pci_default_filter,
        .tf_load        = ata_tf_load,
        .tf_read        = ata_tf_read,
        .check_status   = ata_check_status,
        .exec_command   = ata_exec_command,
        .dev_select     = ata_std_dev_select,
 
        .freeze         = ata_bmdma_freeze,
        .thaw           = ata_bmdma_thaw,
        .error_handler  = ata_bmdma_error_handler,
        .post_internal_cmd = ata_bmdma_post_internal_cmd,
        .cable_detect   = ata_cable_40wire,
 
        .bmdma_setup    = ata_bmdma_setup,
        .bmdma_start    = ata_bmdma_start,
        .bmdma_stop     = cmd646r1_bmdma_stop,
        .bmdma_status   = ata_bmdma_status,
 
        .qc_prep        = ata_qc_prep,
        .qc_issue       = ata_qc_issue_prot,
 
        .data_xfer      = ata_data_xfer,
 
        .irq_handler    = ata_interrupt,
        .irq_clear      = ata_bmdma_irq_clear,
        .irq_on         = ata_irq_on,
 
        .port_start     = ata_port_start,
};
 
static struct ata_port_operations cmd648_port_ops = {
        .set_piomode    = cmd64x_set_piomode,
        .set_dmamode    = cmd64x_set_dmamode,
        .mode_filter    = ata_pci_default_filter,
        .tf_load        = ata_tf_load,
        .tf_read        = ata_tf_read,
        .check_status   = ata_check_status,
        .exec_command   = ata_exec_command,
        .dev_select     = ata_std_dev_select,
 
        .freeze         = ata_bmdma_freeze,
        .thaw           = ata_bmdma_thaw,
        .error_handler  = ata_bmdma_error_handler,
        .post_internal_cmd = ata_bmdma_post_internal_cmd,
        .cable_detect   = cmd648_cable_detect,
 
        .bmdma_setup    = ata_bmdma_setup,
        .bmdma_start    = ata_bmdma_start,
        .bmdma_stop     = cmd648_bmdma_stop,
        .bmdma_status   = ata_bmdma_status,
 
        .qc_prep        = ata_qc_prep,
        .qc_issue       = ata_qc_issue_prot,
 
        .data_xfer      = ata_data_xfer,
 
        .irq_handler    = ata_interrupt,
        .irq_clear      = ata_bmdma_irq_clear,
        .irq_on         = ata_irq_on,
 
        .port_start     = ata_port_start,
};
 
static int cmd64x_init_one(struct pci_dev *pdev, const struct pci_device_id *id)
{
        u32 class_rev;
 
        static const struct ata_port_info cmd_info[6] = {
                {       /* CMD 643 - no UDMA */
                        .sht = &cmd64x_sht,
                        .flags = ATA_FLAG_SLAVE_POSS,
                        .pio_mask = 0x1f,
                        .mwdma_mask = 0x07,
                        .port_ops = &cmd64x_port_ops
                },
                {       /* CMD 646 with broken UDMA */
                        .sht = &cmd64x_sht,
                        .flags = ATA_FLAG_SLAVE_POSS,
                        .pio_mask = 0x1f,
                        .mwdma_mask = 0x07,
                        .port_ops = &cmd64x_port_ops
                },
                {       /* CMD 646 with working UDMA */
                        .sht = &cmd64x_sht,
                        .flags = ATA_FLAG_SLAVE_POSS,
                        .pio_mask = 0x1f,
                        .mwdma_mask = 0x07,
                        .udma_mask = ATA_UDMA2,
                        .port_ops = &cmd64x_port_ops
                },
                {       /* CMD 646 rev 1  */
                        .sht = &cmd64x_sht,
                        .flags = ATA_FLAG_SLAVE_POSS,
                        .pio_mask = 0x1f,
                        .mwdma_mask = 0x07,
                        .port_ops = &cmd646r1_port_ops
                },
                {       /* CMD 648 */
                        .sht = &cmd64x_sht,
                        .flags = ATA_FLAG_SLAVE_POSS,
                        .pio_mask = 0x1f,
                        .mwdma_mask = 0x07,
                        .udma_mask = ATA_UDMA4,
                        .port_ops = &cmd648_port_ops
                },
                {       /* CMD 649 */
                        .sht = &cmd64x_sht,
                        .flags = ATA_FLAG_SLAVE_POSS,
                        .pio_mask = 0x1f,
                        .mwdma_mask = 0x07,
                        .udma_mask = ATA_UDMA5,
                        .port_ops = &cmd648_port_ops
                }
        };
        const struct ata_port_info *ppi[] = { &cmd_info[id->driver_data], NULL };
        u8 mrdmode;
 
        pci_read_config_dword(pdev, PCI_CLASS_REVISION, &class_rev);
        class_rev &= 0xFF;
 
        if (id->driver_data == 0)        /* 643 */
                ata_pci_clear_simplex(pdev);
 
        if (pdev->device == PCI_DEVICE_ID_CMD_646) {
                /* Does UDMA work ? */
                if (class_rev > 4)
                        ppi[0] = &cmd_info[2];
                /* Early rev with other problems ? */
                else if (class_rev == 1)
                        ppi[0] = &cmd_info[3];
        }
 
        pci_write_config_byte(pdev, PCI_LATENCY_TIMER, 64);
        pci_read_config_byte(pdev, MRDMODE, &mrdmode);
        mrdmode &= ~ 0x30;      /* IRQ set up */
        mrdmode |= 0x02;        /* Memory read line enable */
        pci_write_config_byte(pdev, MRDMODE, mrdmode);
 
        /* Force PIO 0 here.. */
 
        /* PPC specific fixup copied from old driver */
#ifdef CONFIG_PPC
        pci_write_config_byte(pdev, UDIDETCR0, 0xF0);
#endif
 
        return ata_pci_init_one(pdev, ppi);
}
 
#ifdef CONFIG_PM
static int cmd64x_reinit_one(struct pci_dev *pdev)
{
        u8 mrdmode;
        pci_write_config_byte(pdev, PCI_LATENCY_TIMER, 64);
        pci_read_config_byte(pdev, MRDMODE, &mrdmode);
        mrdmode &= ~ 0x30;      /* IRQ set up */
        mrdmode |= 0x02;        /* Memory read line enable */
        pci_write_config_byte(pdev, MRDMODE, mrdmode);
#ifdef CONFIG_PPC
        pci_write_config_byte(pdev, UDIDETCR0, 0xF0);
#endif
        return ata_pci_device_resume(pdev);
}
#endif
 
static const struct pci_device_id cmd64x[] = {
        { PCI_VDEVICE(CMD, PCI_DEVICE_ID_CMD_643), 0 },
        { PCI_VDEVICE(CMD, PCI_DEVICE_ID_CMD_646), 1 },
        { PCI_VDEVICE(CMD, PCI_DEVICE_ID_CMD_648), 4 },
        { PCI_VDEVICE(CMD, PCI_DEVICE_ID_CMD_649), 5 },
 
        { },
};
 
static struct pci_driver cmd64x_pci_driver = {
        .name           = DRV_NAME,
        .id_table       = cmd64x,
        .probe          = cmd64x_init_one,
        .remove         = ata_pci_remove_one,
#ifdef CONFIG_PM
        .suspend        = ata_pci_device_suspend,
        .resume         = cmd64x_reinit_one,
#endif
};
 
static int __init cmd64x_init(void)
{
        return pci_register_driver(&cmd64x_pci_driver);
}
 
static void __exit cmd64x_exit(void)
{
        pci_unregister_driver(&cmd64x_pci_driver);
}
 
MODULE_AUTHOR("Alan Cox");
MODULE_DESCRIPTION("low-level driver for CMD64x series PATA controllers");
MODULE_LICENSE("GPL");
MODULE_DEVICE_TABLE(pci, cmd64x);
MODULE_VERSION(DRV_VERSION);
 
module_init(cmd64x_init);
module_exit(cmd64x_exit);

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Subversion Repositories or1k_soc_on_altera_embedded_dev_kit

[/] [or1k_soc_on_altera_embedded_dev_kit/] [trunk/] [linux-2.6/] [linux-2.6.24/] [drivers/] [ata/] [pata_cmd64x.c] - Blame information for rev 3

Line No.	Rev	Author	Line
1	3	xianfeng	`/*`
2			`* pata_cmd64x.c - CMD64x PATA for new ATA layer`
3			`* (C) 2005 Red Hat Inc`
4			`* Alan Cox <alan@redhat.com>`
5			`*`
6			`* Based upon`
7			`* linux/drivers/ide/pci/cmd64x.c Version 1.30 Sept 10, 2002`
8			`*`
9			`* cmd64x.c: Enable interrupts at initialization time on Ultra/PCI machines.`
10			`* Note, this driver is not used at all on other systems because`
11			`* there the "BIOS" has done all of the following already.`
12			`* Due to massive hardware bugs, UltraDMA is only supported`
13			`* on the 646U2 and not on the 646U.`
14			`*`
15			`* Copyright (C) 1998 Eddie C. Dost (ecd@skynet.be)`
16			`* Copyright (C) 1998 David S. Miller (davem@redhat.com)`
17			`*`
18			`* Copyright (C) 1999-2002 Andre Hedrick <andre@linux-ide.org>`
19			`*`
20			`* TODO`
21			`* Testing work`
22			`*/`
23
24			`#include <linux/kernel.h>`
25			`#include <linux/module.h>`
26			`#include <linux/pci.h>`
27			`#include <linux/init.h>`
28			`#include <linux/blkdev.h>`
29			`#include <linux/delay.h>`
30			`#include <scsi/scsi_host.h>`
31			`#include <linux/libata.h>`
32
33			`#define DRV_NAME "pata_cmd64x"`
34			`#define DRV_VERSION "0.2.5"`
35
36			`/*`
37			`* CMD64x specific registers definition.`
38			`*/`
39
40			`enum {`
41			`CFR = 0x50,`
42			`CFR_INTR_CH0 = 0x02,`
43			`CNTRL = 0x51,`
44			`CNTRL_DIS_RA0 = 0x40,`
45			`CNTRL_DIS_RA1 = 0x80,`
46			`CNTRL_ENA_2ND = 0x08,`
47			`CMDTIM = 0x52,`
48			`ARTTIM0 = 0x53,`
49			`DRWTIM0 = 0x54,`
50			`ARTTIM1 = 0x55,`
51			`DRWTIM1 = 0x56,`
52			`ARTTIM23 = 0x57,`
53			`ARTTIM23_DIS_RA2 = 0x04,`
54			`ARTTIM23_DIS_RA3 = 0x08,`
55			`ARTTIM23_INTR_CH1 = 0x10,`
56			`ARTTIM2 = 0x57,`
57			`ARTTIM3 = 0x57,`
58			`DRWTIM23 = 0x58,`
59			`DRWTIM2 = 0x58,`
60			`BRST = 0x59,`
61			`DRWTIM3 = 0x5b,`
62			`BMIDECR0 = 0x70,`
63			`MRDMODE = 0x71,`
64			`MRDMODE_INTR_CH0 = 0x04,`
65			`MRDMODE_INTR_CH1 = 0x08,`
66			`MRDMODE_BLK_CH0 = 0x10,`
67			`MRDMODE_BLK_CH1 = 0x20,`
68			`BMIDESR0 = 0x72,`
69			`UDIDETCR0 = 0x73,`
70			`DTPR0 = 0x74,`
71			`BMIDECR1 = 0x78,`
72			`BMIDECSR = 0x79,`
73			`BMIDESR1 = 0x7A,`
74			`UDIDETCR1 = 0x7B,`
75			`DTPR1 = 0x7C`
76			`};`
77
78			`static int cmd648_cable_detect(struct ata_port *ap)`
79			`{`
80			`struct pci_dev *pdev = to_pci_dev(ap->host->dev);`
81			`u8 r;`
82
83			`/* Check cable detect bits */`
84			`pci_read_config_byte(pdev, BMIDECSR, &r);`
85			`if (r & (1 << ap->port_no))`
86			`return ATA_CBL_PATA80;`
87			`return ATA_CBL_PATA40;`
88			`}`
89
90			`/**`
91			`* cmd64x_set_piomode - set PIO and MWDMA timing`
92			`* @ap: ATA interface`
93			`* @adev: ATA device`
94			`* @mode: mode`
95			`*`
96			`* Called to do the PIO and MWDMA mode setup.`
97			`*/`
98
99			`static void cmd64x_set_timing(struct ata_port ap, struct ata_device adev, u8 mode)`
100			`{`
101			`struct pci_dev *pdev = to_pci_dev(ap->host->dev);`
102			`struct ata_timing t;`
103			`const unsigned long T = 1000000 / 33;`
104			`const u8 setup_data[] = { 0x40, 0x40, 0x40, 0x80, 0x00 };`
105
106			`u8 reg;`
107
108			`/* Port layout is not logical so use a table */`
109			`const u8 arttim_port[2][2] = {`
110			`{ ARTTIM0, ARTTIM1 },`
111			`{ ARTTIM23, ARTTIM23 }`
112			`};`
113			`const u8 drwtim_port[2][2] = {`
114			`{ DRWTIM0, DRWTIM1 },`
115			`{ DRWTIM2, DRWTIM3 }`
116			`};`
117
118			`int arttim = arttim_port[ap->port_no][adev->devno];`
119			`int drwtim = drwtim_port[ap->port_no][adev->devno];`
120
121			`/* ata_timing_compute is smart and will produce timings for MWDMA`
122			`that don't violate the drives PIO capabilities. */`
123			`if (ata_timing_compute(adev, mode, &t, T, 0) < 0) {`
124			`printk(KERN_ERR DRV_NAME ": mode computation failed.\n");`
125			`return;`
126			`}`
127			`if (ap->port_no) {`
128			`/* Slave has shared address setup */`
129			`struct ata_device *pair = ata_dev_pair(adev);`
130
131			`if (pair) {`
132			`struct ata_timing tp;`
133			`ata_timing_compute(pair, pair->pio_mode, &tp, T, 0);`
134			`ata_timing_merge(&t, &tp, &t, ATA_TIMING_SETUP);`
135			`}`
136			`}`
137
138			`printk(KERN_DEBUG DRV_NAME ": active %d recovery %d setup %d.\n",`
139			`t.active, t.recover, t.setup);`
140			`if (t.recover > 16) {`
141			`t.active += t.recover - 16;`
142			`t.recover = 16;`
143			`}`
144			`if (t.active > 16)`
145			`t.active = 16;`
146
147			`/* Now convert the clocks into values we can actually stuff into`
148			`the chip */`
149
150			`if (t.recover > 1)`
151			`t.recover--;`
152			`else`
153			`t.recover = 15;`
154
155			`if (t.setup > 4)`
156			`t.setup = 0xC0;`
157			`else`
158			`t.setup = setup_data[t.setup];`
159
160			`t.active &= 0x0F; /* 0 = 16 */`
161
162			`/* Load setup timing */`
163			`pci_read_config_byte(pdev, arttim, &reg);`
164			`reg &= 0x3F;`
165			`reg \|= t.setup;`
166			`pci_write_config_byte(pdev, arttim, reg);`
167
168			`/* Load active/recovery */`
169			`pci_write_config_byte(pdev, drwtim, (t.active << 4) \| t.recover);`
170			`}`
171
172			`/**`
173			`* cmd64x_set_piomode - set initial PIO mode data`
174			`* @ap: ATA interface`
175			`* @adev: ATA device`
176			`*`
177			`* Used when configuring the devices ot set the PIO timings. All the`
178			`* actual work is done by the PIO/MWDMA setting helper`
179			`*/`
180
181			`static void cmd64x_set_piomode(struct ata_port ap, struct ata_device adev)`
182			`{`
183			`cmd64x_set_timing(ap, adev, adev->pio_mode);`
184			`}`
185
186			`/**`
187			`* cmd64x_set_dmamode - set initial DMA mode data`
188			`* @ap: ATA interface`
189			`* @adev: ATA device`
190			`*`
191			`* Called to do the DMA mode setup.`
192			`*/`
193
194			`static void cmd64x_set_dmamode(struct ata_port ap, struct ata_device adev)`
195			`{`
196			`static const u8 udma_data[] = {`
197			`0x30, 0x20, 0x10, 0x20, 0x10, 0x00`
198			`};`
199
200			`struct pci_dev *pdev = to_pci_dev(ap->host->dev);`
201			`u8 regU, regD;`
202
203			`int pciU = UDIDETCR0 + 8 * ap->port_no;`
204			`int pciD = BMIDESR0 + 8 * ap->port_no;`
205			`int shift = 2 * adev->devno;`
206
207			`pci_read_config_byte(pdev, pciD, &regD);`
208			`pci_read_config_byte(pdev, pciU, &regU);`
209
210			`/* DMA bits off */`
211			`regD &= ~(0x20 << adev->devno);`
212			`/* DMA control bits */`
213			`regU &= ~(0x30 << shift);`
214			`/* DMA timing bits */`
215			`regU &= ~(0x05 << adev->devno);`
216
217			`if (adev->dma_mode >= XFER_UDMA_0) {`
218			`/* Merge the timing value */`
219			`regU \|= udma_data[adev->dma_mode - XFER_UDMA_0] << shift;`
220			`/* Merge the control bits */`
221			`regU \|= 1 << adev->devno; /* UDMA on */`
222			`if (adev->dma_mode > 2) /* 15nS timing */`
223			`regU \|= 4 << adev->devno;`
224			`} else {`
225			`regU &= ~ (1 << adev->devno); /* UDMA off */`
226			`cmd64x_set_timing(ap, adev, adev->dma_mode);`
227			`}`
228
229			`regD \|= 0x20 << adev->devno;`
230
231			`pci_write_config_byte(pdev, pciU, regU);`
232			`pci_write_config_byte(pdev, pciD, regD);`
233			`}`
234
235			`/**`
236			`* cmd648_dma_stop - DMA stop callback`
237			`* @qc: Command in progress`
238			`*`
239			`* DMA has completed.`
240			`*/`
241
242			`static void cmd648_bmdma_stop(struct ata_queued_cmd *qc)`
243			`{`
244			`struct ata_port *ap = qc->ap;`
245			`struct pci_dev *pdev = to_pci_dev(ap->host->dev);`
246			`u8 dma_intr;`
247			`int dma_mask = ap->port_no ? ARTTIM23_INTR_CH1 : CFR_INTR_CH0;`
248			`int dma_reg = ap->port_no ? ARTTIM2 : CFR;`
249
250			`ata_bmdma_stop(qc);`
251
252			`pci_read_config_byte(pdev, dma_reg, &dma_intr);`
253			`pci_write_config_byte(pdev, dma_reg, dma_intr \| dma_mask);`
254			`}`
255
256			`/**`
257			`* cmd646r1_dma_stop - DMA stop callback`
258			`* @qc: Command in progress`
259			`*`
260			`* Stub for now while investigating the r1 quirk in the old driver.`
261			`*/`
262
263			`static void cmd646r1_bmdma_stop(struct ata_queued_cmd *qc)`
264			`{`
265			`ata_bmdma_stop(qc);`
266			`}`
267
268			`static struct scsi_host_template cmd64x_sht = {`
269			`.module = THIS_MODULE,`
270			`.name = DRV_NAME,`
271			`.ioctl = ata_scsi_ioctl,`
272			`.queuecommand = ata_scsi_queuecmd,`
273			`.can_queue = ATA_DEF_QUEUE,`
274			`.this_id = ATA_SHT_THIS_ID,`
275			`.sg_tablesize = LIBATA_MAX_PRD,`
276			`.cmd_per_lun = ATA_SHT_CMD_PER_LUN,`
277			`.emulated = ATA_SHT_EMULATED,`
278			`.use_clustering = ATA_SHT_USE_CLUSTERING,`
279			`.proc_name = DRV_NAME,`
280			`.dma_boundary = ATA_DMA_BOUNDARY,`
281			`.slave_configure = ata_scsi_slave_config,`
282			`.slave_destroy = ata_scsi_slave_destroy,`
283			`.bios_param = ata_std_bios_param,`
284			`};`
285
286			`static struct ata_port_operations cmd64x_port_ops = {`
287			`.set_piomode = cmd64x_set_piomode,`
288			`.set_dmamode = cmd64x_set_dmamode,`
289			`.mode_filter = ata_pci_default_filter,`
290			`.tf_load = ata_tf_load,`
291			`.tf_read = ata_tf_read,`
292			`.check_status = ata_check_status,`
293			`.exec_command = ata_exec_command,`
294			`.dev_select = ata_std_dev_select,`
295
296			`.freeze = ata_bmdma_freeze,`
297			`.thaw = ata_bmdma_thaw,`
298			`.error_handler = ata_bmdma_error_handler,`
299			`.post_internal_cmd = ata_bmdma_post_internal_cmd,`
300			`.cable_detect = ata_cable_40wire,`
301
302			`.bmdma_setup = ata_bmdma_setup,`
303			`.bmdma_start = ata_bmdma_start,`
304			`.bmdma_stop = ata_bmdma_stop,`
305			`.bmdma_status = ata_bmdma_status,`
306
307			`.qc_prep = ata_qc_prep,`
308			`.qc_issue = ata_qc_issue_prot,`
309
310			`.data_xfer = ata_data_xfer,`
311
312			`.irq_handler = ata_interrupt,`
313			`.irq_clear = ata_bmdma_irq_clear,`
314			`.irq_on = ata_irq_on,`
315
316			`.port_start = ata_port_start,`
317			`};`
318
319			`static struct ata_port_operations cmd646r1_port_ops = {`
320			`.set_piomode = cmd64x_set_piomode,`
321			`.set_dmamode = cmd64x_set_dmamode,`
322			`.mode_filter = ata_pci_default_filter,`
323			`.tf_load = ata_tf_load,`
324			`.tf_read = ata_tf_read,`
325			`.check_status = ata_check_status,`
326			`.exec_command = ata_exec_command,`
327			`.dev_select = ata_std_dev_select,`
328
329			`.freeze = ata_bmdma_freeze,`
330			`.thaw = ata_bmdma_thaw,`
331			`.error_handler = ata_bmdma_error_handler,`
332			`.post_internal_cmd = ata_bmdma_post_internal_cmd,`
333			`.cable_detect = ata_cable_40wire,`
334
335			`.bmdma_setup = ata_bmdma_setup,`
336			`.bmdma_start = ata_bmdma_start,`
337			`.bmdma_stop = cmd646r1_bmdma_stop,`
338			`.bmdma_status = ata_bmdma_status,`
339
340			`.qc_prep = ata_qc_prep,`
341			`.qc_issue = ata_qc_issue_prot,`
342
343			`.data_xfer = ata_data_xfer,`
344
345			`.irq_handler = ata_interrupt,`
346			`.irq_clear = ata_bmdma_irq_clear,`
347			`.irq_on = ata_irq_on,`
348
349			`.port_start = ata_port_start,`
350			`};`
351
352			`static struct ata_port_operations cmd648_port_ops = {`
353			`.set_piomode = cmd64x_set_piomode,`
354			`.set_dmamode = cmd64x_set_dmamode,`
355			`.mode_filter = ata_pci_default_filter,`
356			`.tf_load = ata_tf_load,`
357			`.tf_read = ata_tf_read,`
358			`.check_status = ata_check_status,`
359			`.exec_command = ata_exec_command,`
360			`.dev_select = ata_std_dev_select,`
361
362			`.freeze = ata_bmdma_freeze,`
363			`.thaw = ata_bmdma_thaw,`
364			`.error_handler = ata_bmdma_error_handler,`
365			`.post_internal_cmd = ata_bmdma_post_internal_cmd,`
366			`.cable_detect = cmd648_cable_detect,`
367
368			`.bmdma_setup = ata_bmdma_setup,`
369			`.bmdma_start = ata_bmdma_start,`
370			`.bmdma_stop = cmd648_bmdma_stop,`
371			`.bmdma_status = ata_bmdma_status,`
372
373			`.qc_prep = ata_qc_prep,`
374			`.qc_issue = ata_qc_issue_prot,`
375
376			`.data_xfer = ata_data_xfer,`
377
378			`.irq_handler = ata_interrupt,`
379			`.irq_clear = ata_bmdma_irq_clear,`
380			`.irq_on = ata_irq_on,`
381
382			`.port_start = ata_port_start,`
383			`};`
384
385			`static int cmd64x_init_one(struct pci_dev pdev, const struct pci_device_id id)`
386			`{`
387			`u32 class_rev;`
388
389			`static const struct ata_port_info cmd_info[6] = {`
390			`{ /* CMD 643 - no UDMA */`
391			`.sht = &cmd64x_sht,`
392			`.flags = ATA_FLAG_SLAVE_POSS,`
393			`.pio_mask = 0x1f,`
394			`.mwdma_mask = 0x07,`
395			`.port_ops = &cmd64x_port_ops`
396			`},`
397			`{ /* CMD 646 with broken UDMA */`
398			`.sht = &cmd64x_sht,`
399			`.flags = ATA_FLAG_SLAVE_POSS,`
400			`.pio_mask = 0x1f,`
401			`.mwdma_mask = 0x07,`
402			`.port_ops = &cmd64x_port_ops`
403			`},`
404			`{ /* CMD 646 with working UDMA */`
405			`.sht = &cmd64x_sht,`
406			`.flags = ATA_FLAG_SLAVE_POSS,`
407			`.pio_mask = 0x1f,`
408			`.mwdma_mask = 0x07,`
409			`.udma_mask = ATA_UDMA2,`
410			`.port_ops = &cmd64x_port_ops`
411			`},`
412			`{ /* CMD 646 rev 1 */`
413			`.sht = &cmd64x_sht,`
414			`.flags = ATA_FLAG_SLAVE_POSS,`
415			`.pio_mask = 0x1f,`
416			`.mwdma_mask = 0x07,`
417			`.port_ops = &cmd646r1_port_ops`
418			`},`
419			`{ /* CMD 648 */`
420			`.sht = &cmd64x_sht,`
421			`.flags = ATA_FLAG_SLAVE_POSS,`
422			`.pio_mask = 0x1f,`
423			`.mwdma_mask = 0x07,`
424			`.udma_mask = ATA_UDMA4,`
425			`.port_ops = &cmd648_port_ops`
426			`},`
427			`{ /* CMD 649 */`
428			`.sht = &cmd64x_sht,`
429			`.flags = ATA_FLAG_SLAVE_POSS,`
430			`.pio_mask = 0x1f,`
431			`.mwdma_mask = 0x07,`
432			`.udma_mask = ATA_UDMA5,`
433			`.port_ops = &cmd648_port_ops`
434			`}`
435			`};`
436			`const struct ata_port_info *ppi[] = { &cmd_info[id->driver_data], NULL };`
437			`u8 mrdmode;`
438
439			`pci_read_config_dword(pdev, PCI_CLASS_REVISION, &class_rev);`
440			`class_rev &= 0xFF;`
441
442			`if (id->driver_data == 0) /* 643 */`
443			`ata_pci_clear_simplex(pdev);`
444
445			`if (pdev->device == PCI_DEVICE_ID_CMD_646) {`
446			`/* Does UDMA work ? */`
447			`if (class_rev > 4)`
448			`ppi[0] = &cmd_info[2];`
449			`/* Early rev with other problems ? */`
450			`else if (class_rev == 1)`
451			`ppi[0] = &cmd_info[3];`
452			`}`
453
454			`pci_write_config_byte(pdev, PCI_LATENCY_TIMER, 64);`
455			`pci_read_config_byte(pdev, MRDMODE, &mrdmode);`
456			`mrdmode &= ~ 0x30; /* IRQ set up */`
457			`mrdmode \|= 0x02; /* Memory read line enable */`
458			`pci_write_config_byte(pdev, MRDMODE, mrdmode);`
459
460			`/* Force PIO 0 here.. */`
461
462			`/* PPC specific fixup copied from old driver */`
463			`#ifdef CONFIG_PPC`
464			`pci_write_config_byte(pdev, UDIDETCR0, 0xF0);`
465			`#endif`
466
467			`return ata_pci_init_one(pdev, ppi);`
468			`}`
469
470			`#ifdef CONFIG_PM`
471			`static int cmd64x_reinit_one(struct pci_dev *pdev)`
472			`{`
473			`u8 mrdmode;`
474			`pci_write_config_byte(pdev, PCI_LATENCY_TIMER, 64);`
475			`pci_read_config_byte(pdev, MRDMODE, &mrdmode);`
476			`mrdmode &= ~ 0x30; /* IRQ set up */`
477			`mrdmode \|= 0x02; /* Memory read line enable */`
478			`pci_write_config_byte(pdev, MRDMODE, mrdmode);`
479			`#ifdef CONFIG_PPC`
480			`pci_write_config_byte(pdev, UDIDETCR0, 0xF0);`
481			`#endif`
482			`return ata_pci_device_resume(pdev);`
483			`}`
484			`#endif`
485
486			`static const struct pci_device_id cmd64x[] = {`
487			`{ PCI_VDEVICE(CMD, PCI_DEVICE_ID_CMD_643), 0 },`
488			`{ PCI_VDEVICE(CMD, PCI_DEVICE_ID_CMD_646), 1 },`
489			`{ PCI_VDEVICE(CMD, PCI_DEVICE_ID_CMD_648), 4 },`
490			`{ PCI_VDEVICE(CMD, PCI_DEVICE_ID_CMD_649), 5 },`
491
492			`{ },`
493			`};`
494
495			`static struct pci_driver cmd64x_pci_driver = {`
496			`.name = DRV_NAME,`
497			`.id_table = cmd64x,`
498			`.probe = cmd64x_init_one,`
499			`.remove = ata_pci_remove_one,`
500			`#ifdef CONFIG_PM`
501			`.suspend = ata_pci_device_suspend,`
502			`.resume = cmd64x_reinit_one,`
503			`#endif`
504			`};`
505
506			`static int __init cmd64x_init(void)`
507			`{`
508			`return pci_register_driver(&cmd64x_pci_driver);`
509			`}`
510
511			`static void __exit cmd64x_exit(void)`
512			`{`
513			`pci_unregister_driver(&cmd64x_pci_driver);`
514			`}`
515
516			`MODULE_AUTHOR("Alan Cox");`
517			`MODULE_DESCRIPTION("low-level driver for CMD64x series PATA controllers");`
518			`MODULE_LICENSE("GPL");`
519			`MODULE_DEVICE_TABLE(pci, cmd64x);`
520			`MODULE_VERSION(DRV_VERSION);`
521
522			`module_init(cmd64x_init);`
523			`module_exit(cmd64x_exit);`