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[/] [or1k_soc_on_altera_embedded_dev_kit/] [trunk/] [linux-2.6/] [linux-2.6.24/] [include/] [asm-m68knommu/] [m5249sim.h] - Blame information for rev 3

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/****************************************************************************/
 
/*
 *      m5249sim.h -- ColdFire 5249 System Integration Module support.
 *
 *      (C) Copyright 2002, Greg Ungerer (gerg@snapgear.com)
 */
 
/****************************************************************************/
#ifndef m5249sim_h
#define m5249sim_h
/****************************************************************************/
 
/*
 *      Define the 5249 SIM register set addresses.
 */
#define MCFSIM_RSR              0x00            /* Reset Status reg (r/w) */
#define MCFSIM_SYPCR            0x01            /* System Protection reg (r/w)*/
#define MCFSIM_SWIVR            0x02            /* SW Watchdog intr reg (r/w) */
#define MCFSIM_SWSR             0x03            /* SW Watchdog service (r/w) */
#define MCFSIM_PAR              0x04            /* Pin Assignment reg (r/w) */
#define MCFSIM_IRQPAR           0x06            /* Interrupt Assignment reg (r/w) */
#define MCFSIM_MPARK            0x0C            /* BUS Master Control Reg*/
#define MCFSIM_IPR              0x40            /* Interrupt Pend reg (r/w) */
#define MCFSIM_IMR              0x44            /* Interrupt Mask reg (r/w) */
#define MCFSIM_AVR              0x4b            /* Autovector Ctrl reg (r/w) */
#define MCFSIM_ICR0             0x4c            /* Intr Ctrl reg 0 (r/w) */
#define MCFSIM_ICR1             0x4d            /* Intr Ctrl reg 1 (r/w) */
#define MCFSIM_ICR2             0x4e            /* Intr Ctrl reg 2 (r/w) */
#define MCFSIM_ICR3             0x4f            /* Intr Ctrl reg 3 (r/w) */
#define MCFSIM_ICR4             0x50            /* Intr Ctrl reg 4 (r/w) */
#define MCFSIM_ICR5             0x51            /* Intr Ctrl reg 5 (r/w) */
#define MCFSIM_ICR6             0x52            /* Intr Ctrl reg 6 (r/w) */
#define MCFSIM_ICR7             0x53            /* Intr Ctrl reg 7 (r/w) */
#define MCFSIM_ICR8             0x54            /* Intr Ctrl reg 8 (r/w) */
#define MCFSIM_ICR9             0x55            /* Intr Ctrl reg 9 (r/w) */
#define MCFSIM_ICR10            0x56            /* Intr Ctrl reg 10 (r/w) */
#define MCFSIM_ICR11            0x57            /* Intr Ctrl reg 11 (r/w) */
 
#define MCFSIM_CSAR0            0x80            /* CS 0 Address 0 reg (r/w) */
#define MCFSIM_CSMR0            0x84            /* CS 0 Mask 0 reg (r/w) */
#define MCFSIM_CSCR0            0x8a            /* CS 0 Control reg (r/w) */
#define MCFSIM_CSAR1            0x8c            /* CS 1 Address reg (r/w) */
#define MCFSIM_CSMR1            0x90            /* CS 1 Mask reg (r/w) */
#define MCFSIM_CSCR1            0x96            /* CS 1 Control reg (r/w) */
#define MCFSIM_CSAR2            0x98            /* CS 2 Adress reg (r/w) */
#define MCFSIM_CSMR2            0x9c            /* CS 2 Mask reg (r/w) */
#define MCFSIM_CSCR2            0xa2            /* CS 2 Control reg (r/w) */
#define MCFSIM_CSAR3            0xa4            /* CS 3 Adress reg (r/w) */
#define MCFSIM_CSMR3            0xa8            /* CS 3 Mask reg (r/w) */
#define MCFSIM_CSCR3            0xae            /* CS 3 Control reg (r/w) */
 
#define MCFSIM_DCR              0x100           /* DRAM Control reg (r/w) */
#define MCFSIM_DACR0            0x108           /* DRAM 0 Addr and Ctrl (r/w) */
#define MCFSIM_DMR0             0x10c           /* DRAM 0 Mask reg (r/w) */
#define MCFSIM_DACR1            0x110           /* DRAM 1 Addr and Ctrl (r/w) */
#define MCFSIM_DMR1             0x114           /* DRAM 1 Mask reg (r/w) */
 
 
/*
 *      Some symbol defines for the above...
 */
#define MCFSIM_SWDICR           MCFSIM_ICR0     /* Watchdog timer ICR */
#define MCFSIM_TIMER1ICR        MCFSIM_ICR1     /* Timer 1 ICR */
#define MCFSIM_TIMER2ICR        MCFSIM_ICR2     /* Timer 2 ICR */
#define MCFSIM_UART1ICR         MCFSIM_ICR4     /* UART 1 ICR */
#define MCFSIM_UART2ICR         MCFSIM_ICR5     /* UART 2 ICR */
#define MCFSIM_DMA0ICR          MCFSIM_ICR6     /* DMA 0 ICR */
#define MCFSIM_DMA1ICR          MCFSIM_ICR7     /* DMA 1 ICR */
#define MCFSIM_DMA2ICR          MCFSIM_ICR8     /* DMA 2 ICR */
#define MCFSIM_DMA3ICR          MCFSIM_ICR9     /* DMA 3 ICR */
 
/*
 *      General purpose IO registers (in MBAR2).
 */
#define MCFSIM2_GPIOREAD        0x0             /* GPIO read values */
#define MCFSIM2_GPIOWRITE       0x4             /* GPIO write values */
#define MCFSIM2_GPIOENABLE      0x8             /* GPIO enabled */
#define MCFSIM2_GPIOFUNC        0xc             /* GPIO function */
#define MCFSIM2_GPIO1READ       0xb0            /* GPIO1 read values */
#define MCFSIM2_GPIO1WRITE      0xb4            /* GPIO1 write values */
#define MCFSIM2_GPIO1ENABLE     0xb8            /* GPIO1 enabled */
#define MCFSIM2_GPIO1FUNC       0xbc            /* GPIO1 function */
 
#define MCFSIM2_GPIOINTSTAT     0xc0            /* GPIO interrupt status */
#define MCFSIM2_GPIOINTCLEAR    0xc0            /* GPIO interrupt clear */
#define MCFSIM2_GPIOINTENABLE   0xc4            /* GPIO interrupt enable */
 
#define MCFSIM2_INTLEVEL1       0x140           /* Interrupt level reg 1 */
#define MCFSIM2_INTLEVEL2       0x144           /* Interrupt level reg 2 */
#define MCFSIM2_INTLEVEL3       0x148           /* Interrupt level reg 3 */
#define MCFSIM2_INTLEVEL4       0x14c           /* Interrupt level reg 4 */
#define MCFSIM2_INTLEVEL5       0x150           /* Interrupt level reg 5 */
#define MCFSIM2_INTLEVEL6       0x154           /* Interrupt level reg 6 */
#define MCFSIM2_INTLEVEL7       0x158           /* Interrupt level reg 7 */
#define MCFSIM2_INTLEVEL8       0x15c           /* Interrupt level reg 8 */
 
#define MCFSIM2_DMAROUTE        0x188           /* DMA routing */
 
#define MCFSIM2_IDECONFIG1      0x18c           /* IDEconfig1 */
#define MCFSIM2_IDECONFIG2      0x190           /* IDEconfig2 */
 
 
/*
 *      Macro to set IMR register. It is 32 bits on the 5249.
 */
#define MCFSIM_IMR_MASKALL      0x7fffe         /* All SIM intr sources */
 
#define mcf_getimr()            \
        *((volatile unsigned long *) (MCF_MBAR + MCFSIM_IMR))
 
#define mcf_setimr(imr)         \
        *((volatile unsigned long *) (MCF_MBAR + MCFSIM_IMR)) = (imr);
 
#define mcf_getipr()            \
        *((volatile unsigned long *) (MCF_MBAR + MCFSIM_IPR))
 
/****************************************************************************/
 
#ifdef __ASSEMBLER__
 
/*
 *      The M5249C3 board needs a little help getting all its SIM devices
 *      initialized at kernel start time. dBUG doesn't set much up, so
 *      we need to do it manually.
 */
.macro m5249c3_setup
        /*
         *      Set MBAR1 and MBAR2, just incase they are not set.
         */
        movel   #0x10000001,%a0
        movec   %a0,%MBAR                       /* map MBAR region */
        subql   #1,%a0                          /* get MBAR address in a0 */
 
        movel   #0x80000001,%a1
        movec   %a1,#3086                       /* map MBAR2 region */
        subql   #1,%a1                          /* get MBAR2 address in a1 */
 
        /*
         *      Move secondary interrupts to base at 128.
         */
        moveb   #0x80,%d0
        moveb   %d0,0x16b(%a1)                  /* interrupt base register */
 
        /*
         *      Work around broken CSMR0/DRAM vector problem.
         */
        movel   #0x001F0021,%d0                 /* disable C/I bit */
        movel   %d0,0x84(%a0)                   /* set CSMR0 */
 
        /*
         *      Disable the PLL firstly. (Who knows what state it is
         *      in here!).
         */
        movel   0x180(%a1),%d0                  /* get current PLL value */
        andl    #0xfffffffe,%d0                 /* PLL bypass first */
        movel   %d0,0x180(%a1)                  /* set PLL register */
        nop
 
#if CONFIG_CLOCK_FREQ == 140000000
        /*
         *      Set initial clock frequency. This assumes M5249C3 board
         *      is fitted with 11.2896MHz crystal. It will program the
         *      PLL for 140MHz. Lets go fast :-)
         */
        movel   #0x125a40f0,%d0                 /* set for 140MHz */
        movel   %d0,0x180(%a1)                  /* set PLL register */
        orl     #0x1,%d0
        movel   %d0,0x180(%a1)                  /* set PLL register */
#endif
 
        /*
         *      Setup CS1 for ethernet controller.
         *      (Setup as per M5249C3 doco).
         */
        movel  #0xe0000000,%d0                  /* CS1 mapped at 0xe0000000 */
        movel  %d0,0x8c(%a0)
        movel  #0x001f0021,%d0                  /* CS1 size of 1Mb */
        movel  %d0,0x90(%a0)
        movew  #0x0080,%d0                      /* CS1 = 16bit port, AA */
        movew  %d0,0x96(%a0)
 
        /*
         *      Setup CS2 for IDE interface.
         */
        movel   #0x50000000,%d0                 /* CS2 mapped at 0x50000000 */
        movel   %d0,0x98(%a0)
        movel   #0x001f0001,%d0                 /* CS2 size of 1MB */
        movel   %d0,0x9c(%a0)
        movew   #0x0080,%d0                     /* CS2 = 16bit, TA */
        movew   %d0,0xa2(%a0)
 
        movel   #0x00107000,%d0                 /* IDEconfig1 */
        movel   %d0,0x18c(%a1)
        movel   #0x000c0400,%d0                 /* IDEconfig2 */
        movel   %d0,0x190(%a1)
 
        movel   #0x00080000,%d0                 /* GPIO19, IDE reset bit */
        orl     %d0,0xc(%a1)                    /* function GPIO19 */
        orl     %d0,0x8(%a1)                    /* enable GPIO19 as output */
        orl     %d0,0x4(%a1)                    /* de-assert IDE reset */
.endm
 
#define PLATFORM_SETUP  m5249c3_setup
 
#endif /* __ASSEMBLER__ */
 
/****************************************************************************/
#endif  /* m5249sim_h */

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Subversion Repositories or1k_soc_on_altera_embedded_dev_kit

[/] [or1k_soc_on_altera_embedded_dev_kit/] [trunk/] [linux-2.6/] [linux-2.6.24/] [include/] [asm-m68knommu/] [m5249sim.h] - Blame information for rev 3

Line No.	Rev	Author	Line
1	3	xianfeng	`/****************************************************************************/`
2
3			`/*`
4			`* m5249sim.h -- ColdFire 5249 System Integration Module support.`
5			`*`
6			`* (C) Copyright 2002, Greg Ungerer (gerg@snapgear.com)`
7			`*/`
8
9			`/****************************************************************************/`
10			`#ifndef m5249sim_h`
11			`#define m5249sim_h`
12			`/****************************************************************************/`
13
14			`/*`
15			`* Define the 5249 SIM register set addresses.`
16			`*/`
17			`#define MCFSIM_RSR 0x00 /* Reset Status reg (r/w) */`
18			`#define MCFSIM_SYPCR 0x01 /* System Protection reg (r/w)*/`
19			`#define MCFSIM_SWIVR 0x02 /* SW Watchdog intr reg (r/w) */`
20			`#define MCFSIM_SWSR 0x03 /* SW Watchdog service (r/w) */`
21			`#define MCFSIM_PAR 0x04 /* Pin Assignment reg (r/w) */`
22			`#define MCFSIM_IRQPAR 0x06 /* Interrupt Assignment reg (r/w) */`
23			`#define MCFSIM_MPARK 0x0C /* BUS Master Control Reg*/`
24			`#define MCFSIM_IPR 0x40 /* Interrupt Pend reg (r/w) */`
25			`#define MCFSIM_IMR 0x44 /* Interrupt Mask reg (r/w) */`
26			`#define MCFSIM_AVR 0x4b /* Autovector Ctrl reg (r/w) */`
27			`#define MCFSIM_ICR0 0x4c /* Intr Ctrl reg 0 (r/w) */`
28			`#define MCFSIM_ICR1 0x4d /* Intr Ctrl reg 1 (r/w) */`
29			`#define MCFSIM_ICR2 0x4e /* Intr Ctrl reg 2 (r/w) */`
30			`#define MCFSIM_ICR3 0x4f /* Intr Ctrl reg 3 (r/w) */`
31			`#define MCFSIM_ICR4 0x50 /* Intr Ctrl reg 4 (r/w) */`
32			`#define MCFSIM_ICR5 0x51 /* Intr Ctrl reg 5 (r/w) */`
33			`#define MCFSIM_ICR6 0x52 /* Intr Ctrl reg 6 (r/w) */`
34			`#define MCFSIM_ICR7 0x53 /* Intr Ctrl reg 7 (r/w) */`
35			`#define MCFSIM_ICR8 0x54 /* Intr Ctrl reg 8 (r/w) */`
36			`#define MCFSIM_ICR9 0x55 /* Intr Ctrl reg 9 (r/w) */`
37			`#define MCFSIM_ICR10 0x56 /* Intr Ctrl reg 10 (r/w) */`
38			`#define MCFSIM_ICR11 0x57 /* Intr Ctrl reg 11 (r/w) */`
39
40			`#define MCFSIM_CSAR0 0x80 /* CS 0 Address 0 reg (r/w) */`
41			`#define MCFSIM_CSMR0 0x84 /* CS 0 Mask 0 reg (r/w) */`
42			`#define MCFSIM_CSCR0 0x8a /* CS 0 Control reg (r/w) */`
43			`#define MCFSIM_CSAR1 0x8c /* CS 1 Address reg (r/w) */`
44			`#define MCFSIM_CSMR1 0x90 /* CS 1 Mask reg (r/w) */`
45			`#define MCFSIM_CSCR1 0x96 /* CS 1 Control reg (r/w) */`
46			`#define MCFSIM_CSAR2 0x98 /* CS 2 Adress reg (r/w) */`
47			`#define MCFSIM_CSMR2 0x9c /* CS 2 Mask reg (r/w) */`
48			`#define MCFSIM_CSCR2 0xa2 /* CS 2 Control reg (r/w) */`
49			`#define MCFSIM_CSAR3 0xa4 /* CS 3 Adress reg (r/w) */`
50			`#define MCFSIM_CSMR3 0xa8 /* CS 3 Mask reg (r/w) */`
51			`#define MCFSIM_CSCR3 0xae /* CS 3 Control reg (r/w) */`
52
53			`#define MCFSIM_DCR 0x100 /* DRAM Control reg (r/w) */`
54			`#define MCFSIM_DACR0 0x108 /* DRAM 0 Addr and Ctrl (r/w) */`
55			`#define MCFSIM_DMR0 0x10c /* DRAM 0 Mask reg (r/w) */`
56			`#define MCFSIM_DACR1 0x110 /* DRAM 1 Addr and Ctrl (r/w) */`
57			`#define MCFSIM_DMR1 0x114 /* DRAM 1 Mask reg (r/w) */`
58
59
60			`/*`
61			`* Some symbol defines for the above...`
62			`*/`
63			`#define MCFSIM_SWDICR MCFSIM_ICR0 /* Watchdog timer ICR */`
64			`#define MCFSIM_TIMER1ICR MCFSIM_ICR1 /* Timer 1 ICR */`
65			`#define MCFSIM_TIMER2ICR MCFSIM_ICR2 /* Timer 2 ICR */`
66			`#define MCFSIM_UART1ICR MCFSIM_ICR4 /* UART 1 ICR */`
67			`#define MCFSIM_UART2ICR MCFSIM_ICR5 /* UART 2 ICR */`
68			`#define MCFSIM_DMA0ICR MCFSIM_ICR6 /* DMA 0 ICR */`
69			`#define MCFSIM_DMA1ICR MCFSIM_ICR7 /* DMA 1 ICR */`
70			`#define MCFSIM_DMA2ICR MCFSIM_ICR8 /* DMA 2 ICR */`
71			`#define MCFSIM_DMA3ICR MCFSIM_ICR9 /* DMA 3 ICR */`
72
73			`/*`
74			`* General purpose IO registers (in MBAR2).`
75			`*/`
76			`#define MCFSIM2_GPIOREAD 0x0 /* GPIO read values */`
77			`#define MCFSIM2_GPIOWRITE 0x4 /* GPIO write values */`
78			`#define MCFSIM2_GPIOENABLE 0x8 /* GPIO enabled */`
79			`#define MCFSIM2_GPIOFUNC 0xc /* GPIO function */`
80			`#define MCFSIM2_GPIO1READ 0xb0 /* GPIO1 read values */`
81			`#define MCFSIM2_GPIO1WRITE 0xb4 /* GPIO1 write values */`
82			`#define MCFSIM2_GPIO1ENABLE 0xb8 /* GPIO1 enabled */`
83			`#define MCFSIM2_GPIO1FUNC 0xbc /* GPIO1 function */`
84
85			`#define MCFSIM2_GPIOINTSTAT 0xc0 /* GPIO interrupt status */`
86			`#define MCFSIM2_GPIOINTCLEAR 0xc0 /* GPIO interrupt clear */`
87			`#define MCFSIM2_GPIOINTENABLE 0xc4 /* GPIO interrupt enable */`
88
89			`#define MCFSIM2_INTLEVEL1 0x140 /* Interrupt level reg 1 */`
90			`#define MCFSIM2_INTLEVEL2 0x144 /* Interrupt level reg 2 */`
91			`#define MCFSIM2_INTLEVEL3 0x148 /* Interrupt level reg 3 */`
92			`#define MCFSIM2_INTLEVEL4 0x14c /* Interrupt level reg 4 */`
93			`#define MCFSIM2_INTLEVEL5 0x150 /* Interrupt level reg 5 */`
94			`#define MCFSIM2_INTLEVEL6 0x154 /* Interrupt level reg 6 */`
95			`#define MCFSIM2_INTLEVEL7 0x158 /* Interrupt level reg 7 */`
96			`#define MCFSIM2_INTLEVEL8 0x15c /* Interrupt level reg 8 */`
97
98			`#define MCFSIM2_DMAROUTE 0x188 /* DMA routing */`
99
100			`#define MCFSIM2_IDECONFIG1 0x18c /* IDEconfig1 */`
101			`#define MCFSIM2_IDECONFIG2 0x190 /* IDEconfig2 */`
102
103
104			`/*`
105			`* Macro to set IMR register. It is 32 bits on the 5249.`
106			`*/`
107			`#define MCFSIM_IMR_MASKALL 0x7fffe /* All SIM intr sources */`
108
109			`#define mcf_getimr() \`
110			`((volatile unsigned long ) (MCF_MBAR + MCFSIM_IMR))`
111
112			`#define mcf_setimr(imr) \`
113			`((volatile unsigned long ) (MCF_MBAR + MCFSIM_IMR)) = (imr);`
114
115			`#define mcf_getipr() \`
116			`((volatile unsigned long ) (MCF_MBAR + MCFSIM_IPR))`
117
118			`/****************************************************************************/`
119
120			`#ifdef __ASSEMBLER__`
121
122			`/*`
123			`* The M5249C3 board needs a little help getting all its SIM devices`
124			`* initialized at kernel start time. dBUG doesn't set much up, so`
125			`* we need to do it manually.`
126			`*/`
127			`.macro m5249c3_setup`
128			`/*`
129			`* Set MBAR1 and MBAR2, just incase they are not set.`
130			`*/`
131			`movel #0x10000001,%a0`
132			`movec %a0,%MBAR /* map MBAR region */`
133			`subql #1,%a0 /* get MBAR address in a0 */`
134
135			`movel #0x80000001,%a1`
136			`movec %a1,#3086 /* map MBAR2 region */`
137			`subql #1,%a1 /* get MBAR2 address in a1 */`
138
139			`/*`
140			`* Move secondary interrupts to base at 128.`
141			`*/`
142			`moveb #0x80,%d0`
143			`moveb %d0,0x16b(%a1) /* interrupt base register */`
144
145			`/*`
146			`* Work around broken CSMR0/DRAM vector problem.`
147			`*/`
148			`movel #0x001F0021,%d0 /* disable C/I bit */`
149			`movel %d0,0x84(%a0) /* set CSMR0 */`
150
151			`/*`
152			`* Disable the PLL firstly. (Who knows what state it is`
153			`* in here!).`
154			`*/`
155			`movel 0x180(%a1),%d0 /* get current PLL value */`
156			`andl #0xfffffffe,%d0 /* PLL bypass first */`
157			`movel %d0,0x180(%a1) /* set PLL register */`
158			`nop`
159
160			`#if CONFIG_CLOCK_FREQ == 140000000`
161			`/*`
162			`* Set initial clock frequency. This assumes M5249C3 board`
163			`* is fitted with 11.2896MHz crystal. It will program the`
164			`* PLL for 140MHz. Lets go fast :-)`
165			`*/`
166			`movel #0x125a40f0,%d0 /* set for 140MHz */`
167			`movel %d0,0x180(%a1) /* set PLL register */`
168			`orl #0x1,%d0`
169			`movel %d0,0x180(%a1) /* set PLL register */`
170			`#endif`
171
172			`/*`
173			`* Setup CS1 for ethernet controller.`
174			`* (Setup as per M5249C3 doco).`
175			`*/`
176			`movel #0xe0000000,%d0 /* CS1 mapped at 0xe0000000 */`
177			`movel %d0,0x8c(%a0)`
178			`movel #0x001f0021,%d0 /* CS1 size of 1Mb */`
179			`movel %d0,0x90(%a0)`
180			`movew #0x0080,%d0 /* CS1 = 16bit port, AA */`
181			`movew %d0,0x96(%a0)`
182
183			`/*`
184			`* Setup CS2 for IDE interface.`
185			`*/`
186			`movel #0x50000000,%d0 /* CS2 mapped at 0x50000000 */`
187			`movel %d0,0x98(%a0)`
188			`movel #0x001f0001,%d0 /* CS2 size of 1MB */`
189			`movel %d0,0x9c(%a0)`
190			`movew #0x0080,%d0 /* CS2 = 16bit, TA */`
191			`movew %d0,0xa2(%a0)`
192
193			`movel #0x00107000,%d0 /* IDEconfig1 */`
194			`movel %d0,0x18c(%a1)`
195			`movel #0x000c0400,%d0 /* IDEconfig2 */`
196			`movel %d0,0x190(%a1)`
197
198			`movel #0x00080000,%d0 /* GPIO19, IDE reset bit */`
199			`orl %d0,0xc(%a1) /* function GPIO19 */`
200			`orl %d0,0x8(%a1) /* enable GPIO19 as output */`
201			`orl %d0,0x4(%a1) /* de-assert IDE reset */`
202			`.endm`
203
204			`#define PLATFORM_SETUP m5249c3_setup`
205
206			`#endif /* __ASSEMBLER__ */`
207
208			`/****************************************************************************/`
209			`#endif /* m5249sim_h */`