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[/] [or1k_soc_on_altera_embedded_dev_kit/] [trunk/] [linux-2.6/] [linux-2.6.24/] [include/] [asm-or32/] [cache.h] - Blame information for rev 7

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Line No. Rev Author Line
1 7 xianfeng
#ifdef __KERNEL__
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#ifndef _OR32_CACHE_H
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#define _OR32_CACHE_H
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#include <asm/processor.h>
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#if CONFIG_OR32_DC_LINE!=CONFIG_OR32_IC_LINE
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#  warning "insn cachline is different than data cacheline" 
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#endif
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#define L1_CACHE_BYTES CONFIG_OR32_DC_LINE
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#if L1_CACHE_BYTES==16
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#  define L1_CACHE_SHIFT     4
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#elif L1_CACHE_BYTES==32
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#  define L1_CACHE_SHIFT     5
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#else
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#  error "please define L1_CACHE_SHIFT, and if neccessery correct L1_CACHE_SHIFT_MAX"
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#endif
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/* Maximum cache line this arch supports */
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#  define L1_CACHE_SHIFT_MAX 5
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#endif
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#endif

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