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xianfeng |
#ifndef _OR32_MC2_H
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2 |
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#define _OR32_MC2_H
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3 |
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4 |
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#if CONFIG_OR32_MC_VERSION==2
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#ifdef CONFIG_OR32_HIGHLAND_DEFAULT_MEMORY_TIMINGS
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//# define CONFIG_OR32_FLASH_INTEL_J3
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# define CONFIG_OR32_FLASH_BENDER_2
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# define CONFIG_OR32_SDRAM_MICRON_MT48LC16M16A2_TC_75D
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#elif CONFIG_OR32_GENERIC_MEMORY_TIMINGS
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/* FLASH timings: worst cases in ns, from data sheets */
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# define FLASH_WA_TIME CONFIG_OR32_FLASH_WA_TIME
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# define FLASH_WE_DELAY CONFIG_OR32_FLASH_WE_DELAY
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# define FLASH_WH_TIME CONFIG_OR32_FLASH_WH_TIME
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# define FLASH_RA_TIME CONFIG_OR32_FLASH_RA_TIME
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# define FLASH_PRA_TIME CONFIG_OR32_FLASH_PRA_TIME
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# define FLASH_RT_TIME CONFIG_OR32_FLASH_RT_TIME
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/* SDRAM timings: worst cases in ns, from data sheets */
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# define SDRAM_tRCD CONFIG_OR32_SDRAM_tRCD
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# define SDRAM_tWR CONFIG_OR32_SDRAM_tWR
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# define SDRAM_tRC CONFIG_OR32_SDRAM_tRC
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# define SDRAM_tRFC CONFIG_OR32_SDRAM_tRFC
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23 |
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# define SDRAM_tRAS CONFIG_OR32_SDRAM_tRAS
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24 |
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# define SDRAM_tRP CONFIG_OR32_SDRAM_tRP
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25 |
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# define SDRAM_tRRD CONFIG_OR32_SDRAM_tRRD
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26 |
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# define SDRAM_tREF CONFIG_OR32_SDRAM_tREF
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27 |
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#else
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28 |
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# error "no timings defined"
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29 |
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#endif
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#endif
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31 |
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32 |
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/* ----------------------------------------------------[ memory timings ]--- */
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33 |
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/* FLASH timings: worst cases in ns, from data sheets */
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#ifdef CONFIG_OR32_FLASH_INTEL_J3
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# define FLASH_WA_TIME 150+10 /* write access*/
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# define FLASH_WE_DELAY 0 /* write enable*/
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38 |
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# define FLASH_WH_TIME 0 /* write hold */
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# define FLASH_RA_TIME 120+10 /* read access*/
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# define FLASH_PRA_TIME 25 /* page read access time */
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# define FLASH_RT_TIME 15 /* read turnaround time */
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#endif /* CONFIG_OR32_FLASH_INTEL_J3 */
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#ifdef CONFIG_OR32_FLASH_BENDER_2
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# define FLASH_WA_TIME 50 /* write access*/
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# define FLASH_WE_DELAY 0 /* write enable*/
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# define FLASH_WH_TIME 0 /* write hold */
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48 |
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# define FLASH_RA_TIME 95 /* read access*/
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# define FLASH_PRA_TIME 25 /* page read access time */
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50 |
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# define FLASH_RT_TIME 24 /* read turnaround time */
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#endif /* CONFIG_OR32_FLASH_BENDER_2 */
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/* SDRAM timings: worst cases in ns, from data sheets */
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#ifdef CONFIG_OR32_SDRAM_MICRON_MT48LC16M16A2_TC_75D
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# define SDRAM_tRCD 20
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# define SDRAM_tWR 15 /* ?? */
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# define SDRAM_tRC 66
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# define SDRAM_tRFC 66 /* sometimes the same as tRC */
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# define SDRAM_tRAS 44 /* use the worst case minimal value */
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60 |
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# define SDRAM_tRP 20
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# define SDRAM_tRRD 15
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# define SDRAM_tREF ((64000000/8192)+1)
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#endif /* CONFIG_OR32_SDRAM_MICRON_MT48LC16M16A2_TC_75D */
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#ifdef CONFIG_OR32_SDRAM_BENDER_2
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# define SDRAM_tRCD 23
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# define SDRAM_tWR 20
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# define SDRAM_tRC 60
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# define SDRAM_tRFC 60 /* sometimes the same as tRC */
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# define SDRAM_tRAS 50 /* use the worst case minimal value */
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# define SDRAM_tRP 23
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# define SDRAM_tRRD 15
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# define SDRAM_tREF ((64000000/8192)+1)
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#endif /* CONFIG_OR32_SDRAM_BENDER_2 */
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/* -------------------------------------------------------[ calculation ]--- */
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#if CONFIG_OR32_MC_VERSION==1
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/* Memory controller initialize values */
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# if CONFIG_OR32_SYS_CLK==25
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# define MC_CSR_VAL 0x0B000300
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# define MC_MASK_VAL 0x000003f0
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# define FLASH_TMS_VAL 0x00000103
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84 |
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# define SDRAM_BASE_ADD 0x00000000
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# define SDRAM_TMS_VAL 0x19220057
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# elif CONFIG_OR32_SYS_CLK==48
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# warning Timings for 48Mhz are taken the same as for 25MHz
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88 |
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# define MC_CSR_VAL 0x0B000300
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# define MC_MASK_VAL 0x000003f0
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# define FLASH_TMS_VAL 0x00000103
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# define SDRAM_BASE_ADD 0x00000000
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# define SDRAM_TMS_VAL 0x19220057
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93 |
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# elif CONFIG_OR32_SYS_CLK==100
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# define MC_CSR_VAL 0x0B000300
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# define MC_MASK_VAL 0x000003f0
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# define FLASH_TMS_VAL 0x0000010c
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# define SDRAM_BASE_ADD 0x00000000
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# define SDRAM_TMS_VAL 0x2a5a0300
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100 |
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# elif CONFIG_OR32_SYS_CLK==120
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/* Sandi guarantees timings are ok */
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# define MC_CSR_VAL 0x0B000300
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103 |
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# define MC_MASK_VAL 0x000003f0
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104 |
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# define FLASH_TMS_VAL 0x0000010c
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# define SDRAM_BASE_ADD 0x00000000
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# define SDRAM_TMS_VAL 0x2a5a0300
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# else
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108 |
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# error No MC ver. 1 initialization values for this frequency
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# endif
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#elif CONFIG_OR32_MC_VERSION==2
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# define FLASH_BAR_VAL FLASH_BASE_ADD
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113 |
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# define FLASH_AMR_VAL 0xf0000000 /* address mask register */
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114 |
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# define SDRAM_BASE_ADDR 0x00000000
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# define SDRAM_SIZE 0x02000000
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116 |
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# define SDRAM_BAR_VAL SDRAM_BASE_ADDR
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117 |
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# define SDRAM_AMR_VAL (~(SDRAM_SIZE-1))
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118 |
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119 |
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/* independant from flash properties, always 0 ;) */
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120 |
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# define FLASH_OE_DELAY 0 /* output enable */
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121 |
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122 |
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// define FLASH_WTR_VAL 0x00011009 /* write timings */
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# define FLASH_WTR_VAL ((0x000003ff & (FLASH_WA_TIME /SYS_CLK_PERIOD)) | \
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(0x0000f000 & (FLASH_WE_DELAY/SYS_CLK_PERIOD)<<12) | \
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(0x001f0000 & (FLASH_WH_TIME /SYS_CLK_PERIOD)<<16))
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126 |
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127 |
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// define FLASH_RTR_VAL 0x01002009 /* read timings */
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128 |
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# define FLASH_RTR_VAL ((0x000003ff & (FLASH_RA_TIME /SYS_CLK_PERIOD)) | \
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(0x0000f000 & (FLASH_OE_DELAY/SYS_CLK_PERIOD)<<12) | \
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(0x001f0000 & (FLASH_PRA_TIME/SYS_CLK_PERIOD)<<16) | \
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(0x1f000000 & (FLASH_RT_TIME /SYS_CLK_PERIOD)<<24))
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/* round this value down:
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* if it's 30 / 10 -> we want 2, so it's ok, 31 / 10 -> we want 3
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*
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* define SDRAM_RCDR_VAL 0x00000002
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*/
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# define SDRAM_RCDR_VAL ((SDRAM_tRCD-1)/SYS_CLK_PERIOD)
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// prviously undefined
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# define SDRAM_WRTR_VAL (((SDRAM_tWR+(SYS_CLK_PERIOD-1))/SYS_CLK_PERIOD)-1)
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# if SDRAM_WRTR_VAL<0
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# undef SDRAM_WRTR_VAL
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# define SDRAM_WRTR_VAL 0
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# endif
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// define SDRAM_RCTR_VAL 0x00000006
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# define SDRAM_RCTR_VAL (((SDRAM_tRC+(SYS_CLK_PERIOD-1))/SYS_CLK_PERIOD)-1)
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# if SDRAM_RCTR_VAL<0
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# undef SDRAM_RCTR_VAL
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# define SDRAM_RCTR_VAL 0
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# endif
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154 |
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// define SDRAM_REFCTR_VAL 0x00000006
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# define SDRAM_REFCTR_VAL (((SDRAM_tRFC+(SYS_CLK_PERIOD-1))/SYS_CLK_PERIOD)-1)
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# if SDRAM_REFCTR_VAL<0
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# undef SDRAM_REFCTR_VAL
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# define SDRAM_REFCTR_VAL 0
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# endif
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// define SDRAM_RATR_VAL 0x00000006
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# define SDRAM_RATR_VAL (((SDRAM_tRAS+(SYS_CLK_PERIOD-1))/SYS_CLK_PERIOD)-1)
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# if SDRAM_RATR_VAL<0
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# undef SDRAM_RATR_VAL
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# define SDRAM_RATR_VAL 0
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# endif
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168 |
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// define SDRAM_PTR_VAL 0x00000001
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169 |
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# define SDRAM_PTR_VAL (((SDRAM_tRP+(SYS_CLK_PERIOD-1))/SYS_CLK_PERIOD)-1)
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170 |
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# if SDRAM_PTR_VAL<0
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# undef SDRAM_PTR_VAL
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# define SDRAM_PTR_VAL 0
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# endif
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// define SDRAM_RRDR_VAL 0x00000000
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# define SDRAM_RRDR_VAL (((SDRAM_tRRD+(SYS_CLK_PERIOD-1))/SYS_CLK_PERIOD)-1)
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# if SDRAM_RRDR_VAL<0
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# undef SDRAM_RRDR_VAL
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179 |
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# define SDRAM_RRDR_VAL 0
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# endif
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182 |
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/*
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* we don't want to go to the edge with refresh delays
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* define SDRAM_RIR_VAL 0x00000300
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*/
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# define SDRAM_RIR_VAL ((SDRAM_tREF/SYS_CLK_PERIOD)-((SDRAM_tREF/SYS_CLK_PERIOD)+10)/10)
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188 |
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/* ------------------------------------------------------[ MC registers ]--- */
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189 |
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190 |
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191 |
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# define MC_BAR_0 (0x00)
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192 |
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# define MC_AMR_0 (0x04)
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193 |
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# define MC_BAR_1 (0x08)
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194 |
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# define MC_AMR_1 (0x0c)
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# define MC_BAR_2 (0x10)
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196 |
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# define MC_AMR_2 (0x14)
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197 |
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# define MC_BAR_3 (0x18)
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198 |
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# define MC_AMR_3 (0x1c)
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199 |
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# define MC_CCR_0 (0x20)
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200 |
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# define MC_CCR_1 (0x24)
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201 |
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# define MC_CCR_2 (0x28)
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202 |
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# define MC_CCR_3 (0x2c)
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203 |
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# define MC_WTR_0 (0x30)
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204 |
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# define MC_RTR_0 (0x34)
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205 |
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# define MC_WTR_1 (0x38)
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206 |
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# define MC_RTR_1 (0x3c)
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207 |
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# define MC_WTR_2 (0x40)
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208 |
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# define MC_RTR_2 (0x44)
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209 |
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# define MC_WTR_3 (0x48)
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210 |
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# define MC_RTR_3 (0x4c)
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211 |
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212 |
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# define MC_BAR_4 (0x80)
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213 |
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# define MC_AMR_4 (0x84)
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214 |
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# define MC_BAR_5 (0x88)
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215 |
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# define MC_AMR_5 (0x8c)
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216 |
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# define MC_BAR_6 (0x90)
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217 |
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# define MC_AMR_6 (0x94)
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218 |
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# define MC_BAR_7 (0x98)
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219 |
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# define MC_AMR_7 (0x9c)
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220 |
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# define MC_CCR_4 (0xa0)
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221 |
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# define MC_CCR_5 (0xa4)
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222 |
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# define MC_CCR_6 (0xa8)
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223 |
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# define MC_CCR_7 (0xac)
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224 |
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225 |
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# define MC_RATR (0xb0) /* row active time register */
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226 |
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# define MC_RCTR (0xb4)
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227 |
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# define MC_RRDR (0xb8)
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228 |
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# define MC_PTR (0xbc)
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229 |
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# define MC_WRTR (0xc0)
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230 |
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# define MC_REFCTR (0xc4)
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231 |
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# define MC_RCDR (0xc8)
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232 |
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# define MC_RIR (0xcc)
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233 |
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# define MC_SMBOR (0xe0)
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234 |
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# define MC_ORR (0xe4)
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235 |
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# define MC_OSR (0xe8)
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236 |
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# define MC_PCR (0xec)
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237 |
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# define MC_IIR (0xf0)
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238 |
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239 |
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/* POC register field definition */
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240 |
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# define MC_POC_EN_BW_OFFSET 0
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241 |
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# define MC_POC_EN_BW_WIDTH 2
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242 |
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# define MC_POC_EN_MEMTYPE_OFFSET 2
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243 |
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# define MC_POC_EN_MEMTYPE_WIDTH 2
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244 |
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245 |
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/* CSC register field definition */
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246 |
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# define MC_CSC_EN_OFFSET 0
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247 |
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# define MC_CSC_MEMTYPE_OFFSET 1
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248 |
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# define MC_CSC_MEMTYPE_WIDTH 2
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249 |
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# define MC_CSC_BW_OFFSET 4
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250 |
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# define MC_CSC_BW_WIDTH 2
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251 |
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# define MC_CSC_MS_OFFSET 6
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252 |
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# define MC_CSC_MS_WIDTH 2
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253 |
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# define MC_CSC_WP_OFFSET 8
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254 |
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# define MC_CSC_BAS_OFFSET 9
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255 |
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# define MC_CSC_KRO_OFFSET 10
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256 |
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# define MC_CSC_PEN_OFFSET 11
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257 |
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# define MC_CSC_SEL_OFFSET 16
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258 |
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# define MC_CSC_SEL_WIDTH 8
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259 |
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260 |
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# define MC_CSC_MEMTYPE_SDRAM 0
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261 |
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# define MC_CSC_MEMTYPE_SSRAM 1
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262 |
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# define MC_CSC_MEMTYPE_ASYNC 2
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263 |
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# define MC_CSC_MEMTYPE_SYNC 3
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264 |
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265 |
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# define MC_CSR_VALID 0xFF000703LU
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266 |
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# define MC_POC_VALID 0x0000000FLU
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267 |
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# define MC_BA_MASK_VALID 0x000003FFLU
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268 |
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# define MC_CSC_VALID 0x00FF0FFFLU
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269 |
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# define MC_TMS_SDRAM_VALID 0x0FFF83FFLU
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270 |
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# define MC_TMS_SSRAM_VALID 0x00000000LU
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271 |
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# define MC_TMS_ASYNC_VALID 0x03FFFFFFLU
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272 |
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# define MC_TMS_SYNC_VALID 0x01FFFFFFLU
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273 |
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# define MC_TMS_VALID 0xFFFFFFFFLU /* reg test compat. */
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274 |
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275 |
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/* TMS register field definition SDRAM */
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276 |
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# define MC_TMS_SDRAM_TRFC_OFFSET 24
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277 |
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# define MC_TMS_SDRAM_TRFC_WIDTH 4
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278 |
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# define MC_TMS_SDRAM_TRP_OFFSET 20
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279 |
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# define MC_TMS_SDRAM_TRP_WIDTH 4
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280 |
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# define MC_TMS_SDRAM_TRCD_OFFSET 17
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281 |
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# define MC_TMS_SDRAM_TRCD_WIDTH 4
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282 |
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# define MC_TMS_SDRAM_TWR_OFFSET 15
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283 |
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# define MC_TMS_SDRAM_TWR_WIDTH 2
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284 |
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# define MC_TMS_SDRAM_WBL_OFFSET 9
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285 |
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# define MC_TMS_SDRAM_OM_OFFSET 7
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286 |
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# define MC_TMS_SDRAM_OM_WIDTH 2
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287 |
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# define MC_TMS_SDRAM_CL_OFFSET 4
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288 |
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# define MC_TMS_SDRAM_CL_WIDTH 3
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289 |
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# define MC_TMS_SDRAM_BT_OFFSET 3
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290 |
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# define MC_TMS_SDRAM_BL_OFFSET 0
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291 |
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# define MC_TMS_SDRAM_BL_WIDTH 3
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292 |
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293 |
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/* TMS register field definition ASYNC */
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294 |
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# define MC_TMS_ASYNC_TWWD_OFFSET 20
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295 |
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# define MC_TMS_ASYNC_TWWD_WIDTH 6
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296 |
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# define MC_TMS_ASYNC_TWD_OFFSET 16
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297 |
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# define MC_TMS_ASYNC_TWD_WIDTH 4
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298 |
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# define MC_TMS_ASYNC_TWPW_OFFSET 12
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299 |
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# define MC_TMS_ASYNC_TWPW_WIDTH 4
|
300 |
|
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# define MC_TMS_ASYNC_TRDZ_OFFSET 8
|
301 |
|
|
# define MC_TMS_ASYNC_TRDZ_WIDTH 4
|
302 |
|
|
# define MC_TMS_ASYNC_TRDV_OFFSET 0
|
303 |
|
|
# define MC_TMS_ASYNC_TRDV_WIDTH 8
|
304 |
|
|
|
305 |
|
|
/* TMS register field definition SYNC */
|
306 |
|
|
# define MC_TMS_SYNC_TTO_OFFSET 16
|
307 |
|
|
# define MC_TMS_SYNC_TTO_WIDTH 9
|
308 |
|
|
# define MC_TMS_SYNC_TWR_OFFSET 12
|
309 |
|
|
# define MC_TMS_SYNC_TWR_WIDTH 4
|
310 |
|
|
# define MC_TMS_SYNC_TRDZ_OFFSET 8
|
311 |
|
|
# define MC_TMS_SYNC_TRDZ_WIDTH 4
|
312 |
|
|
# define MC_TMS_SYNC_TRDV_OFFSET 0
|
313 |
|
|
# define MC_TMS_SYNC_TRDV_WIDTH 8
|
314 |
|
|
|
315 |
|
|
#else
|
316 |
|
|
# error "no memory controler specified"
|
317 |
|
|
#endif
|
318 |
|
|
|
319 |
|
|
#endif
|
320 |
|
|
|