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xianfeng |
/*
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* Copyright (c) 2004 James Courtier-Dutton <James@superbug.demon.co.uk>
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* Driver CA0106 chips. e.g. Sound Blaster Audigy LS and Live 24bit
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* Version: 0.0.22
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*
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* FEATURES currently supported:
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* See ca0106_main.c for features.
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*
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* Changelog:
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* Support interrupts per period.
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* Removed noise from Center/LFE channel when in Analog mode.
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* Rename and remove mixer controls.
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* 0.0.6
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* Use separate card based DMA buffer for periods table list.
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* 0.0.7
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* Change remove and rename ctrls into lists.
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* 0.0.8
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* Try to fix capture sources.
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* 0.0.9
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* Fix AC3 output.
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* Enable S32_LE format support.
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* 0.0.10
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* Enable playback 48000 and 96000 rates. (Rates other that these do not work, even with "plug:front".)
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* 0.0.11
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* Add Model name recognition.
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* 0.0.12
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* Correct interrupt timing. interrupt at end of period, instead of in the middle of a playback period.
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* Remove redundent "voice" handling.
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* 0.0.13
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* Single trigger call for multi channels.
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* 0.0.14
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* Set limits based on what the sound card hardware can do.
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* playback periods_min=2, periods_max=8
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* capture hw constraints require period_size = n * 64 bytes.
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* playback hw constraints require period_size = n * 64 bytes.
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* 0.0.15
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* Separated ca0106.c into separate functional .c files.
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* 0.0.16
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* Implement 192000 sample rate.
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* 0.0.17
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* Add support for SB0410 and SB0413.
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* 0.0.18
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* Modified Copyright message.
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* 0.0.19
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* Added I2C and SPI registers. Filled in interrupt enable.
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* 0.0.20
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* Added GPIO info for SB Live 24bit.
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* 0.0.21
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* Implement support for Line-in capture on SB Live 24bit.
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* 0.0.22
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* Add support for mute control on SB Live 24bit (cards w/ SPI DAC)
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*
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*
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* This code was initally based on code from ALSA's emu10k1x.c which is:
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* Copyright (c) by Francisco Moraes <fmoraes@nc.rr.com>
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; either version 2 of the License, or
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* (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
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*
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*/
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/************************************************************************************************/
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/* PCI function 0 registers, address = <val> + PCIBASE0 */
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/************************************************************************************************/
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#define PTR 0x00 /* Indexed register set pointer register */
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/* NOTE: The CHANNELNUM and ADDRESS words can */
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/* be modified independently of each other. */
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/* CNL[1:0], ADDR[27:16] */
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#define DATA 0x04 /* Indexed register set data register */
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/* DATA[31:0] */
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#define IPR 0x08 /* Global interrupt pending register */
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/* Clear pending interrupts by writing a 1 to */
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/* the relevant bits and zero to the other bits */
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#define IPR_MIDI_RX_B 0x00020000 /* MIDI UART-B Receive buffer non-empty */
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#define IPR_MIDI_TX_B 0x00010000 /* MIDI UART-B Transmit buffer empty */
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#define IPR_SPDIF_IN_USER 0x00004000 /* SPDIF input user data has 16 more bits */
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#define IPR_SPDIF_OUT_USER 0x00002000 /* SPDIF output user data needs 16 more bits */
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#define IPR_SPDIF_OUT_FRAME 0x00001000 /* SPDIF frame about to start */
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#define IPR_SPI 0x00000800 /* SPI transaction completed */
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#define IPR_I2C_EEPROM 0x00000400 /* I2C EEPROM transaction completed */
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#define IPR_I2C_DAC 0x00000200 /* I2C DAC transaction completed */
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#define IPR_AI 0x00000100 /* Audio pending register changed. See PTR reg 0x76 */
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#define IPR_GPI 0x00000080 /* General Purpose input changed */
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#define IPR_SRC_LOCKED 0x00000040 /* SRC lock status changed */
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#define IPR_SPDIF_STATUS 0x00000020 /* SPDIF status changed */
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#define IPR_TIMER2 0x00000010 /* 192000Hz Timer */
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#define IPR_TIMER1 0x00000008 /* 44100Hz Timer */
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#define IPR_MIDI_RX_A 0x00000004 /* MIDI UART-A Receive buffer non-empty */
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#define IPR_MIDI_TX_A 0x00000002 /* MIDI UART-A Transmit buffer empty */
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#define IPR_PCI 0x00000001 /* PCI Bus error */
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#define INTE 0x0c /* Interrupt enable register */
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#define INTE_MIDI_RX_B 0x00020000 /* MIDI UART-B Receive buffer non-empty */
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#define INTE_MIDI_TX_B 0x00010000 /* MIDI UART-B Transmit buffer empty */
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#define INTE_SPDIF_IN_USER 0x00004000 /* SPDIF input user data has 16 more bits */
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#define INTE_SPDIF_OUT_USER 0x00002000 /* SPDIF output user data needs 16 more bits */
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#define INTE_SPDIF_OUT_FRAME 0x00001000 /* SPDIF frame about to start */
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#define INTE_SPI 0x00000800 /* SPI transaction completed */
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#define INTE_I2C_EEPROM 0x00000400 /* I2C EEPROM transaction completed */
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#define INTE_I2C_DAC 0x00000200 /* I2C DAC transaction completed */
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#define INTE_AI 0x00000100 /* Audio pending register changed. See PTR reg 0x75 */
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#define INTE_GPI 0x00000080 /* General Purpose input changed */
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#define INTE_SRC_LOCKED 0x00000040 /* SRC lock status changed */
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#define INTE_SPDIF_STATUS 0x00000020 /* SPDIF status changed */
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#define INTE_TIMER2 0x00000010 /* 192000Hz Timer */
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#define INTE_TIMER1 0x00000008 /* 44100Hz Timer */
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#define INTE_MIDI_RX_A 0x00000004 /* MIDI UART-A Receive buffer non-empty */
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#define INTE_MIDI_TX_A 0x00000002 /* MIDI UART-A Transmit buffer empty */
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#define INTE_PCI 0x00000001 /* PCI Bus error */
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#define UNKNOWN10 0x10 /* Unknown ??. Defaults to 0 */
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#define HCFG 0x14 /* Hardware config register */
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/* 0x1000 causes AC3 to fails. It adds a dither bit. */
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#define HCFG_STAC 0x10000000 /* Special mode for STAC9460 Codec. */
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#define HCFG_CAPTURE_I2S_BYPASS 0x08000000 /* 1 = bypass I2S input async SRC. */
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#define HCFG_CAPTURE_SPDIF_BYPASS 0x04000000 /* 1 = bypass SPDIF input async SRC. */
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#define HCFG_PLAYBACK_I2S_BYPASS 0x02000000 /* 0 = I2S IN mixer output, 1 = I2S IN1. */
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#define HCFG_FORCE_LOCK 0x01000000 /* For test only. Force input SRC tracker to lock. */
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#define HCFG_PLAYBACK_ATTENUATION 0x00006000 /* Playback attenuation mask. 0 = 0dB, 1 = 6dB, 2 = 12dB, 3 = Mute. */
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#define HCFG_PLAYBACK_DITHER 0x00001000 /* 1 = Add dither bit to all playback channels. */
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#define HCFG_PLAYBACK_S32_LE 0x00000800 /* 1 = S32_LE, 0 = S16_LE */
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#define HCFG_CAPTURE_S32_LE 0x00000400 /* 1 = S32_LE, 0 = S16_LE (S32_LE current not working) */
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#define HCFG_8_CHANNEL_PLAY 0x00000200 /* 1 = 8 channels, 0 = 2 channels per substream.*/
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#define HCFG_8_CHANNEL_CAPTURE 0x00000100 /* 1 = 8 channels, 0 = 2 channels per substream.*/
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#define HCFG_MONO 0x00000080 /* 1 = I2S Input mono */
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#define HCFG_I2S_OUTPUT 0x00000010 /* 1 = I2S Output disabled */
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#define HCFG_AC97 0x00000008 /* 0 = AC97 1.0, 1 = AC97 2.0 */
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#define HCFG_LOCK_PLAYBACK_CACHE 0x00000004 /* 1 = Cancel bustmaster accesses to soundcache */
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/* NOTE: This should generally never be used. */
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#define HCFG_LOCK_CAPTURE_CACHE 0x00000002 /* 1 = Cancel bustmaster accesses to soundcache */
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/* NOTE: This should generally never be used. */
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#define HCFG_AUDIOENABLE 0x00000001 /* 0 = CODECs transmit zero-valued samples */
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/* Should be set to 1 when the EMU10K1 is */
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/* completely initialized. */
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#define GPIO 0x18 /* Defaults: 005f03a3-Analog, 005f02a2-SPDIF. */
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/* Here pins 0,1,2,3,4,,6 are output. 5,7 are input */
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/* For the Audigy LS, pin 0 (or bit 8) controls the SPDIF/Analog jack. */
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/* SB Live 24bit:
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* bit 8 0 = SPDIF in and out / 1 = Analog (Mic or Line)-in.
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* bit 9 0 = Mute / 1 = Analog out.
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* bit 10 0 = Line-in / 1 = Mic-in.
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* bit 11 0 = ? / 1 = ?
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* bit 12 0 = 48 Khz / 1 = 96 Khz Analog out on SB Live 24bit.
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* bit 13 0 = ? / 1 = ?
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* bit 14 0 = Mute / 1 = Analog out
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* bit 15 0 = ? / 1 = ?
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* Both bit 9 and bit 14 have to be set for analog sound to work on the SB Live 24bit.
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*/
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/* 8 general purpose programmable In/Out pins.
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* GPI [8:0] Read only. Default 0.
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* GPO [15:8] Default 0x9. (Default to SPDIF jack enabled for SPDIF)
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* GPO Enable [23:16] Default 0x0f. Setting a bit to 1, causes the pin to be an output pin.
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*/
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#define AC97DATA 0x1c /* AC97 register set data register (16 bit) */
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#define AC97ADDRESS 0x1e /* AC97 register set address register (8 bit) */
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/********************************************************************************************************/
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/* CA0106 pointer-offset register set, accessed through the PTR and DATA registers */
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/********************************************************************************************************/
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/* Initally all registers from 0x00 to 0x3f have zero contents. */
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#define PLAYBACK_LIST_ADDR 0x00 /* Base DMA address of a list of pointers to each period/size */
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/* One list entry: 4 bytes for DMA address,
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* 4 bytes for period_size << 16.
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* One list entry is 8 bytes long.
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* One list entry for each period in the buffer.
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*/
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/* ADDR[31:0], Default: 0x0 */
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#define PLAYBACK_LIST_SIZE 0x01 /* Size of list in bytes << 16. E.g. 8 periods -> 0x00380000 */
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/* SIZE[21:16], Default: 0x8 */
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#define PLAYBACK_LIST_PTR 0x02 /* Pointer to the current period being played */
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/* PTR[5:0], Default: 0x0 */
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#define PLAYBACK_UNKNOWN3 0x03 /* Not used ?? */
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#define PLAYBACK_DMA_ADDR 0x04 /* Playback DMA addresss */
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/* DMA[31:0], Default: 0x0 */
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#define PLAYBACK_PERIOD_SIZE 0x05 /* Playback period size. win2000 uses 0x04000000 */
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/* SIZE[31:16], Default: 0x0 */
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#define PLAYBACK_POINTER 0x06 /* Playback period pointer. Used with PLAYBACK_LIST_PTR to determine buffer position currently in DAC */
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/* POINTER[15:0], Default: 0x0 */
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#define PLAYBACK_PERIOD_END_ADDR 0x07 /* Playback fifo end address */
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/* END_ADDR[15:0], FLAG[16] 0 = don't stop, 1 = stop */
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#define PLAYBACK_FIFO_OFFSET_ADDRESS 0x08 /* Current fifo offset address [21:16] */
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/* Cache size valid [5:0] */
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#define PLAYBACK_UNKNOWN9 0x09 /* 0x9 to 0xf Unused */
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#define CAPTURE_DMA_ADDR 0x10 /* Capture DMA address */
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/* DMA[31:0], Default: 0x0 */
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#define CAPTURE_BUFFER_SIZE 0x11 /* Capture buffer size */
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/* SIZE[31:16], Default: 0x0 */
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#define CAPTURE_POINTER 0x12 /* Capture buffer pointer. Sample currently in ADC */
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/* POINTER[15:0], Default: 0x0 */
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#define CAPTURE_FIFO_OFFSET_ADDRESS 0x13 /* Current fifo offset address [21:16] */
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/* Cache size valid [5:0] */
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#define PLAYBACK_LAST_SAMPLE 0x20 /* The sample currently being played */
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/* 0x21 - 0x3f unused */
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#define BASIC_INTERRUPT 0x40 /* Used by both playback and capture interrupt handler */
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/* Playback (0x1<<channel_id) */
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/* Capture (0x100<<channel_id) */
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/* Playback sample rate 96000 = 0x20000 */
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/* Start Playback [3:0] (one bit per channel)
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* Start Capture [11:8] (one bit per channel)
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* Playback rate [23:16] (2 bits per channel) (0=48kHz, 1=44.1kHz, 2=96kHz, 3=192Khz)
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* Playback mixer in enable [27:24] (one bit per channel)
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* Playback mixer out enable [31:28] (one bit per channel)
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*/
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/* The Digital out jack is shared with the Center/LFE Analogue output.
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* The jack has 4 poles. I will call 1 - Tip, 2 - Next to 1, 3 - Next to 2, 4 - Next to 3
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* For Analogue: 1 -> Center Speaker, 2 -> Sub Woofer, 3 -> Ground, 4 -> Ground
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* For Digital: 1 -> Front SPDIF, 2 -> Rear SPDIF, 3 -> Center/Subwoofer SPDIF, 4 -> Ground.
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* Standard 4 pole Video A/V cable with RCA outputs: 1 -> White, 2 -> Yellow, 3 -> Sheild on all three, 4 -> Red.
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* So, from this you can see that you cannot use a Standard 4 pole Video A/V cable with the SB Audigy LS card.
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*/
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/* The Front SPDIF PCM gets mixed with samples from the AC97 codec, so can only work for Stereo PCM and not AC3/DTS
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* The Rear SPDIF can be used for Stereo PCM and also AC3/DTS
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* The Center/LFE SPDIF cannot be used for AC3/DTS, but can be used for Stereo PCM.
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* Summary: For ALSA we use the Rear channel for SPDIF Digital AC3/DTS output
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*/
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/* A standard 2 pole mono mini-jack to RCA plug can be used for SPDIF Stereo PCM output from the Front channel.
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* A standard 3 pole stereo mini-jack to 2 RCA plugs can be used for SPDIF AC3/DTS and Stereo PCM output utilising the Rear channel and just one of the RCA plugs.
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*/
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#define SPCS0 0x41 /* SPDIF output Channel Status 0 register. For Rear. default=0x02108004, non-audio=0x02108006 */
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#define SPCS1 0x42 /* SPDIF output Channel Status 1 register. For Front */
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#define SPCS2 0x43 /* SPDIF output Channel Status 2 register. For Center/LFE */
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#define SPCS3 0x44 /* SPDIF output Channel Status 3 register. Unknown */
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/* When Channel set to 0: */
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#define SPCS_CLKACCYMASK 0x30000000 /* Clock accuracy */
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#define SPCS_CLKACCY_1000PPM 0x00000000 /* 1000 parts per million */
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#define SPCS_CLKACCY_50PPM 0x10000000 /* 50 parts per million */
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#define SPCS_CLKACCY_VARIABLE 0x20000000 /* Variable accuracy */
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#define SPCS_SAMPLERATEMASK 0x0f000000 /* Sample rate */
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#define SPCS_SAMPLERATE_44 0x00000000 /* 44.1kHz sample rate */
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#define SPCS_SAMPLERATE_48 0x02000000 /* 48kHz sample rate */
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#define SPCS_SAMPLERATE_32 0x03000000 /* 32kHz sample rate */
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#define SPCS_CHANNELNUMMASK 0x00f00000 /* Channel number */
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#define SPCS_CHANNELNUM_UNSPEC 0x00000000 /* Unspecified channel number */
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#define SPCS_CHANNELNUM_LEFT 0x00100000 /* Left channel */
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#define SPCS_CHANNELNUM_RIGHT 0x00200000 /* Right channel */
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#define SPCS_SOURCENUMMASK 0x000f0000 /* Source number */
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#define SPCS_SOURCENUM_UNSPEC 0x00000000 /* Unspecified source number */
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#define SPCS_GENERATIONSTATUS 0x00008000 /* Originality flag (see IEC-958 spec) */
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|
|
#define SPCS_CATEGORYCODEMASK 0x00007f00 /* Category code (see IEC-958 spec) */
|
| 258 |
|
|
#define SPCS_MODEMASK 0x000000c0 /* Mode (see IEC-958 spec) */
|
| 259 |
|
|
#define SPCS_EMPHASISMASK 0x00000038 /* Emphasis */
|
| 260 |
|
|
#define SPCS_EMPHASIS_NONE 0x00000000 /* No emphasis */
|
| 261 |
|
|
#define SPCS_EMPHASIS_50_15 0x00000008 /* 50/15 usec 2 channel */
|
| 262 |
|
|
#define SPCS_COPYRIGHT 0x00000004 /* Copyright asserted flag -- do not modify */
|
| 263 |
|
|
#define SPCS_NOTAUDIODATA 0x00000002 /* 0 = Digital audio, 1 = not audio */
|
| 264 |
|
|
#define SPCS_PROFESSIONAL 0x00000001 /* 0 = Consumer (IEC-958), 1 = pro (AES3-1992) */
|
| 265 |
|
|
|
| 266 |
|
|
/* When Channel set to 1: */
|
| 267 |
|
|
#define SPCS_WORD_LENGTH_MASK 0x0000000f /* Word Length Mask */
|
| 268 |
|
|
#define SPCS_WORD_LENGTH_16 0x00000008 /* Word Length 16 bit */
|
| 269 |
|
|
#define SPCS_WORD_LENGTH_17 0x00000006 /* Word Length 17 bit */
|
| 270 |
|
|
#define SPCS_WORD_LENGTH_18 0x00000004 /* Word Length 18 bit */
|
| 271 |
|
|
#define SPCS_WORD_LENGTH_19 0x00000002 /* Word Length 19 bit */
|
| 272 |
|
|
#define SPCS_WORD_LENGTH_20A 0x0000000a /* Word Length 20 bit */
|
| 273 |
|
|
#define SPCS_WORD_LENGTH_20 0x00000009 /* Word Length 20 bit (both 0xa and 0x9 are 20 bit) */
|
| 274 |
|
|
#define SPCS_WORD_LENGTH_21 0x00000007 /* Word Length 21 bit */
|
| 275 |
|
|
#define SPCS_WORD_LENGTH_21 0x00000007 /* Word Length 21 bit */
|
| 276 |
|
|
#define SPCS_WORD_LENGTH_22 0x00000005 /* Word Length 22 bit */
|
| 277 |
|
|
#define SPCS_WORD_LENGTH_23 0x00000003 /* Word Length 23 bit */
|
| 278 |
|
|
#define SPCS_WORD_LENGTH_24 0x0000000b /* Word Length 24 bit */
|
| 279 |
|
|
#define SPCS_ORIGINAL_SAMPLE_RATE_MASK 0x000000f0 /* Original Sample rate */
|
| 280 |
|
|
#define SPCS_ORIGINAL_SAMPLE_RATE_NONE 0x00000000 /* Original Sample rate not indicated */
|
| 281 |
|
|
#define SPCS_ORIGINAL_SAMPLE_RATE_16000 0x00000010 /* Original Sample rate */
|
| 282 |
|
|
#define SPCS_ORIGINAL_SAMPLE_RATE_RES1 0x00000020 /* Original Sample rate */
|
| 283 |
|
|
#define SPCS_ORIGINAL_SAMPLE_RATE_32000 0x00000030 /* Original Sample rate */
|
| 284 |
|
|
#define SPCS_ORIGINAL_SAMPLE_RATE_12000 0x00000040 /* Original Sample rate */
|
| 285 |
|
|
#define SPCS_ORIGINAL_SAMPLE_RATE_11025 0x00000050 /* Original Sample rate */
|
| 286 |
|
|
#define SPCS_ORIGINAL_SAMPLE_RATE_8000 0x00000060 /* Original Sample rate */
|
| 287 |
|
|
#define SPCS_ORIGINAL_SAMPLE_RATE_RES2 0x00000070 /* Original Sample rate */
|
| 288 |
|
|
#define SPCS_ORIGINAL_SAMPLE_RATE_192000 0x00000080 /* Original Sample rate */
|
| 289 |
|
|
#define SPCS_ORIGINAL_SAMPLE_RATE_24000 0x00000090 /* Original Sample rate */
|
| 290 |
|
|
#define SPCS_ORIGINAL_SAMPLE_RATE_96000 0x000000a0 /* Original Sample rate */
|
| 291 |
|
|
#define SPCS_ORIGINAL_SAMPLE_RATE_48000 0x000000b0 /* Original Sample rate */
|
| 292 |
|
|
#define SPCS_ORIGINAL_SAMPLE_RATE_176400 0x000000c0 /* Original Sample rate */
|
| 293 |
|
|
#define SPCS_ORIGINAL_SAMPLE_RATE_22050 0x000000d0 /* Original Sample rate */
|
| 294 |
|
|
#define SPCS_ORIGINAL_SAMPLE_RATE_88200 0x000000e0 /* Original Sample rate */
|
| 295 |
|
|
#define SPCS_ORIGINAL_SAMPLE_RATE_44100 0x000000f0 /* Original Sample rate */
|
| 296 |
|
|
|
| 297 |
|
|
#define SPDIF_SELECT1 0x45 /* Enables SPDIF or Analogue outputs 0-SPDIF, 0xf00-Analogue */
|
| 298 |
|
|
/* 0x100 - Front, 0x800 - Rear, 0x200 - Center/LFE.
|
| 299 |
|
|
* But as the jack is shared, use 0xf00.
|
| 300 |
|
|
* The Windows2000 driver uses 0x0000000f for both digital and analog.
|
| 301 |
|
|
* 0xf00 introduces interesting noises onto the Center/LFE.
|
| 302 |
|
|
* If you turn the volume up, you hear computer noise,
|
| 303 |
|
|
* e.g. mouse moving, changing between app windows etc.
|
| 304 |
|
|
* So, I am going to set this to 0x0000000f all the time now,
|
| 305 |
|
|
* same as the windows driver does.
|
| 306 |
|
|
* Use register SPDIF_SELECT2(0x72) to switch between SPDIF and Analog.
|
| 307 |
|
|
*/
|
| 308 |
|
|
/* When Channel = 0:
|
| 309 |
|
|
* Wide SPDIF format [3:0] (one bit for each channel) (0=20bit, 1=24bit)
|
| 310 |
|
|
* Tristate SPDIF Output [11:8] (one bit for each channel) (0=Not tristate, 1=Tristate)
|
| 311 |
|
|
* SPDIF Bypass enable [19:16] (one bit for each channel) (0=Not bypass, 1=Bypass)
|
| 312 |
|
|
*/
|
| 313 |
|
|
/* When Channel = 1:
|
| 314 |
|
|
* SPDIF 0 User data [7:0]
|
| 315 |
|
|
* SPDIF 1 User data [15:8]
|
| 316 |
|
|
* SPDIF 0 User data [23:16]
|
| 317 |
|
|
* SPDIF 0 User data [31:24]
|
| 318 |
|
|
* User data can be sent by using the SPDIF output frame pending and SPDIF output user bit interrupts.
|
| 319 |
|
|
*/
|
| 320 |
|
|
#define WATERMARK 0x46 /* Test bit to indicate cache usage level */
|
| 321 |
|
|
#define SPDIF_INPUT_STATUS 0x49 /* SPDIF Input status register. Bits the same as SPCS.
|
| 322 |
|
|
* When Channel = 0: Bits the same as SPCS channel 0.
|
| 323 |
|
|
* When Channel = 1: Bits the same as SPCS channel 1.
|
| 324 |
|
|
* When Channel = 2:
|
| 325 |
|
|
* SPDIF Input User data [16:0]
|
| 326 |
|
|
* SPDIF Input Frame count [21:16]
|
| 327 |
|
|
*/
|
| 328 |
|
|
#define CAPTURE_CACHE_DATA 0x50 /* 0x50-0x5f Recorded samples. */
|
| 329 |
|
|
#define CAPTURE_SOURCE 0x60 /* Capture Source 0 = MIC */
|
| 330 |
|
|
#define CAPTURE_SOURCE_CHANNEL0 0xf0000000 /* Mask for selecting the Capture sources */
|
| 331 |
|
|
#define CAPTURE_SOURCE_CHANNEL1 0x0f000000 /* 0 - SPDIF mixer output. */
|
| 332 |
|
|
#define CAPTURE_SOURCE_CHANNEL2 0x00f00000 /* 1 - What you hear or . 2 - ?? */
|
| 333 |
|
|
#define CAPTURE_SOURCE_CHANNEL3 0x000f0000 /* 3 - Mic in, Line in, TAD in, Aux in. */
|
| 334 |
|
|
#define CAPTURE_SOURCE_RECORD_MAP 0x0000ffff /* Default 0x00e4 */
|
| 335 |
|
|
/* Record Map [7:0] (2 bits per channel) 0=mapped to channel 0, 1=mapped to channel 1, 2=mapped to channel2, 3=mapped to channel3
|
| 336 |
|
|
* Record source select for channel 0 [18:16]
|
| 337 |
|
|
* Record source select for channel 1 [22:20]
|
| 338 |
|
|
* Record source select for channel 2 [26:24]
|
| 339 |
|
|
* Record source select for channel 3 [30:28]
|
| 340 |
|
|
* 0 - SPDIF mixer output.
|
| 341 |
|
|
* 1 - i2s mixer output.
|
| 342 |
|
|
* 2 - SPDIF input.
|
| 343 |
|
|
* 3 - i2s input.
|
| 344 |
|
|
* 4 - AC97 capture.
|
| 345 |
|
|
* 5 - SRC output.
|
| 346 |
|
|
*/
|
| 347 |
|
|
#define CAPTURE_VOLUME1 0x61 /* Capture volume per channel 0-3 */
|
| 348 |
|
|
#define CAPTURE_VOLUME2 0x62 /* Capture volume per channel 4-7 */
|
| 349 |
|
|
|
| 350 |
|
|
#define PLAYBACK_ROUTING1 0x63 /* Playback routing of channels 0-7. Effects AC3 output. Default 0x32765410 */
|
| 351 |
|
|
#define ROUTING1_REAR 0x77000000 /* Channel_id 0 sends to 10, Channel_id 1 sends to 32 */
|
| 352 |
|
|
#define ROUTING1_NULL 0x00770000 /* Channel_id 2 sends to 54, Channel_id 3 sends to 76 */
|
| 353 |
|
|
#define ROUTING1_CENTER_LFE 0x00007700 /* 0x32765410 means, send Channel_id 0 to FRONT, Channel_id 1 to REAR */
|
| 354 |
|
|
#define ROUTING1_FRONT 0x00000077 /* Channel_id 2 to CENTER_LFE, Channel_id 3 to NULL. */
|
| 355 |
|
|
/* Channel_id's handle stereo channels. Channel X is a single mono channel */
|
| 356 |
|
|
/* Host is input from the PCI bus. */
|
| 357 |
|
|
/* Host channel 0 [2:0] -> SPDIF Mixer/Router channel 0-7.
|
| 358 |
|
|
* Host channel 1 [6:4] -> SPDIF Mixer/Router channel 0-7.
|
| 359 |
|
|
* Host channel 2 [10:8] -> SPDIF Mixer/Router channel 0-7.
|
| 360 |
|
|
* Host channel 3 [14:12] -> SPDIF Mixer/Router channel 0-7.
|
| 361 |
|
|
* Host channel 4 [18:16] -> SPDIF Mixer/Router channel 0-7.
|
| 362 |
|
|
* Host channel 5 [22:20] -> SPDIF Mixer/Router channel 0-7.
|
| 363 |
|
|
* Host channel 6 [26:24] -> SPDIF Mixer/Router channel 0-7.
|
| 364 |
|
|
* Host channel 7 [30:28] -> SPDIF Mixer/Router channel 0-7.
|
| 365 |
|
|
*/
|
| 366 |
|
|
|
| 367 |
|
|
#define PLAYBACK_ROUTING2 0x64 /* Playback Routing . Feeding Capture channels back into Playback. Effects AC3 output. Default 0x76767676 */
|
| 368 |
|
|
/* SRC is input from the capture inputs. */
|
| 369 |
|
|
/* SRC channel 0 [2:0] -> SPDIF Mixer/Router channel 0-7.
|
| 370 |
|
|
* SRC channel 1 [6:4] -> SPDIF Mixer/Router channel 0-7.
|
| 371 |
|
|
* SRC channel 2 [10:8] -> SPDIF Mixer/Router channel 0-7.
|
| 372 |
|
|
* SRC channel 3 [14:12] -> SPDIF Mixer/Router channel 0-7.
|
| 373 |
|
|
* SRC channel 4 [18:16] -> SPDIF Mixer/Router channel 0-7.
|
| 374 |
|
|
* SRC channel 5 [22:20] -> SPDIF Mixer/Router channel 0-7.
|
| 375 |
|
|
* SRC channel 6 [26:24] -> SPDIF Mixer/Router channel 0-7.
|
| 376 |
|
|
* SRC channel 7 [30:28] -> SPDIF Mixer/Router channel 0-7.
|
| 377 |
|
|
*/
|
| 378 |
|
|
|
| 379 |
|
|
#define PLAYBACK_MUTE 0x65 /* Unknown. While playing 0x0, while silent 0x00fc0000 */
|
| 380 |
|
|
/* SPDIF Mixer input control:
|
| 381 |
|
|
* Invert SRC to SPDIF Mixer [7-0] (One bit per channel)
|
| 382 |
|
|
* Invert Host to SPDIF Mixer [15:8] (One bit per channel)
|
| 383 |
|
|
* SRC to SPDIF Mixer disable [23:16] (One bit per channel)
|
| 384 |
|
|
* Host to SPDIF Mixer disable [31:24] (One bit per channel)
|
| 385 |
|
|
*/
|
| 386 |
|
|
#define PLAYBACK_VOLUME1 0x66 /* Playback SPDIF volume per channel. Set to the same PLAYBACK_VOLUME(0x6a) */
|
| 387 |
|
|
/* PLAYBACK_VOLUME1 must be set to 30303030 for SPDIF AC3 Playback */
|
| 388 |
|
|
/* SPDIF mixer input volume. 0=12dB, 0x30=0dB, 0xFE=-51.5dB, 0xff=Mute */
|
| 389 |
|
|
/* One register for each of the 4 stereo streams. */
|
| 390 |
|
|
/* SRC Right volume [7:0]
|
| 391 |
|
|
* SRC Left volume [15:8]
|
| 392 |
|
|
* Host Right volume [23:16]
|
| 393 |
|
|
* Host Left volume [31:24]
|
| 394 |
|
|
*/
|
| 395 |
|
|
#define CAPTURE_ROUTING1 0x67 /* Capture Routing. Default 0x32765410 */
|
| 396 |
|
|
/* Similar to register 0x63, except that the destination is the I2S mixer instead of the SPDIF mixer. I.E. Outputs to the Analog outputs instead of SPDIF. */
|
| 397 |
|
|
#define CAPTURE_ROUTING2 0x68 /* Unknown Routing. Default 0x76767676 */
|
| 398 |
|
|
/* Similar to register 0x64, except that the destination is the I2S mixer instead of the SPDIF mixer. I.E. Outputs to the Analog outputs instead of SPDIF. */
|
| 399 |
|
|
#define CAPTURE_MUTE 0x69 /* Unknown. While capturing 0x0, while silent 0x00fc0000 */
|
| 400 |
|
|
/* Similar to register 0x65, except that the destination is the I2S mixer instead of the SPDIF mixer. I.E. Outputs to the Analog outputs instead of SPDIF. */
|
| 401 |
|
|
#define PLAYBACK_VOLUME2 0x6a /* Playback Analog volume per channel. Does not effect AC3 output */
|
| 402 |
|
|
/* Similar to register 0x66, except that the destination is the I2S mixer instead of the SPDIF mixer. I.E. Outputs to the Analog outputs instead of SPDIF. */
|
| 403 |
|
|
#define UNKNOWN6b 0x6b /* Unknown. Readonly. Default 00400000 00400000 00400000 00400000 */
|
| 404 |
|
|
#define MIDI_UART_A_DATA 0x6c /* Midi Uart A Data */
|
| 405 |
|
|
#define MIDI_UART_A_CMD 0x6d /* Midi Uart A Command/Status */
|
| 406 |
|
|
#define MIDI_UART_B_DATA 0x6e /* Midi Uart B Data (currently unused) */
|
| 407 |
|
|
#define MIDI_UART_B_CMD 0x6f /* Midi Uart B Command/Status (currently unused) */
|
| 408 |
|
|
|
| 409 |
|
|
/* unique channel identifier for midi->channel */
|
| 410 |
|
|
|
| 411 |
|
|
#define CA0106_MIDI_CHAN_A 0x1
|
| 412 |
|
|
#define CA0106_MIDI_CHAN_B 0x2
|
| 413 |
|
|
|
| 414 |
|
|
/* from mpu401 */
|
| 415 |
|
|
|
| 416 |
|
|
#define CA0106_MIDI_INPUT_AVAIL 0x80
|
| 417 |
|
|
#define CA0106_MIDI_OUTPUT_READY 0x40
|
| 418 |
|
|
#define CA0106_MPU401_RESET 0xff
|
| 419 |
|
|
#define CA0106_MPU401_ENTER_UART 0x3f
|
| 420 |
|
|
#define CA0106_MPU401_ACK 0xfe
|
| 421 |
|
|
|
| 422 |
|
|
#define SAMPLE_RATE_TRACKER_STATUS 0x70 /* Readonly. Default 00108000 00108000 00500000 00500000 */
|
| 423 |
|
|
/* Estimated sample rate [19:0] Relative to 48kHz. 0x8000 = 1.0
|
| 424 |
|
|
* Rate Locked [20]
|
| 425 |
|
|
* SPDIF Locked [21] For SPDIF channel only.
|
| 426 |
|
|
* Valid Audio [22] For SPDIF channel only.
|
| 427 |
|
|
*/
|
| 428 |
|
|
#define CAPTURE_CONTROL 0x71 /* Some sort of routing. default = 40c81000 30303030 30300000 00700000 */
|
| 429 |
|
|
/* Channel_id 0: 0x40c81000 must be changed to 0x40c80000 for SPDIF AC3 input or output. */
|
| 430 |
|
|
/* Channel_id 1: 0xffffffff(mute) 0x30303030(max) controls CAPTURE feedback into PLAYBACK. */
|
| 431 |
|
|
/* Sample rate output control register Channel=0
|
| 432 |
|
|
* Sample output rate [1:0] (0=48kHz, 1=44.1kHz, 2=96kHz, 3=192Khz)
|
| 433 |
|
|
* Sample input rate [3:2] (0=48kHz, 1=Not available, 2=96kHz, 3=192Khz)
|
| 434 |
|
|
* SRC input source select [4] 0=Audio from digital mixer, 1=Audio from analog source.
|
| 435 |
|
|
* Record rate [9:8] (0=48kHz, 1=Not available, 2=96kHz, 3=192Khz)
|
| 436 |
|
|
* Record mixer output enable [12:10]
|
| 437 |
|
|
* I2S input rate master mode [15:14] (0=48kHz, 1=44.1kHz, 2=96kHz, 3=192Khz)
|
| 438 |
|
|
* I2S output rate [17:16] (0=48kHz, 1=44.1kHz, 2=96kHz, 3=192Khz)
|
| 439 |
|
|
* I2S output source select [18] (0=Audio from host, 1=Audio from SRC)
|
| 440 |
|
|
* Record mixer I2S enable [20:19] (enable/disable i2sin1 and i2sin0)
|
| 441 |
|
|
* I2S output master clock select [21] (0=256*I2S output rate, 1=512*I2S output rate.)
|
| 442 |
|
|
* I2S input master clock select [22] (0=256*I2S input rate, 1=512*I2S input rate.)
|
| 443 |
|
|
* I2S input mode [23] (0=Slave, 1=Master)
|
| 444 |
|
|
* SPDIF output rate [25:24] (0=48kHz, 1=44.1kHz, 2=96kHz, 3=192Khz)
|
| 445 |
|
|
* SPDIF output source select [26] (0=host, 1=SRC)
|
| 446 |
|
|
* Not used [27]
|
| 447 |
|
|
* Record Source 0 input [29:28] (0=SPDIF in, 1=I2S in, 2=AC97 Mic, 3=AC97 PCM)
|
| 448 |
|
|
* Record Source 1 input [31:30] (0=SPDIF in, 1=I2S in, 2=AC97 Mic, 3=AC97 PCM)
|
| 449 |
|
|
*/
|
| 450 |
|
|
/* Sample rate output control register Channel=1
|
| 451 |
|
|
* I2S Input 0 volume Right [7:0]
|
| 452 |
|
|
* I2S Input 0 volume Left [15:8]
|
| 453 |
|
|
* I2S Input 1 volume Right [23:16]
|
| 454 |
|
|
* I2S Input 1 volume Left [31:24]
|
| 455 |
|
|
*/
|
| 456 |
|
|
/* Sample rate output control register Channel=2
|
| 457 |
|
|
* SPDIF Input volume Right [23:16]
|
| 458 |
|
|
* SPDIF Input volume Left [31:24]
|
| 459 |
|
|
*/
|
| 460 |
|
|
/* Sample rate output control register Channel=3
|
| 461 |
|
|
* No used
|
| 462 |
|
|
*/
|
| 463 |
|
|
#define SPDIF_SELECT2 0x72 /* Some sort of routing. Channel_id 0 only. default = 0x0f0f003f. Analog 0x000b0000, Digital 0x0b000000 */
|
| 464 |
|
|
#define ROUTING2_FRONT_MASK 0x00010000 /* Enable for Front speakers. */
|
| 465 |
|
|
#define ROUTING2_CENTER_LFE_MASK 0x00020000 /* Enable for Center/LFE speakers. */
|
| 466 |
|
|
#define ROUTING2_REAR_MASK 0x00080000 /* Enable for Rear speakers. */
|
| 467 |
|
|
/* Audio output control
|
| 468 |
|
|
* AC97 output enable [5:0]
|
| 469 |
|
|
* I2S output enable [19:16]
|
| 470 |
|
|
* SPDIF output enable [27:24]
|
| 471 |
|
|
*/
|
| 472 |
|
|
#define UNKNOWN73 0x73 /* Unknown. Readonly. Default 0x0 */
|
| 473 |
|
|
#define CHIP_VERSION 0x74 /* P17 Chip version. Channel_id 0 only. Default 00000071 */
|
| 474 |
|
|
#define EXTENDED_INT_MASK 0x75 /* Used by both playback and capture interrupt handler */
|
| 475 |
|
|
/* Sets which Interrupts are enabled. */
|
| 476 |
|
|
/* 0x00000001 = Half period. Playback.
|
| 477 |
|
|
* 0x00000010 = Full period. Playback.
|
| 478 |
|
|
* 0x00000100 = Half buffer. Playback.
|
| 479 |
|
|
* 0x00001000 = Full buffer. Playback.
|
| 480 |
|
|
* 0x00010000 = Half buffer. Capture.
|
| 481 |
|
|
* 0x00100000 = Full buffer. Capture.
|
| 482 |
|
|
* Capture can only do 2 periods.
|
| 483 |
|
|
* 0x01000000 = End audio. Playback.
|
| 484 |
|
|
* 0x40000000 = Half buffer Playback,Caputre xrun.
|
| 485 |
|
|
* 0x80000000 = Full buffer Playback,Caputre xrun.
|
| 486 |
|
|
*/
|
| 487 |
|
|
#define EXTENDED_INT 0x76 /* Used by both playback and capture interrupt handler */
|
| 488 |
|
|
/* Shows which interrupts are active at the moment. */
|
| 489 |
|
|
/* Same bit layout as EXTENDED_INT_MASK */
|
| 490 |
|
|
#define COUNTER77 0x77 /* Counter range 0 to 0x3fffff, 192000 counts per second. */
|
| 491 |
|
|
#define COUNTER78 0x78 /* Counter range 0 to 0x3fffff, 44100 counts per second. */
|
| 492 |
|
|
#define EXTENDED_INT_TIMER 0x79 /* Channel_id 0 only. Used by both playback and capture interrupt handler */
|
| 493 |
|
|
/* Causes interrupts based on timer intervals. */
|
| 494 |
|
|
#define SPI 0x7a /* SPI: Serial Interface Register */
|
| 495 |
|
|
#define I2C_A 0x7b /* I2C Address. 32 bit */
|
| 496 |
|
|
#define I2C_D0 0x7c /* I2C Data Port 0. 32 bit */
|
| 497 |
|
|
#define I2C_D1 0x7d /* I2C Data Port 1. 32 bit */
|
| 498 |
|
|
//I2C values
|
| 499 |
|
|
#define I2C_A_ADC_ADD_MASK 0x000000fe //The address is a 7 bit address
|
| 500 |
|
|
#define I2C_A_ADC_RW_MASK 0x00000001 //bit mask for R/W
|
| 501 |
|
|
#define I2C_A_ADC_TRANS_MASK 0x00000010 //Bit mask for I2c address DAC value
|
| 502 |
|
|
#define I2C_A_ADC_ABORT_MASK 0x00000020 //Bit mask for I2C transaction abort flag
|
| 503 |
|
|
#define I2C_A_ADC_LAST_MASK 0x00000040 //Bit mask for Last word transaction
|
| 504 |
|
|
#define I2C_A_ADC_BYTE_MASK 0x00000080 //Bit mask for Byte Mode
|
| 505 |
|
|
|
| 506 |
|
|
#define I2C_A_ADC_ADD 0x00000034 //This is the Device address for ADC
|
| 507 |
|
|
#define I2C_A_ADC_READ 0x00000001 //To perform a read operation
|
| 508 |
|
|
#define I2C_A_ADC_START 0x00000100 //Start I2C transaction
|
| 509 |
|
|
#define I2C_A_ADC_ABORT 0x00000200 //I2C transaction abort
|
| 510 |
|
|
#define I2C_A_ADC_LAST 0x00000400 //I2C last transaction
|
| 511 |
|
|
#define I2C_A_ADC_BYTE 0x00000800 //I2C one byte mode
|
| 512 |
|
|
|
| 513 |
|
|
#define I2C_D_ADC_REG_MASK 0xfe000000 //ADC address register
|
| 514 |
|
|
#define I2C_D_ADC_DAT_MASK 0x01ff0000 //ADC data register
|
| 515 |
|
|
|
| 516 |
|
|
#define ADC_TIMEOUT 0x00000007 //ADC Timeout Clock Disable
|
| 517 |
|
|
#define ADC_IFC_CTRL 0x0000000b //ADC Interface Control
|
| 518 |
|
|
#define ADC_MASTER 0x0000000c //ADC Master Mode Control
|
| 519 |
|
|
#define ADC_POWER 0x0000000d //ADC PowerDown Control
|
| 520 |
|
|
#define ADC_ATTEN_ADCL 0x0000000e //ADC Attenuation ADCL
|
| 521 |
|
|
#define ADC_ATTEN_ADCR 0x0000000f //ADC Attenuation ADCR
|
| 522 |
|
|
#define ADC_ALC_CTRL1 0x00000010 //ADC ALC Control 1
|
| 523 |
|
|
#define ADC_ALC_CTRL2 0x00000011 //ADC ALC Control 2
|
| 524 |
|
|
#define ADC_ALC_CTRL3 0x00000012 //ADC ALC Control 3
|
| 525 |
|
|
#define ADC_NOISE_CTRL 0x00000013 //ADC Noise Gate Control
|
| 526 |
|
|
#define ADC_LIMIT_CTRL 0x00000014 //ADC Limiter Control
|
| 527 |
|
|
#define ADC_MUX 0x00000015 //ADC Mux offset
|
| 528 |
|
|
|
| 529 |
|
|
#if 0
|
| 530 |
|
|
/* FIXME: Not tested yet. */
|
| 531 |
|
|
#define ADC_GAIN_MASK 0x000000ff //Mask for ADC Gain
|
| 532 |
|
|
#define ADC_ZERODB 0x000000cf //Value to set ADC to 0dB
|
| 533 |
|
|
#define ADC_MUTE_MASK 0x000000c0 //Mask for ADC mute
|
| 534 |
|
|
#define ADC_MUTE 0x000000c0 //Value to mute ADC
|
| 535 |
|
|
#define ADC_OSR 0x00000008 //Mask for ADC oversample rate select
|
| 536 |
|
|
#define ADC_TIMEOUT_DISABLE 0x00000008 //Value and mask to disable Timeout clock
|
| 537 |
|
|
#define ADC_HPF_DISABLE 0x00000100 //Value and mask to disable High pass filter
|
| 538 |
|
|
#define ADC_TRANWIN_MASK 0x00000070 //Mask for Length of Transient Window
|
| 539 |
|
|
#endif
|
| 540 |
|
|
|
| 541 |
|
|
#define ADC_MUX_MASK 0x0000000f //Mask for ADC Mux
|
| 542 |
|
|
#define ADC_MUX_PHONE 0x00000001 //Value to select TAD at ADC Mux (Not used)
|
| 543 |
|
|
#define ADC_MUX_MIC 0x00000002 //Value to select Mic at ADC Mux
|
| 544 |
|
|
#define ADC_MUX_LINEIN 0x00000004 //Value to select LineIn at ADC Mux
|
| 545 |
|
|
#define ADC_MUX_AUX 0x00000008 //Value to select Aux at ADC Mux
|
| 546 |
|
|
|
| 547 |
|
|
#define SET_CHANNEL 0 /* Testing channel outputs 0=Front, 1=Center/LFE, 2=Unknown, 3=Rear */
|
| 548 |
|
|
#define PCM_FRONT_CHANNEL 0
|
| 549 |
|
|
#define PCM_REAR_CHANNEL 1
|
| 550 |
|
|
#define PCM_CENTER_LFE_CHANNEL 2
|
| 551 |
|
|
#define PCM_UNKNOWN_CHANNEL 3
|
| 552 |
|
|
#define CONTROL_FRONT_CHANNEL 0
|
| 553 |
|
|
#define CONTROL_REAR_CHANNEL 3
|
| 554 |
|
|
#define CONTROL_CENTER_LFE_CHANNEL 1
|
| 555 |
|
|
#define CONTROL_UNKNOWN_CHANNEL 2
|
| 556 |
|
|
|
| 557 |
|
|
|
| 558 |
|
|
/* Based on WM8768 Datasheet Rev 4.2 page 32 */
|
| 559 |
|
|
#define SPI_REG_MASK 0x1ff /* 16-bit SPI writes have a 7-bit address */
|
| 560 |
|
|
#define SPI_REG_SHIFT 9 /* followed by 9 bits of data */
|
| 561 |
|
|
|
| 562 |
|
|
#define SPI_LDA1_REG 0 /* digital attenuation */
|
| 563 |
|
|
#define SPI_RDA1_REG 1
|
| 564 |
|
|
#define SPI_LDA2_REG 4
|
| 565 |
|
|
#define SPI_RDA2_REG 5
|
| 566 |
|
|
#define SPI_LDA3_REG 6
|
| 567 |
|
|
#define SPI_RDA3_REG 7
|
| 568 |
|
|
#define SPI_LDA4_REG 13
|
| 569 |
|
|
#define SPI_RDA4_REG 14
|
| 570 |
|
|
#define SPI_MASTDA_REG 8
|
| 571 |
|
|
|
| 572 |
|
|
#define SPI_DA_BIT_UPDATE (1<<8) /* update attenuation values */
|
| 573 |
|
|
#define SPI_DA_BIT_0dB 0xff /* 0 dB */
|
| 574 |
|
|
#define SPI_DA_BIT_infdB 0x00 /* inf dB attenuation (mute) */
|
| 575 |
|
|
|
| 576 |
|
|
#define SPI_PL_REG 2
|
| 577 |
|
|
#define SPI_PL_BIT_L_M (0<<5) /* left channel = mute */
|
| 578 |
|
|
#define SPI_PL_BIT_L_L (1<<5) /* left channel = left */
|
| 579 |
|
|
#define SPI_PL_BIT_L_R (2<<5) /* left channel = right */
|
| 580 |
|
|
#define SPI_PL_BIT_L_C (3<<5) /* left channel = (L+R)/2 */
|
| 581 |
|
|
#define SPI_PL_BIT_R_M (0<<7) /* right channel = mute */
|
| 582 |
|
|
#define SPI_PL_BIT_R_L (1<<7) /* right channel = left */
|
| 583 |
|
|
#define SPI_PL_BIT_R_R (2<<7) /* right channel = right */
|
| 584 |
|
|
#define SPI_PL_BIT_R_C (3<<7) /* right channel = (L+R)/2 */
|
| 585 |
|
|
#define SPI_IZD_REG 2
|
| 586 |
|
|
#define SPI_IZD_BIT (1<<4) /* infinite zero detect */
|
| 587 |
|
|
|
| 588 |
|
|
#define SPI_FMT_REG 3
|
| 589 |
|
|
#define SPI_FMT_BIT_RJ (0<<0) /* right justified mode */
|
| 590 |
|
|
#define SPI_FMT_BIT_LJ (1<<0) /* left justified mode */
|
| 591 |
|
|
#define SPI_FMT_BIT_I2S (2<<0) /* I2S mode */
|
| 592 |
|
|
#define SPI_FMT_BIT_DSP (3<<0) /* DSP Modes A or B */
|
| 593 |
|
|
#define SPI_LRP_REG 3
|
| 594 |
|
|
#define SPI_LRP_BIT (1<<2) /* invert LRCLK polarity */
|
| 595 |
|
|
#define SPI_BCP_REG 3
|
| 596 |
|
|
#define SPI_BCP_BIT (1<<3) /* invert BCLK polarity */
|
| 597 |
|
|
#define SPI_IWL_REG 3
|
| 598 |
|
|
#define SPI_IWL_BIT_16 (0<<4) /* 16-bit world length */
|
| 599 |
|
|
#define SPI_IWL_BIT_20 (1<<4) /* 20-bit world length */
|
| 600 |
|
|
#define SPI_IWL_BIT_24 (2<<4) /* 24-bit world length */
|
| 601 |
|
|
#define SPI_IWL_BIT_32 (3<<4) /* 32-bit world length */
|
| 602 |
|
|
|
| 603 |
|
|
#define SPI_MS_REG 10
|
| 604 |
|
|
#define SPI_MS_BIT (1<<5) /* master mode */
|
| 605 |
|
|
#define SPI_RATE_REG 10 /* only applies in master mode */
|
| 606 |
|
|
#define SPI_RATE_BIT_128 (0<<6) /* MCLK = LRCLK * 128 */
|
| 607 |
|
|
#define SPI_RATE_BIT_192 (1<<6)
|
| 608 |
|
|
#define SPI_RATE_BIT_256 (2<<6)
|
| 609 |
|
|
#define SPI_RATE_BIT_384 (3<<6)
|
| 610 |
|
|
#define SPI_RATE_BIT_512 (4<<6)
|
| 611 |
|
|
#define SPI_RATE_BIT_768 (5<<6)
|
| 612 |
|
|
|
| 613 |
|
|
/* They really do label the bit for the 4th channel "4" and not "3" */
|
| 614 |
|
|
#define SPI_DMUTE0_REG 9
|
| 615 |
|
|
#define SPI_DMUTE1_REG 9
|
| 616 |
|
|
#define SPI_DMUTE2_REG 9
|
| 617 |
|
|
#define SPI_DMUTE4_REG 15
|
| 618 |
|
|
#define SPI_DMUTE0_BIT (1<<3)
|
| 619 |
|
|
#define SPI_DMUTE1_BIT (1<<4)
|
| 620 |
|
|
#define SPI_DMUTE2_BIT (1<<5)
|
| 621 |
|
|
#define SPI_DMUTE4_BIT (1<<2)
|
| 622 |
|
|
|
| 623 |
|
|
#define SPI_PHASE0_REG 3
|
| 624 |
|
|
#define SPI_PHASE1_REG 3
|
| 625 |
|
|
#define SPI_PHASE2_REG 3
|
| 626 |
|
|
#define SPI_PHASE4_REG 15
|
| 627 |
|
|
#define SPI_PHASE0_BIT (1<<6)
|
| 628 |
|
|
#define SPI_PHASE1_BIT (1<<7)
|
| 629 |
|
|
#define SPI_PHASE2_BIT (1<<8)
|
| 630 |
|
|
#define SPI_PHASE4_BIT (1<<3)
|
| 631 |
|
|
|
| 632 |
|
|
#define SPI_PDWN_REG 2 /* power down all DACs */
|
| 633 |
|
|
#define SPI_PDWN_BIT (1<<2)
|
| 634 |
|
|
#define SPI_DACD0_REG 10 /* power down individual DACs */
|
| 635 |
|
|
#define SPI_DACD1_REG 10
|
| 636 |
|
|
#define SPI_DACD2_REG 10
|
| 637 |
|
|
#define SPI_DACD4_REG 15
|
| 638 |
|
|
#define SPI_DACD0_BIT (1<<1)
|
| 639 |
|
|
#define SPI_DACD1_BIT (1<<2)
|
| 640 |
|
|
#define SPI_DACD2_BIT (1<<3)
|
| 641 |
|
|
#define SPI_DACD4_BIT (1<<0) /* datasheet error says it's 1 */
|
| 642 |
|
|
|
| 643 |
|
|
#define SPI_PWRDNALL_REG 10 /* power down everything */
|
| 644 |
|
|
#define SPI_PWRDNALL_BIT (1<<4)
|
| 645 |
|
|
|
| 646 |
|
|
#include "ca_midi.h"
|
| 647 |
|
|
|
| 648 |
|
|
struct snd_ca0106;
|
| 649 |
|
|
|
| 650 |
|
|
struct snd_ca0106_channel {
|
| 651 |
|
|
struct snd_ca0106 *emu;
|
| 652 |
|
|
int number;
|
| 653 |
|
|
int use;
|
| 654 |
|
|
void (*interrupt)(struct snd_ca0106 *emu, struct snd_ca0106_channel *channel);
|
| 655 |
|
|
struct snd_ca0106_pcm *epcm;
|
| 656 |
|
|
};
|
| 657 |
|
|
|
| 658 |
|
|
struct snd_ca0106_pcm {
|
| 659 |
|
|
struct snd_ca0106 *emu;
|
| 660 |
|
|
struct snd_pcm_substream *substream;
|
| 661 |
|
|
int channel_id;
|
| 662 |
|
|
unsigned short running;
|
| 663 |
|
|
};
|
| 664 |
|
|
|
| 665 |
|
|
struct snd_ca0106_details {
|
| 666 |
|
|
u32 serial;
|
| 667 |
|
|
char * name;
|
| 668 |
|
|
int ac97;
|
| 669 |
|
|
int gpio_type;
|
| 670 |
|
|
int i2c_adc;
|
| 671 |
|
|
int spi_dac;
|
| 672 |
|
|
};
|
| 673 |
|
|
|
| 674 |
|
|
// definition of the chip-specific record
|
| 675 |
|
|
struct snd_ca0106 {
|
| 676 |
|
|
struct snd_card *card;
|
| 677 |
|
|
struct snd_ca0106_details *details;
|
| 678 |
|
|
struct pci_dev *pci;
|
| 679 |
|
|
|
| 680 |
|
|
unsigned long port;
|
| 681 |
|
|
struct resource *res_port;
|
| 682 |
|
|
int irq;
|
| 683 |
|
|
|
| 684 |
|
|
unsigned int serial; /* serial number */
|
| 685 |
|
|
unsigned short model; /* subsystem id */
|
| 686 |
|
|
|
| 687 |
|
|
spinlock_t emu_lock;
|
| 688 |
|
|
|
| 689 |
|
|
struct snd_ac97 *ac97;
|
| 690 |
|
|
struct snd_pcm *pcm;
|
| 691 |
|
|
|
| 692 |
|
|
struct snd_ca0106_channel playback_channels[4];
|
| 693 |
|
|
struct snd_ca0106_channel capture_channels[4];
|
| 694 |
|
|
u32 spdif_bits[4]; /* s/pdif out setup */
|
| 695 |
|
|
int spdif_enable;
|
| 696 |
|
|
int capture_source;
|
| 697 |
|
|
int i2c_capture_source;
|
| 698 |
|
|
u8 i2c_capture_volume[4][2];
|
| 699 |
|
|
int capture_mic_line_in;
|
| 700 |
|
|
|
| 701 |
|
|
struct snd_dma_buffer buffer;
|
| 702 |
|
|
|
| 703 |
|
|
struct snd_ca_midi midi;
|
| 704 |
|
|
struct snd_ca_midi midi2;
|
| 705 |
|
|
|
| 706 |
|
|
u16 spi_dac_reg[16];
|
| 707 |
|
|
};
|
| 708 |
|
|
|
| 709 |
|
|
int snd_ca0106_mixer(struct snd_ca0106 *emu);
|
| 710 |
|
|
int snd_ca0106_proc_init(struct snd_ca0106 * emu);
|
| 711 |
|
|
|
| 712 |
|
|
unsigned int snd_ca0106_ptr_read(struct snd_ca0106 * emu,
|
| 713 |
|
|
unsigned int reg,
|
| 714 |
|
|
unsigned int chn);
|
| 715 |
|
|
|
| 716 |
|
|
void snd_ca0106_ptr_write(struct snd_ca0106 *emu,
|
| 717 |
|
|
unsigned int reg,
|
| 718 |
|
|
unsigned int chn,
|
| 719 |
|
|
unsigned int data);
|
| 720 |
|
|
|
| 721 |
|
|
int snd_ca0106_i2c_write(struct snd_ca0106 *emu, u32 reg, u32 value);
|
| 722 |
|
|
|
| 723 |
|
|
int snd_ca0106_spi_write(struct snd_ca0106 * emu,
|
| 724 |
|
|
unsigned int data);
|
