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URL https://opencores.org/ocsvn/or1k_soc_on_altera_embedded_dev_kit/or1k_soc_on_altera_embedded_dev_kit/trunk

Subversion Repositories or1k_soc_on_altera_embedded_dev_kit

[/] [or1k_soc_on_altera_embedded_dev_kit/] [trunk/] [soc/] [bench/] [ATMEL_FLASH/] [flash_verilog/] [flash_verilog_w_wo_hold/] [run.csh] - Blame information for rev 12

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Line No. Rev Author Line
1 12 xianfeng 
# for MODE0 operation
2 
vcs -R -PP +define+041 +vcs+lic+wait -f filelist.v -l at26x.log
3 
#vcs -R -PP +define+081 +vcs+lic+wait -f filelist.v -l at26x.log
4 
#vcs -R -PP +define+161 +vcs+lic+wait -f filelist.v -l at26x.log
5 
#vcs -R -PP +define+321 +vcs+lic+wait -f filelist.v -l at26x.log
6 
 
7 
# for MODE3 operation
8 
#vcs -R -PP +define+041+MODE3 +vcs+lic+wait -f filelist.v -l at26x.log
9 
#vcs -R -PP +define+081+MODE3 +vcs+lic+wait -f filelist.v -l at26x.log
10 
#vcs -R -PP +define+161+MODE3 +vcs+lic+wait -f filelist.v -l at26x.log
11 
#vcs -R -PP +define+321+MODE3 +vcs+lic+wait -f filelist.v -l at26x.log
12 
 
13 
# for memory preloading in the cards
14 
# for MODE0 operation
15 
#vcs -R -PP +define+041+LOAD +vcs+lic+wait -f filelist.v -l at26x.log
16 
#vcs -R -PP +define+081+LOAD +vcs+lic+wait -f filelist.v -l at26x.log
17 
#vcs -R -PP +define+161+LOAD +vcs+lic+wait -f filelist.v -l at26x.log
18 
#vcs -R -PP +define+321+LOAD +vcs+lic+wait -f filelist.v -l at26x.log
19 
 
20 
# for MODE3 operation
21 
#vcs -R -PP +define+041+MODE3+LOAD +vcs+lic+wait -f filelist.v -l at26x.log
22 
#vcs -R -PP +define+081+MODE3+LOAD +vcs+lic+wait -f filelist.v -l at26x.log
23 
#vcs -R -PP +define+161+MODE3+LOAD +vcs+lic+wait -f filelist.v -l at26x.log
24 
#vcs -R -PP +define+321+MODE3+LOAD +vcs+lic+wait -f filelist.v -l at26x.log

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